CS 152 Computer Architecture and Engineering CS252 Graduate Computer Architecture. Lecture 9 Virtual Memory

Transcription

1 CS 152 Computer Architecture and Engineering CS252 Graduate Computer Architecture Lecture 9 Virtual Memory Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley

2 in Lecture 8 Protec=on and transla=on required for mul=programming Base and bounds was early simple scheme Page-based transla=on and protec=on avoids need for memory compac=on, easy alloca=on by OS But need to indirect in large page table on every access Address spaces accessed sparsely Can use mul=-level page table to hold transla=on/protec=on informa=on, but implies mul=ple memory accesses per reference Address space access with locality Can use transla=on lookaside buffer () to cache address transla=ons (some=mes known as address transla=on cache) S=ll have to walk page tables on miss, can be hardware or sonware talk Virtual memory uses DRAM as a cache of disk memory, allows very cheap main memory 2

3 Modern Virtual Memory Systems Illusion of a large, private, uniform store Protec=on & Privacy several users, each with their private address space and one or more shared address spaces page table name space OS user i Demand Paging Provides the ability to run programs larger than the primary memory Primary Memory Secondary Storage Hides differences in machine configura=ons The price is address transla/on on each memory reference VA mapping PA 3

4 Recap: Hierarchical Page Table Virtual Address p1 p2 offset 10-bit L1 index Root of Current Page Table (Processor Register) 10-bit L2 index p1 Level 1 Page Table page in primary memory page in secondary memory PTE of a nonexistent page p2 Level 2 Page Tables offset Pages Physical Memory 4

5 PC Recap: Page-Based Virtual-Memory Machine (Hardware Page-Table Walk) Page Fault? Protec/on viola/on? Virtual Address Inst. Physical Address Inst. Cache D Decode E + M Page Fault? Protec/on viola/on? Virtual Address Physical Address Cache W Miss? Page-Table Base Register Miss? Hardware Page Table Walker Physical Address Memory Controller Physical Address Physical Address Main Memory (DRAM) Assumes page tables held in untranslated physical memory 5

6 Address pu3ng it all together Virtual Address Lookup hardware hardware or sonware sonware miss hit Page Table Walk Protec=on Check the page is memory memory denied permi^ed Where? Page Fault (OS loads page) Update SEGFAULT Protec=on Fault Physical Address (to cache) 6

7 Page Fault Handler When the referenced page is not in DRAM: The missing page is located (or created) It is brought in from disk, and page table is updated Another job may be run on the CPU while the first job waits for the requested page to be read from disk If no free pages are len, a page is swapped out Pseudo-LRU replacement policy, implemented in sonware Since it takes a long =me to transfer a page (msecs), page faults are handled completely in sonware by the OS Untranslated addressing mode is essen=al to allow kernel to access page tables 7

8 Handling VM-related PC Inst Inst. Cache D Decode E + M Cache W miss? Page Fault? Protec/on viola/on? Handling a miss needs a hardware or sonware mechanism to refill Handling page fault (e.g., page is on disk) needs restartable excep=on so sonware handler can resume aner retrieving page Precise excep=ons are easy to restart Can be imprecise but restartable, but this complicates OS sonware A protec=on viola=on may abort process But onen handled the same as a page fault miss? Page Fault? Protec/on viola/on? 8

9 Address in CPU Pipeline PC Inst Inst. Cache D Decode E + M Cache W miss? Page Fault? Protec/on viola/on? miss? Page Fault? Protec/on viola/on? Need to cope with addi=onal latency of : slow down the clock? pipeline the and cache access? virtual address caches parallel /cache access 9

10 Virtual-Address Caches CPU VA PA Physical PA Cache Primary Memory Alternative: place the cache before the CPU VA Virtual Cache VA PA Primary Memory (StrongARM) one-step process in case of a hit (+) cache needs to be flushed on a context switch unless address space iden=fiers (ASIDs) included in tags (-) aliasing problems due to the sharing of pages (-) maintaining cache coherence (-) 10

11 Virtually Addressed Cache (Virtual Index/Virtual Tag) Virtual Address Virtual Address PC Physical Address Inst. Cache D Decode E + M Miss? Inst. Instruc=on data Translate on miss P Register Memory Controller Main Memory (DRAM) Cache Hardware Page Table Walker Physical Address Miss? W Physical Address 11

12 Aliasing in Virtual-Address Caches Page Table Tag VA 1 Pages VA 1 1st Copy of at PA PA VA 2 2nd Copy of at PA VA 2 Two virtual pages share one physical page Virtual cache can have two copies of same physical data. Writes to one copy not visible to reads of other! General Solu=on: Prevent aliases coexis/ng in cache SoNware (i.e., OS) solu=on for direct-mapped cache VAs of shared pages must agree in cache index bits; this ensures all VAs accessing same PA will conflict in direct-mapped cache (early SPARCs) 12

13 Concurrent Access to & Cache (Virtual Index/Physical Tag) VA PA VPN L b k PPN Page Offset Virtual Index Direct-map Cache 2 L blocks 2 b -byte block Tag hit? Index L is available without consul=ng the cache and accesses can begin simultaneously! Tag comparison is made aner both accesses are completed Cases: L + b = k, L + b < k, L + b > k = Physical Tag 13

14 Virtual-Index Physical-Tag Caches: VA VPN a L = k-b b 2 a Virtual Index k Direct-map 2 L blocks Direct-map 2 L blocks PA PPN Tag Page Offset = hit? Phy. Tag 2 a = ANer the PPN is known, 2 a physical tags are compared How does this scheme scale to larger caches? 14

15 CS152 Administrivia PS 2 due Wednesday Feb 21 Lab 2 out on Friday in Sec=on Midterm in class Monday Feb 26 Covers lectures 1 9, plus assigned problem sets, labs, readings No lecture Monday Feb 19 President s Day Holiday 15

16 CS252 Administrivia Start thinking of class projects and forming teams of two Proposal due Monday March 5 th Proposal should be one page PDF including: Title Team member names What are you trying to do? How is it done today? What is your idea for improvement and why do you think you ll be successful What infrastructure are you going to use for your project? Project =meline with milestones Mail PDF of proposal to instructors Give a <5-minute presenta=on in class in discussion sec=on =me on March 5 th CS252 16

17 Concurrent Access to & Large L1 The problem with L1 > Page size VA VPN a Page Offset b Virtual Index L1 PA cache Direct-map VA 1 VA 2 PPN a PPN a PA PPN Page Offset b Tag Can VA 1 and VA 2 both map to PA? = hit? 17

18 A via Second-Level Cache CPU RF L1 Instruc=on Cache L1 Cache Unified L2 Cache Memory Memory Memory Memory Usually a common L2 cache backs up both Instruc=on and L1 caches L2 is inclusive of both Instruc=on and caches Inclusive means L2 has copy of any line in either L1 18

19 VA Using L2 [MIPS R10000,1996] VPN a Page Offset b into L2 tag Virtual Index VA 1 VA 2 PPN a PPN a L1 PA cache Direct-map PA PPN Page Offset b Tag Suppose VA1 and VA2 both map to PA and VA1 is already in L1, L2 (VA1 VA2) ANer VA2 is resolved to PA, a collision will be detected in L2. VA1 will be purged from L1 and L2, and VA2 will be loaded no aliasing! PPN = hit? PA a 1 Direct-Mapped L2 19

20 using L2 for a Virtually Addressed L1 VA PA VPN Page Offset b PPN Page Offset b Virtual Index & Tag VA 1 VA 2 L1 VA Cache Tag Physical Index & Tag Physically-addressed L2 can also be used to avoid aliases in virtuallyaddressed L1 PA VA 1 Virtual Tag L2 PA Cache L2 contains L1 20

21 Atlas Revisited One PAR for each physical page PAR s contain the VPN s of the pages resident in primary memory PAR s Advantage: The size is propor=onal to the size of the primary memory PPN VPN What is the disadvantage? CS252 21

22 Hashed Page Table: Addressing PID VPN d Virtual Address Offset hash + PA of PTE Page Table Base of Table Hashed Page Table is typically 2 to 3 =mes larger than the number of PPN s to reduce collision probability It can also contain DPN s for some non-resident pages (not common) If a transla=on cannot be resolved in this table then the sonware consults a data structure that has an entry for every exis=ng page (e.g., full page table) CS252 VPN PID PPN VPN PID DPN VPN PID Primary Memory 22

23 Power PC: Hashed Page Table Base of Table Each hash table slot has 8 PTE's <VPN,PPN> that are searched sequen=ally If the first hash slot fails, an alternate hash func=on is used to look in another slot All these steps are done in hardware! Hashed Table is typically 2 to 3 =mes larger than the number of physical pages The full backup Page Table is managed in sonware CS252 VPN d 80-bit VA hash Offset + PA of Slot Page Table VPN VPN PPN Primary Memory 23

24 VM features track historical uses: Bare machine, only physical addresses One program owned en=re machine Batch-style mul=programming Several programs sharing CPU while wai=ng for I/O Base & bound: transla=on and protec=on between programs (supports swapping en=re programs but not demand-paged virtual memory) Problem with external fragmenta=on (holes in memory), needed occasional memory defragmenta=on as new jobs arrived Time sharing More interac=ve programs, wai=ng for user. Also, more jobs/second. Mo=vated move to fixed-size page transla=on and protec=on, no external fragmenta=on (but now internal fragmenta=on, wasted bytes in page) Mo=vated adop=on of virtual memory to allow more jobs to share limited physical memory resources while holding working set in memory Virtual Machine Monitors Run mul=ple opera=ng systems on one machine Idea from 1970s IBM mainframes, now common on laptops e.g., run Windows on top of Mac OS X Hardware support for two levels of transla=on/protec=on Guest OS virtual -> Guest OS physical -> Host machine physical 24

25 Virtual Memory Use Today - 1 Servers/desktops/laptops/smartphones have full demandpaged virtual memory Portability between machines with different memory sizes Protec=on between mul=ple users or mul=ple tasks Share small physical memory among ac=ve tasks Simplifies implementa=on of some OS features Vector supercomputers have transla=on and protec=on but rarely complete demand-paging (Older Crays: base&bound, Japanese & Cray X1/X2: pages) Don t waste expensive CPU =me thrashing to disk (make jobs fit in memory) Mostly run in batch mode (run set of jobs that fits in memory) Difficult to implement restartable vector instruc=ons 25

26 Virtual Memory Use Today - 2 Most embedded processors and DSPs provide physical addressing only Can t afford area/speed/power budget for virtual memory support ONen there is no secondary storage to swap to! Programs custom wri^en for par=cular memory configura=on in product Difficult to implement restartable instruc=ons for exposed architectures 26

27 Acknowledgements This course is partly inspired by previous MIT and Berkeley CS252 computer architecture courses created by my collaborators and colleagues: Arvind (MIT) Joel Emer (Intel/MIT) James Hoe (CMU) John Kubiatowicz (UCB) David Pa^erson (UCB) 27