CS 152 Computer Architecture and Engineering. Lecture 9 - Virtual Memory. Last?me in Lecture 9

Transcription

1 CS 152 Computer Architecture and Engineering Lecture 9 - Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley Last?me in Lecture 9 ProtecDon and transladon required for muldprogramming Base and bounds was early simple scheme Page- based transladon and protecdon avoids need for memory compacdon, easy allocadon by OS But need to indirect in large page table on every access spaces accessed sparsely Can use muld- level page table to hold transladon/protecdon informadon, but implies muldple memory accesses per reference space access with locality Can use transladon lookaside buffer () to cache address transladons (somedmes known as address transladon cache) SDll have to walk page tables on miss, can be hardware or sosware talk memory uses DRAM as a cache of disk memory, allows very cheap main memory 2 CS252 S05 1

2 Management Can separate into orthogonal funcdons: TranslaDon (mapping of virtual address to physical address) ProtecDon (permission to access word in memory) memory (transparent extension of memory space using slower disk or flash storage) But most modern systems provide support for all the above funcdons with a single page- based system 3 Modern Systems Illusion of a large, private, uniform store ProtecDon & Privacy several users, each with their private address space and one or more shared address spaces page table name space Demand Paging Provides the ability to run programs larger than the primary memory Hides differences in machine configuradons Primary OS user i Secondary Storage The price is address transla/on on each memory reference VA mapping 4 CS252 S05 2

3 Hierarchical Page Table p1 p2 offset 10- bit L1 index Root of Current Page Table (Processor Register) 10- bit L2 index p1 Level 1 Page Table page in primary memory page in secondary memory PTE of a nonexistent page p2 Level 2 Page Tables offset Pages 5 PC Page- Based - Machine Page Fault? Protec/on viola/on? Inst. (Hardware Page- Table Walk) Inst. D Decode E + M Page Fault? Protec/on viola/on? W Miss? Page- Table Base Register Miss? Hardware Page Table Walker Controller Main (DRAM) Assumes page tables held in untranslated physical memory 6 CS252 S05 3

4 Transla?on: pu3ng it all together miss Lookup hit hardware hardware or sosware sosware Page Table Walk ProtecDon Check the page is memory memory denied permibed Where? Page Fault (OS loads page) Update SEGFAULT ProtecDon Fault (to cache) 7 Page Fault Handler When the referenced page is not in DRAM: The missing page is located (or created) It is brought in from disk, and page table is updated Another job may be run on the CPU while the first job waits for the requested page to be read from disk If no free pages are les, a page is swapped out Pseudo- LRU replacement policy, implemented in sosware Since it takes a long Dme to transfer a page (msecs), page faults are handled completely in sosware by the OS Untranslated addressing mode is essendal to allow kernel to access page tables 8 CS252 S05 4

5 Handling VM- related excep?ons PC Inst Inst. D Decode E + M W miss? Page Fault? Protec/on viola/on? miss? Page Fault? Protec/on viola/on? Handling a miss needs a hardware or sosware mechanism to refill Handling a page fault (e.g., page is on disk) needs a restartable excepdon so sosware handler can resume aser retrieving page Precise excepdons are easy to restart Can be imprecise but restartable, but this complicates OS sosware Handling protecdon violadon may abort process But osen handled the same as a page fault 9 Transla?on in CPU Pipeline PC Inst Inst. D Decode E + M W miss? Page Fault? Protec/on viola/on? miss? Page Fault? Protec/on viola/on? Need to cope with addidonal latency of : slow down the clock? pipeline the and cache access? virtual address caches parallel /cache access 10 CS252 S05 5

6 - s CPU VA Primary Alternative: place the cache before the CPU VA VA Primary (StrongARM) one- step process in case of a hit (+) cache needs to be flushed on a context switch unless address space idendfiers (ASIDs) included in tags (- ) aliasing problems due to the sharing of pages (- ) maintaining cache coherence (- ) (see later in course) 11 ly ed ( Index/ Tag) PC Inst. D Decode E + M Miss? Inst. InstrucDon data Translate on miss P Register Controller Main (DRAM) Hardware Page Table Walker Miss? W 12 CS252 S05 6

7 Aliasing in - s VA 1 Page Table Pages Tag VA 1 1st Copy of at VA 2 2nd Copy of at VA 2 Two virtual pages share one physical page cache can have two copies of same physical data. Writes to one copy not visible to reads of other! General SoluDon: Prevent aliases coexis/ng in cache SoSware (i.e., OS) soludon for direct- mapped cache VAs of shared pages must agree in cache index bits; this ensures all VAs accessing same will conflict in direct- mapped cache (early SRCs) 13 Concurrent Access to & ( Index/ Tag) VA VPN L b k PPN Page Offset Index Direct- map 2 L blocks 2 b - byte block Tag hit? Index L is available without consuldng the cache and accesses can begin simultaneously! Tag comparison is made aser both accesses are completed Cases: L + b = k, L + b < k, L + b > k = Tag 14 CS252 S05 7

8 - Index - Tag s: Associa?ve Organiza?on VA VPN a L = k- b b 2 a Index k Direct- map 2 L blocks Direct- map 2 L blocks PPN Tag Page Offset = hit? Phy. Tag 2 a = ASer the PPN is known, 2 a physical tags are compared How does this scheme scale to larger caches? 15 Concurrent Access to & Large L1 The problem with L1 > Page size VA Index VPN a Page Offset b VA 1 VA 2 PPN a PPN a L1 cache Direct- map PPN Page Offset b Tag Can VA 1 and VA 2 both map to? = hit? 16 CS252 S05 8

9 CS152 Administrivia PS 2 and Lab 2 out Short Dme frame only one week les Dll due so start soon Quiz 2, Tuesday March 5 Lectures 6-9, PS 2, Lab 2, readings 17 A solu?on via Second Level CPU RF L1 InstrucDon L1 Unified L2 Usually a common L2 cache backs up both InstrucDon and L1 caches L2 is inclusive of both InstrucDon and caches Inclusive means L2 has copy of any line in either L1 18 CS252 S05 9

10 VA An?- Aliasing Using L2 [MIPS R10000,1996] VPN a Page Offset b into L2 tag Index VA 1 VA 2 L1 cache Direct- map PPN a PPN a PPN Page Offset b Tag Suppose VA1 and VA2 both map to and VA1 is already in L1, L2 (VA1 VA2) ASer VA2 is resolved to, a collision will be detected in L2. VA1 will be purged from L1 and L2, and VA2 will be loaded no aliasing! PPN = hit? a 1 Direct- Mapped L2 19 An?- Aliasing using L2 for a ly ed L1 VA VPN Page Offset b PPN Page Offset b Index & Tag VA 1 VA 2 L1 VA Tag Index & Tag ly- addressed L2 can also be used to avoid aliases in virtually- addressed L1 VA 1 Tag L2 L2 contains L1 20 CS252 S05 10

11 Atlas Revisited One R for each physical page R s contain the VPN s of the pages resident in primary memory Advantage: The size is propordonal to the size of the primary memory PPN R s VPN What is the disadvantage? 21 Hashed Page Table: Approxima?ng Associa?ve ing PID VPN d Offset hash + of PTE Page Table Base of Table Hashed Page Table is typically 2 to 3 Dmes larger than the number of PPN s to reduce collision probability It can also contain DPN s for some non- resident pages (not common) If a transladon cannot be resolved in this table then the sosware consults a data structure that has an entry for every exisdng page (e.g., full page table) VPN PID PPN VPN PID DPN VPN PID Primary 22 CS252 S05 11

12 Power PC: Hashed Page Table VPN d 80- bit VA hash Base of Table Offset Each hash table slot has 8 PTE's <VPN,PPN> that are searched sequendally If the first hash slot fails, an alternate hash funcdon is used to look in another slot All these steps are done in hardware! Hashed Table is typically 2 to 3 Dmes larger than the number of physical pages The full backup Page Table is managed in sosware + of Slot Page Table VPN VPN PPN Primary 23 VM features track historical uses: Bare machine, only physical addresses One program owned endre machine Batch- style muldprogramming Several programs sharing CPU while waidng for I/O Base & bound: transladon and protecdon between programs (supports swapping endre programs but not demand- paged virtual memory) Problem with external fragmentadon (holes in memory), needed occasional memory defragmentadon as new jobs arrived Time sharing More interacdve programs, waidng for user. Also, more jobs/second. MoDvated move to fixed- size page transladon and protecdon, no external fragmentadon (but now internal fragmentadon, wasted bytes in page) MoDvated adopdon of virtual memory to allow more jobs to share limited physical memory resources while holding working set in memory Machine Monitors Run muldple operadng systems on one machine Idea from 1970s IBM mainframes, now common on laptops e.g., run Windows on top of Mac OS X Hardware support for two levels of transladon/protecdon Guest OS virtual - > Guest OS physical - > Host machine physical 24 CS252 S05 12

13 Use Today - 1 Servers/desktops/laptops/smartphones have full demand- paged virtual memory Portability between machines with different memory sizes ProtecDon between muldple users or muldple tasks Share small physical memory among acdve tasks Simplifies implementadon of some OS features Vector supercomputers have transladon and protecdon but rarely complete demand- paging (Older Crays: base&bound, Japanese & Cray X1/X2: pages) Don t waste expensive CPU Dme thrashing to disk (make jobs fit in memory) Mostly run in batch mode (run set of jobs that fits in memory) Difficult to implement restartable vector instrucdons 25 Use Today - 2 Most embedded processors and DSPs provide physical addressing only Can t afford area/speed/power budget for virtual memory support OSen there is no secondary storage to swap to! Programs custom wriben for pardcular memory configuradon in product Difficult to implement restartable instrucdons for exposed architectures 26 CS252 S05 13

14 Acknowledgements These slides contain material developed and copyright by: Arvind (MIT) Krste Asanovic (MIT/UCB) Joel Emer (Intel/MIT) James Hoe (CMU) John Kubiatowicz (UCB) David Paberson (UCB) MIT material derived from course UCB material derived from course CS CS252 S05 14