MONSOON IR Acquisition Board Test Procedures

Transcription

1 NATIONAL OPTICAL ASTRONOMY OBSERVATORY MAJOR INSTRUMENTATION GROUP 950 N. Cherry Ave. P. O. Box Tucson, Arizona (520) FAX: (520) MONSOON IR Acquisition Board Test Procedures NOAO Document MNSN-TS Revision: 0 Authored by: Peter Moore, John Garcia, Paul Schmitt, Nick C. Buchholz and Mark Hunten 3/31/2006 Please send comments: pmoore@noao.edu Page 1 of 13

2 Revision History Version Date Approved Sections Affected Remarks 0 4/5/2006 All Original Version Page 2 of 13

3 Table of Contents Revision History...2 Table of Contents Introduction Required Equipment Test Schedule Additional Tests Appendix Appendix I IR Acquisition Board FPD Programming Appendix II IR Acquisition Board Power Consumption Before Programming Power Consumption After Programming Power Consumption Appendix III - MEC Screen Shots Appendix IV - Analyzing and Correcting DHE Connection Problems...13 List of Figures Figure 1 - JTAG Device Chain...10 Figure 2 - MEC Screen after Connection, >reset> and >asyncresp>...13 List of Tables Table 1 - Test Description Conventions...4 Table 2 - JTAG Device Description and Load Files...11 Table 3 - Power Supply Requirements (before programming)...11 Table 4 - Power Supply Requirements (after programming)...12 Table 5 - Overcurrent Protection Settings for MCB plus IR Acquisition Boards...12 Page 3 of 13

4 2.1 Introduction This document covers the testing strategy for the MONSOON IR Acqisition Board to take the board from post-manufacture to a fully functional state. All tests described in this document pertain to the latest hardware revision level of the subject board. The tests described here do not prove that the board under test will meet specification but will test the full functionality of the board and identify failures that may result from component and manufacture problems. The test assumes the tester is familiar with the use of the MONSOON Engineering Console (MEC) and can execute the required commands. The tests are divided into progressive stages ranging from 1 to N. Each higher number stage uses assumptions of the board condition that requires the successful completion of the previous stages. Stage 1. Stage 2. Stage 3. Stage 4. Preparation of documentation. Board finishing to configure the board to meet specifications. Mechanical fit, power consumption and firmware programming tests. Additional tests for the Clock and Bias Board In the description for these tests, certain conventions are followed to ease comprehension. These conventions and examples of each are presented in Table 1. Table 1 Test Description Conventions Convention Example Description Linux commands that are typed on a Pixel Acquisition Node (PAN) xterm window mecstart Boldface characters Commands typed to the mec command line ppxsetavp Buttons on the Detector Head Electronics >startexp< (DHE) boards or MEC Boldface italics Bold italics underlined inside > < symbols Designate data values that are returned in the PAN xterm or mec console window dir Italics Responses from the programs this is a response Courier font Specific board signal names FBIAS1 BOLDFACE SMALL CAPITALS MECattribute names mcbcodeid Boldface italics The result of each test will be an EXCEL test report (EXCEL and.pdf file) generated by the tester and the MEC in a file called MNSN_EL_10_0300SNnnnn_vvv.txt (where SNnnnn is the serial number and vvv is the test sequence number for this board). This file should be copied to the relevant area of the MONSOON archive in directory: (/MNSN/MonsoonAdmin/Production/TST_Repository/TSTResults/ This file is a record of the test and an analysis of the test results that can be printed out and kept in the system binder supplied to the end user. The test procedure functions will request the entry of data as required. Page 4 of 13

5 1.1 Required Equipment DHE with programmable power supplies and 8- or 6-slot backplane chassis. Personal Computer running MS Windows 2000 or Windows XP. The PC must be connected to the network with the \\decapod\mnsn disk mapped into the Windows disk structure. Required programs are EXCEL, Word, and Xilinx Impact. JTAG-programming cable. Oscilloscope Agilent 54622D (Is there a suitable substitute for this scope and should it be listed?), DMM, and signal breakout box. 1.2 Test Schedule Stage 1. Stage 2. Stage 3. Step iii. Preparation of documentation Read the manufactured parts list and determine a serial number. Mark the board appropriately. (1) (Is there a footnote?) Create a new Assembly Record Tag (ART) for the board and create the Test Record file from the appropriate EXCEL template in the directory /MNSN/MonsoonAdmin/Production/TST_Repository/TestProcedures/ The file is located in the directory MONSOON_FunctionalBoardLevelTest_ClkBiasBrd_Ver1CCD.xlt for boards set up for CCD systems. Using a comparison photograph, (Should we supply a photo in this manual?) visually inspect the board for physical damage, missing and misplaced components. Board finishing to configure the board to meet specifications Install the jumper configuration required by the system (CCD) and enter the jumper configuration into the Test Record File. (Should we spell out the jumper config. Required or indicate where to find it?) Locate a test backplane, a suitable power supply, and a PAN computer. Inspect the backplane for bent pins and fit the appropriate test transition card (2) (Is there a footnote?) in slot 6. Set the power supply voltages and overcurrent limits to those listed in Table 3 in Appendix II. Mechanical fit, power consumption and firmware programming tests With the power to the chassis off, carefully insert the new IR Acquisition board for the first time in slot 6. While inserting the board, check for the alignment of the connectors and key. Connect a JTAG programming cable to the JTAG port and the programming pod. Remove any other boards from the system backplane. Page 5 of 13

6 Stage 3 (Cont.) Step iii. Step iv. Apply power to the board and compare the static power supply consumption with that noted in Table 3 in Appendix II. Enter the power supply readings in Table 3A of the EXCEL Test Record File from measurements taken at the test points noted in Figure N. (Are test points to be included?) Initialize the IMPACT JTAG tool. Now follow the procedures outlined in Appendix I to load the field programmable devices. Once programming of the FPDs is complete, compare the power supply consumption with that noted in Table 4 in Appendix II. Enter the power supply readings in Table 3B of the EXCEL Test Record File from measurements taken at the test points noted in Figure N. (Are test points to be included?) Additional Tests for the IR Acquisition Board Stage 4 Step iii. Step iv. NOTE: Preliminary Tests Shut down the power supply and insert a previously tested and known good Master Control Board (MCB) into the controller slot. Connect a fiber to the test Pixel Acquisition Node (PAN). Slot 1 is marked with a triangle on the PCI backplane. Reset the overcurrent protection levels to those indicated in Power up the system and compare the power consumption with that noted in. Verify the board FPGA code ID in the IR Acquisition and Master Control boards. Open two xterm windows on the PAN. In the first xterm window, type fs0 and look at the fiber link status. The status will probably show data in the receive FIFO buffer and should show the DHE to be in reset mode by having the dir(ection) bit true in the IO register (i=01xx0). The status command should return something similar to the following: Page 6 of 13

7 FibreXtreme (SL) Monitor (sl_mon) rev (2003/10/06) Driver: rev. b : for Linux with API rev. 2.1 Hardware: unit/bus/slot 0/1/4 - SL100 (D64) Firm. 1C.13 (1C.13) for 5.0V PCI Link Control Register (CSR 0x08) = 0x37 Link Status Register (CSR 0x0c) = 0x200 Link is UP FPDP Flags Register (CSR 0x10) = 0x200 NR.D.P2.P1.S: i=01110 o=00000 FIFO Threshold Register (CSR 0x14) = 0x0 Int.thr. = 0x0 Data count = 0xE75D (59229) bytes Link (and other) Errors = 3 Configurable parameters: Loop Configuration: 0 (Point-to-Point) Max Timeout: ( ms) Flow Control: 0 (NO) Halt on link error: 1 (YES) CRC generate/check: 1 (YES) Allow Queuing on link error: 1 (YES) Data Byte Swapping: 0 (NO) Receive SYNC with DVALID: 0 (NO) Step v. Step vi. Step vii. Use the command fc0 to clear the read buffer. Confirm with the status command that the read FIFO buffer is now empty (Data count = 0x0 (0) bytes). Install 1kΩ ganged loads to ground on the transition board video input connectors. The ganged loads present a 1kΩ load to each input and are connected together at the other end at a common ground point. An alligator clip with a wire to the local signal ground on the board is attached to the common side of the load. Connect a voltmeter probe to convenient ADC signal and ground input test points. These will probably be most accessible on the daughter card. In the second xterm window, change directory by using the command cd/mnsn/monsoonadmin/production/tst_repository/ TestProcedures/IRAcqBrdTstVer_1. Start up the PAN software and MONSOON Engineering Console using the command mecstart mnsnbrdtest panmachinename /data 65 The four PAN process windows and the MEC window should appear. Verify that the text fields Step 1. Enter Host Name and Step 2. Port Number contain the correct PAN machine name and port number (5142). Press the >STEP 3. CONNECT< button on the MEC. The Attribute Display pages will appear. Next press the >RESET< then the >ASYNCRESP< buttons on the MEC. Synchronization of the communication link will occur and the PIX and SEQ LEDs on the MCB will turn off. The MEC text area should look like Figure 1 in Appendix II after these steps are completed. Page 7 of 13

8 Stage5. Step ix. Step x. Step xi. In the first xterm window, use the fs0 status command to observe the link status again. The dir bit should now be clear i=0x00100and indicates correct communication between the PAN and MCB. To verify this, enter the following in the MEC command line: ppxgetavp mcbcodeid >RETURN< This should return the line r< OK: ppxgetavp: Success. \\ mcbcodeid= <0x000001c2> in the MEC text area. The MCB code is the firmware revision/version running in the MCB. In this case it should return the MCB function code of 0x000001C2 hex, 450 decimal. If the return line starts with r< OK[SIM]: ppxgetavp: it indicates that the PAN software has not connected to the DHE correctly. Follow the procedures in 0 to reconnect. Press the >SYSTEM DETUP< button and execute step 5. Of the setup procedure. Open the IR_ACQ_BOARD_MISC attribute screen by pressing the >IR_ACQ_BOARD_MISC< button Read the IR acquisition board iracqcodeid and iracqboardid attributes from the screen. The correct values should be 413 decimal (0x d hex) and 100 decimal (0x hex). If this is correct, the basic first level of the bus interface for the board under test is functioning. The system clock to the board under test should have been turned on during the loading of the monsoon.ini file during 0. Check it by going to the MCB screen and pressing >UPDATE<. The value of the mcbsysclken6 attribute should be set to 0x This enables the system clock to PCI slot 6.???The LED D2 on the IR Acquisition board should turn on??? This confirms correct system clock distribution on the IR Acquisition board. Offset Level Noise Test. Load StartOLNT from the prompt: L StartOLNT. Check the log file to see that all commands executed. StartOLNT must be in your local test directory. A copy of StartOLNT can be found in the Test Scripts folder of the NEWFIRM Test folder in MNSN on decapod. We do not have this file!!! Do we know what it is supposed to do??? Setup an oscilloscope and a DMM on ADC test point 0(1). Check the voltage. It should be between 0.000v and 2.500v. Calibrate the oscilloscope and set its input channel to AC coupling. Adjust the vertical deflection scale to a convenient range to observe the noise riding on the signal and observe the offset signal on the scope display. Page 8 of 13

9 Step iii. Step iv. Step v. Step vi. Step vii. Step viii. Step ix. Stage 5 Stage 6 In the MEC command line enter: setrawaddr 6 0x x7f >RETURN< This should return the line: Address 512 through 559 set to 0x7f On the IR_ACQ_BOARD_MISC screen set the iracqcfgdac attribute to 0 (0x00 ). This loads all IR Acq board DACs from bank 0. All video offset and spare DAC voltages should be set to their midrange (near 0.0v) value. Verify this by checking with the DMM. Repeat 0 varying the last (0x7F) parameter until the hex values 0x## (between 0x40 and 0xA0) required to set the ADC input to 0.3v, 1.3v and 2.3 v are found. The exact value of the parameter for each voltage may be determined by stepping the input offset value from 0x40 to 0xA0 in steps of 0x08 to determine the full range, then fine tuning on the first test of a particular board configuration. Record the resulting table of offset value vs. ADC voltage Using the previously determined hex value, set the offsets to.3 volts using the MEC command line command: setrawaddr 6 0x x## >RETURN< This should return the line: Address 512 through 559 set to 0x## Disconnect the DMM probes and take three frames of data. Use the MEC ENVIRONMENT screen to set the imagedir attribute to a directory on decapod called /data/ir_acq_sn###_tests. The board serial number is rpresented as ###. Use the MEC command area to enter the command: expsequence 3 OLNT_>RETURN< This should return the line: Gain test done 3 images taken Page 9 of 13

10 2.0 Appendix JTAG Usage and Field Programmable Device (FPD) Setup 2.1 Appendix I IR Acquisition Board FPD Programming Step iii. Step iv. Step v. Move the JTAG cable to the JTAG connector on the daughter board and initialize the chain with the Xilinx IMPACT program. Program and Verify the device (18V04, EEPROM) with the file: iracqfpgav35.mcs. To check the programming, run Verify only. This file and other loaders for the programmable devices can be found at decapod:/mnsn/monsoonadmin/newfirm_test\loaders. Reset the board using the front panel reset pushbutton. Install the JTAG programming cable on the Motherboard JTAG connector. Use IMPACT to initialize the JTAG chain. The IMPACT program should identify seven devices: TDI 18V02 (EEPROM) XCV300E (FPGA) XCR3384xl (CPLD) XCR3384xl (CPLD) TDO XCR3384xl (CPLD) XCR3384xl (CPLD) XCR3384xl (CPLD) XCR3384xl (CPLD) Step vi. Step vii. JTAG Device Chain Figure 1 Assign the iracqcpldv35.jed configuration file to the CPLD devices Program and verify the devices Verify that the file iracqfpgav35.bit has been downloaded to the FPGA during the reset of Step vi above. Page 10 of 13

11 Table 2 JTAG Order IR Acquisition Board - JTAG Device Description and Load Files 1 U95 2 U55 Designator Device Load file User Code 3 M.B. U51 4 M.B. U53 5 M.B. U54 6 D.B. U7 7 D.B. U18 8 D.B. zu26 18V02 EEPROM FPGA Configuration Store Virtex300E FPGA Buss Interface Coolrunner XCR3384 Sequencer CPLD Coolrunner XCR3384 Sequencer CPLD Coolrunner XCR3384 Sequencer CPLD Coolrunner XCR3384 Sequencer CPLD Coolrunner XCR3384 Sequencer CPLD Coolrunner XCR3384 Sequencer CPLD IrAcqFpgaV413.mcs IrAcqFpgaV413.bit IRAcqCpldV40.jed IRAcqCpldV40.jed IRAcqCpldV40.jed IRAcqCpldV40.jed IRAcqCpldV40.jed IRAcqCpldV40.jed f5 UsrCode fc2d fc2d fc2d fc2d fc2d fc2d 2.2 Appendix II. Power Consumption Tables These tables outline the power consumption for a correctly operating board alone in a MONSOON chassis under test conditions: Before Programming Power Consumption Tables Table 3 - Power Supply Requirements (before programming) Supply Name Set Voltage 3.3VD 3.3v +/- 50mv 5VD 5.0v +/- +5VA +5v +/- -5VA -5v +/- +15VA +15v +/- -15VA -15v +/- Nominal Current with Internal 3.3v Generation Nominal Current with External 3.3v Supply Overcurrent Setting 0.00 amps 0.05 amps 1.0 amps 0.61 amps 0.05 amps 1.0 amps 0.80 amps 0.85 amps 1.0 amps 0.30 amps 0.30 amps 0.5 amps 0.05 amps 0.05 amps 1.0 amps 0.16 amps 0.15 amps 1.0 amps Page 11 of 13

12 NOTES: Please review notes for currency and correctness. Some notes were removed because I didn t think they applied to this board. Could be wrong. (1). This should be done from the person who originally ordered the boards i.e. Dee! (3). Depending on the time constant set in the bias voltage amplifier, it may be necessary to wait several seconds for the voltage levels to settle before measuring the voltage of the signal After Programming Power Consumption Tables Table 4 - Power Supply Requirements (after programming) Supply Name Set Voltage 3.3VD 3.3v +/- 50mv 5VD 5.0v +/- +5VA +5v +/- -5VA -5v +/- +15VA +15v +/- -15VA -15v +/- Nominal Current with Internal 3.3v Generation Nominal Current with External 3.3v Supply Overcurrent Setting 0.00 amps 0.05 amps 1.0 amps 0.61 amps 0.05 amps 1.0 amps 0.80 amps 0.85 amps 1.0 amps 0.30 amps 0.30 amps 0.5 amps 0.05 amps 0.05 amps 1.0 amps 0.16 amps 0.15 amps 1.0 amps Table 5 - Overcurrent Protection Settings for MCB plus IR Acquisition Boards Supply Name Nominal Current with Internal 3.3v Generation Nominal Current with External 3.3v Supply Overcurrent Setting 3.3VD 0.90 amps 1.00 amps 2.5 amps 5VD 0.60 amps 0.50 amps 1.5 amps 3.3VA?????? +5VA 0.35 amps 0.35 amps 1.0 amps -5VA 0.01 amps 0.01 amps 0.5 amps +15VA 0.20 amps 0.20 amps 1.0 amps -15VA 0.30 amps 0.30 amps 1.0 amps Page 12 of 13

13 2.3 Appendix III MEC Screen Shots mec Screen after Connection, >reset> and >asyncresp> Figure Appendix IV Analyzing and Fixing DHE Connection Problems Page 13 of 13