MONSOON Master Control Board Test Procedures

Transcription

1 NATIONAL OPTICAL ASTRONOMY OBSERVATORY MAJOR INSTRUMENTATION GROUP 950 N. Cherry Ave. P. O. Box Tucson, Arizona (520) FAX: (520) MONSOON Master Control Board Test Procedures NOAO Document MNSN-TS Revision: 0 Authored by: Peter Moore, John Garcia, Paul Schmitt, Nick C. Buchholz and Mark Hunten 3/29/2006 Please send comments: pmoore@noao.edu Page 1 of 13

2 Revision History Version Date Approved Sections Affected Remarks 0 3/29/2006 All Original Version Page 2 of 13

3 Table of Contents Revision History...2 Table of Contents Introduction Required Equipment Test Schedule Additional Tests Appendix Appendix I Master Control Board FPD Programming Appendix II Master Control Board Power Consumption Before Programming Power Consumption After Programming Power Consumption Appendix III - MEC Screen Shots Appendix IV - Analyzing and Correcting DHE Connection Problems...13 List of Figures Figure 1 - MEC Screen after Connection, >reset> and >asyncresp>...12 List of Tables Table 1 - Test Description Conventions...5 Table 2 - JTAG Device Description and Load Files...9 Table 3 - Power Requirements (before programming)...10 Table 4 - Power Requirements (after programming)...11 Table 5 - Overcurrent Protection Settings for MCB plus CCD Acquisition Boards..11 Table 6 - Overcurrent Protection Settings for MCB plus Clock and Bias Boards...11 Table 7 - Overcurrent Protection Settings for MCB plus IR Acquisition Boards...12 Page 3 of 13

4 1.0 Introduction This document covers the testing strategy for the MONSOON Master Control Board to take the board from post-manufacture to a fully functional state. All tests described in this document pertain to the latest hardware revision level of the subject board. The tests described here do not prove that the board under test will meet specification but will test the full functionality of the board and identify failures that may result from component and manufacture problems. The test assumes the tester is familiar with the use of the mec (MONSOON Engineering Console) and can execute the required commands. The tests are divided into progressive stages ranging from 1 to N. Each higher number stage uses assumptions on the board condition that requires the successful completion of the previous stages. Stage 1. Stage 2. Stage 3. Stage 4. Preparation of documentation. Board finishing to configure the board to meet specifications. Mechanical fit, power consumption and firmware programming tests. Additional tests for the Master Control Board In the description for these tests, certain conventions are followed to ease comprehension. These conventions and examples of each are presented in Table 1. Table 1 - Test Description Conventions Convention Example Description Linux commands that are typed on a PAN xterm window mecstart Boldface characters Commands typed to the mec command line ppxsetavp Boldface italics Buttons on the DHE boards or mec console >startexp< Bold italics underlined inside > < symbols Designate data values that are returned in the PAN xterm or mec console window dir Italics Responses from the programs this is a response Courier font Specific board signal names FBIAS1 BOLDFACE SMALL CAPITALS Mec attribute names mcbcodeid Boldface italics The result of each test will be an EXCEL test report (EXCEL and.pdf file) generated by the tester and the mec in a file called MNSN_EL_10_0300SNnnnn_vvv.txt (where SNnnnn is the serial number and vvv is the test sequence number for this board). This file should be copied to the relevant area of the MONSOON archive in directory: (/MNSN/MonsoonAdmin/Production/TST_Repository/TSTResults/ This file is a record of the test and an analysis of the test results that can be printed out and kept in the system binder supplied to the end user. The test procedure functions will request the entry of data as required. Page 4 of 13

5 1.1 Required Equipment DHE with programmable power supplies and 8- or 6-slot backplane chassis. Personal Computer running MS Windows 2000 or Windows XP. The PC must be connected to the network with the \\decapod\mnsn disk mapped into the Windows disk structure. Required programs are EXCEL, Word, and Xilinx Impact. JTAG-programming cable. Oscilloscope - Agilent 54622D (Is there a suitable substitute for this scope and should it be listed?), DMM, and signal breakout box. 1.2 Test Schedule Stage 1. Stage 2. Stage 3. Step i. Step ii. Step iii. Step i. Step ii. Step i. Preparation of documentation Read the manufactured parts list and determine a serial number. Mark the board appropriately. (1) (Is there a footnote?) Create a new Assembly Record Tag (ART) for the board and create the Test Record file from the appropriate EXCEL template in the directory /MNSN/MonsoonAdmin/Production/TST_Repository/TestProcedures/ The file is located in the directory MONSOON_FunctionalBoardLevelTest_ClkBiasBrd_Ver1CCD.xlt for boards set up for CCD systems. Using a comparison photograph, (Should we supply a photo in this manual?) visually inspect the board for physical damage, missing and misplaced components. Board finishing to configure the board to meet specifications Install the jumper configuration required by the system (CCD) and enter the jumper configuration into the Test Record File. (Should we spell out the jumper config. required or indicate where to find it?) Locate a test backplane, a suitable power supply, and a PAN computer. Inspect the backplane for bent pins and fit the appropriate test transition card (2) (Is there a footnote?) in slot 6. Set the power supply voltages and overcurrent limits to those listed in Table 3 in Appendix II. Mechanical fit, power consumption and firmware programming tests With the power to the chassis off, carefully insert the new Master Control board for the first time in slot 1. While inserting the board, check for the alignment of the connectors and key. Connect a JTAG programming cable to the JTAG port and the programming pod. Remove any other boards from the system backplane. NOTE: Slot 1 is marked with a triangle on the PCI backplane. Page 5 of 13

6 Stage 3 (Cont.) Step ii. Step iii. Step iv. Apply power to the board and compare the static power supply consumption with that noted in Table 3 in Appendix II. Enter the power supply readings in Table 3A of the EXCEL Test Record File from measurements taken at the test points noted in Figure N. (Are test points to be included?) Initialize the IMPACT JTAG tool. Now follow the procedures outlined in Appendix I to load the field programmable devices. Once programming of the FPDs is complete, compare the power supply consumption with that noted in Table 4 in Appendix II. Enter the power supply readings in Table 3B of the EXCEL Test Record File from measurements taken at the test points noted in Figure N. (Are test points to be included?) Additional Tests for the Master Control Board Stage 4 Step i. Step ii. Step iii. System Tests Power up the system and compare the power consumption with that noted in Table 4. The front panel LEDs PIX and SEQ should be illuminated. Verify the board FPGA code ID in the MCB board. Press >RESET< on the front of the MCB board and note that the front panel LEDs turn off and turn back on when the >RESET< button is released. This tests local reset and FPGA boot functions. Open two xterm windows on the PAN. In the first xterm window, type fs0 and look at the fiber link status. The status will probably show data in the receive FIFO buffer and should show the DHE to be in reset mode by having the dir(ection) bit true in the IO register (i=01xx0). The status command should return something similar to the following: FibreXtreme (SL) Monitor (sl_mon) rev (2003/10/06) Driver: rev. b : for Linux with API rev. 2.1 Hardware: unit/bus/slot 0/1/4 - SL100 (D64) Firm. 1C.13 (1C.13) for 5.0V PCI Link Control Register (CSR 0x08) = 0x37 Link Status Register (CSR 0x0c) = 0x200 Link is UP FPDP Flags Register (CSR 0x10) = 0x200 NR.D.P2.P1.S: i=01110 o=00000 FIFO Threshold Register (CSR 0x14) = 0x0 Int.thr. = 0x0 Data count = 0xE75D (59229) bytes Link (and other) Errors = 3 Configurable parameters: Loop Configuration: 0 (Point-to-Point) Max Timeout: ( ms) Flow Control: 0 (NO) Halt on link error: 1 (YES) CRC generate/check: 1 (YES) Allow Queuing on link error: 1 (YES) Data Byte Swapping: 0 (NO) Receive SYNC with DVALID: 0 (NO) Page 6 of 13

7 Step iv. Step v. Step vi. Use the command fc0 to clear the read buffer. Confirm with the status command that the read FIFO buffer is now empty (Data count = 0x0 (0) bytes). In the second xterm window, start up the PAN software and MONSOON Engineering Console using the command mecstart mnsnbrdtest panmachinename /data 50 The four PAN process windows and the mec window should appear. Verify that the text fields Step 1. Enter Host Name and Step 2. Port Number contains the correct PAN machine name and port number (5142). Press the >STEP 3. CONNECT< button on the mec console. This should result in the appearance of the Attribute Display pages. Next press the >RESET< then the >ASYNCRESP< buttons on the mec console. This achieves synchronization of the communication link and turns off the PIX and SEQ LED s on the MCB. See Figure 1 for an example of the mec console text area after these steps are completed. In the first xterm window, use the fs0 status command to observe the link status again. The dir bit should now be clear i=0x00100and indicates correct communication between the PAN and MCB. To verify this in the mec command line, issue the command ppxgetavp mcbcodeid <RETURN> This should return the line r< OK: ppxgetavp: Success. \\ mcbcodeid= <0x000001b8> in the mec text area. The MCB code is the firmware revision/version running in the Sequencer FPGA on the MCB in this case should return revision code 0x000001b8 hex, 440 decimal. If the return line starts with r< OK[SIM]: ppxgetavp: it indicates that the PAN software has not connected to the DHE correctly. Follow the procedures in Appendix IV to reconnect. On the MCB_&_SEQUENCER screen review the MCBDBLPXLXFER attribute. Change the value from 0 to 1 or 1 to 0 and press the >UPDATE< button. The changes you made should be reflected in the read back. If they are not, the wrong version of the mcbpixfpga may be loaded. Page 7 of 13

8 Stage 5 Step i. Step ii. Step iii. Step iv. Step v. Step vi. Stage 6 Stage 7 Page 8 of 13

9 2.0 Appendix JTAG usage and Field Programmable Device (FPD) setup. 2.1 Appendix I Master Control Board FPD Programming Step i. Step ii. Step iii. Step iv. Connect the JTAG cable to the JTAG connector on the MCB board and initialize the chain with the Xilinx IMPACT program, Confirm that four devices are seen. The first is the Sequencer FPGA EEPROM store, the second is the Sequencer FPGA, the third is the Pixel FPGA EEPROM store, and the fourth is the Pixel FPGA Assign the correct codes to these devices as per??? from decapod@/mnsn/engr_development/loaders and annotate the EXCEL test report in the appropriate column of Table 4. Program the EEPROMs but do not program the FPGA. Cycle power to the chassis. Table 2 - JTAG Device Description and Load Files JTAG Order 1 U25 2 U22 3 U26 4 U20 With the IMPACT JTAG tool, verify that the proper code is present in both FPGAs, which should now have booted their own code from the EEPROMs. Designator Device Load file User Code 18V02 EEPROM FPGA configuration store Virtex300E FPGA Sequencer 18V02 EEPROM FPGA configuration store Virtex300E FPGA Pixel Buss McbSeqFpgaV42.mcs McbSeqFpgaV42.bit McbPixFpgaV421.mcs McbPixFpgaV421.bit Chksum 0014cc05d UsrCode Chksum UsrCode Page 9 of 13

10 2.2 Appendix II. Power Consumption Tables These tables outline the power consumption for a correctly operating board alone in a MONSOON chassis under test conditions: Before Programming Power Consumption Tables Table 3 - Power Requirements (before programming) NOTES: Name Set Voltage 3.3VD 3.3v +/- 50mv 5VD 5.0v +/- +5VA +5v +/- -5VA -5v +/- +15VA +15v +/- -15VA -15v +/- with Internal 3.3v Generation with External 3.3v Overcurrent Setting 0.00 amps 0.06 amps 1.0 amps 0.25 amps 0.15 amps 1.0 amps 0.35 amps 0.35 amps 1.0 amps 0.01 amps 0.01 amps 0.5 amps 0.20 amps 0.20 amps 1.0 amps 0.30 amps 0.30 amps 1.0 amps Please review notes for currency and correctness. Some notes were removed because I didn t think they applied to this board. Could be wrong. (1). This should be done from the person who originally ordered the boards i.e. Dee! (3). Depending on the time constant set in the bias voltage amplifier, it may be necessary to wait several seconds for the voltage levels to settle before measuring the voltage of the signal. Page 10 of 13

11 2.2.2 After Programming Power Consumption Tables Table 4 - Power Requirements (after programming) Name Set Voltage 3.3VD 3.3v +/- 50mv 5VD 5.0v +/- +5VA +5v +/- -5VA -5v +/- +15VA +15v +/- -15VA -15v +/- with Internal 3.3v Generation with External 3.3v Overcurrent Setting 0.00 amps 0.06 amps 1.0 amps 0.25 amps 0.15 amps 1.0 amps 0.35 amps 0.35 amps 1.0 amps 0.01 amps 0.01 amps 0.5 amps 0.20 amps 0.20 amps 1.0 amps 0.30 amps 0.30 amps 1.0 amps Table 5 - Overcurrent Protection Settings for MCB plus CCD Acquisition Boards Name with Internal 3.3v Generation with External 3.3v Overcurrent Setting 3.3VD 0.90 amps 1.00 amps 2.5 amps 5VD 0.60 amps 0.50 amps 1.5 amps +5VA 0.35 amps 0.35 amps 1.0 amps -5VA 0.01 amps 0.01 amps 0.5 amps +15VA 0.20 amps 0.20 amps 1.0 amps -15VA 0.30 amps 0.30 amps 1.0 amps Table 6 - Overcurrent Protection Settings for MCB plus Clock and Bias Boards Name with Internal 3.3v Generation with External 3.3v Overcurrent Setting 3.3VD 0.90 amps 1.00 amps 2.5 amps 5VD 0.60 amps 0.50 amps 1.5 amps 3.3VA?????? +5VA 0.35 amps 0.35 amps 1.0 amps -5VA 0.01 amps 0.01 amps 0.5 amps +15VA 0.20 amps 0.20 amps 1.0 amps -15VA 0.30 amps 0.30 amps 1.0 amps Page 11 of 13

12 Table 7 - Overcurrent Protection Settings for MCB plus IR Acquisition Boards Name with Internal 3.3v Generation with External 3.3v Overcurrent Setting 3.3VD 0.90 amps 1.00 amps 2.5 amps 5VD 0.60 amps 0.50 amps 1.5 amps +5VA 0.35 amps 0.35 amps 1.0 amps -5VA 0.01 amps 0.01 amps 0.5 amps +15VA 0.20 amps 0.20 amps 1.0 amps -15VA 0.30 amps 0.30 amps 1.0 amps 2.3 Appendix III MEC Screen Shots mec Screen after Connection, >reset> and >asyncresp> Figure 1 Page 12 of 13

13 2.4 Appendix IV Analyzing and Fixing DHE Connection Problems Page 13 of 13