CUORE/ELECTRONICS. UCLA (testing) USC (production) INFN-MIB (design, prototyping and validation)

Transcription

1 CUORE/ELECTRONICS UCLA (testing) Huan Z. Huang, Xiaohua Liu, Stephen Trentalange, Charles Whitten, Xiaoyu (Brian) Zhu. USC (production) Frank T. Avignone, Ray Edmonds, Carl Rosenfeld, Kevin Wilson. INFN-MIB (design, prototyping and validation) Andrea Giachero, Claudio Gotti, Matteo Maino, Gianluigi Pessina, Lorenzo Cassina

2 CUORE project The hw of CUORE has been split into few main items:. Refrigerator;. Detector;. Electronics; 4. DAQ We are considering here the Electronics, which include: All that concern the managing of detectors bias/signal from the bolometer up to the DAQ. GS, CRC5 May, 0

3 Main requirements to the Electronics Experiment characteristics:. Detector signal bandwidth very small, few tens of Hz maximum;. Very Long runs. Design rules: NOISE: whatever source of noise must be extremely small at low frequency. The system must be stable at few ppm/c for most of the stuff. GS, CRC5 May, 0

4 A selection of few of the many implemented features Customization of the detector load resistors; Customization of the preamplifier input JFET; Temperature compensation of the preamplifier drift at second order; Power supply with ppm/c stability and low /f noise; Pulser calibration with ppm/c stability to allow for a seldom use of a reference particle source; Microcontrollers on all the boards for control and monitoring; GS, CRC5 May, 0 4

5 Electronic System Scheme Detector Links to the detectors: PEN and glue Kapton boards. Very front-end (on the fridge) Antialiasing Pre PGA x K Bias and load resistors X Glue Logic DAQ Glue. Logic Main board Bessel Filter Small Faraday Cages = PEN =Constantan Close to the DAQ K =Kapton Heater Linear DC/DC 48 V Pulser Supply, 9 V, 48 V to / V AC/DC 5 V Calibration Pulse Gen. Power supply system Glue Logic from DAQ to ALL blocks GS, CRC5 May, 0 5

6 CUORE vs CUORICINO Detector bias stability CUORE <00 ppm/c (< 5 ppm/c measured and to be verified in production) CUORICINO < 000 ppm/c Detector bias range +/- 0 V, 8 bit +/- 5 V or +/-.5 V, fixed in hd Very front-end occupation CUORICINO/. Preamplifier series noise same Preamplifier Input current 40 fa SE, 5 fa DIff 0. pa SE, 0 fa Diff Gain 0 V/V or V/V settable, Few ppm/c 0 V/V, Few ppm/c Preamplifier drift < 00 nv/c < 00 nv/c PGA gain On board DC detector characterization V/V, 0 bits, Few ppm/c V/V, 5 bits, Few ppm/c 4 bit ADC Sigma delta Not available Communication protocol CAN bus on fiber optic IC on fiber optic Bessel volume occupation CUORICINO/4 Linear power supply ppm/c, NOISE_CUORICINO/ DC/DC 48 V input Not available AC/DC Commercial Commercial Pulser ppm/c, Differential output ppm/c, single ended output GS, CRC5 May, 0

7 Electronic System Scheme: design completed Detector Links to the detectors: PEN and glue Kapton boards. Very front-end (on the fridge) = design completed Antialiasing Pre SS x K Bias and load resistors X Glue Logic DAQ Glue. Logic Main board Bessel Filter Small Faraday Cages = PEN =Constantan Close to the DAQ K =Kapton Heater Linear DC/DC 48 V Pulser Supply, 9 V, 48 V to / V AC/DC 5 V Calibration Pulse Gen. Power supply system Glue Logic from DAQ to ALL blocks GS, CRC5 May, 0

8 Electronic System Scheme at a glance Each DAC handles two channels D DAC_SYNC DAC_SCLK DAC_MOSI +V DAC_MISO LDAC CLR D +V C0 00nF D +8V -8V C 00nF +V +8V U OPA8-8V -8V OPA8 +8V U0 +8V + C 4uF C0 00nF U C9 00nF VDD SDIN SDO C 00nF C 00nF AD545YRUZ C4 00nF CORR_CH +VREF +VREF CORR_CH -8V + C8 4uF RFBA IOUTA 0 IOUTB LDAC* 5 IOUTB CLR* 9 SYNC* SCLK 8 RA RB 9 R_A R_B 5 0 RA RB 8 VREFA VREFB 4 RA IOUTA RB RFBB J8 JUMPER 4 J JUMPER +VREF C5 5 pf C5 5 pf C 00nF +VREF + C 4uF +8V -8V -8V +8V C 00nF U8 C 00nF C8 00nF OPA8 U9 C9 00nF OPA8 J CON J4 CON CH_OUTN CH Test Point CH_OUTP CH_OUTN CH Test Point CH_OUTP 4CH_PULSER schematic path = /Gen0/DAC Page Name = DAC schematic name = DAC INFN e Uni Fis MIB Sheet P.za della Scienza 0 MI - I Thursday, August 9, 00 of 9 P.0 P. 4 5 ENET_MDIO P.4 P. R 0R_MCB0 only 0 P. ENET_MDC R0 0R_MCB0 only 4 C 00n P.4 R k C4 R8 0k 00n RST P.8 P.9 P.0 C5 00n U PWR_DOWN/INT RESET_N TX_CLK TXD_0 TXD_ TXD_ TXD_/SNI_MODE TX_EN MDIO MDC COL/PHYAD0 CRS/CRS_DV/LED_CFG RX_ER/MDIX_EN RX_DV/MII_MODE RXD_0/PHYAD RXD_/PHYAD RXD_/PHYAD RXD_/PHYAD4 RX_CLK AVDD IOVDD IOVDD DP8848CVV P.5 8 TX- RX- Title 50MHz VDD 4 80R CHS_ N.C. C8 ETH J R9 49R9 % 00n <Title> C 00n C9 00n C 00n TD+ TD- 4 RD+ RD- OSC 4 X SJ OUT X 5 INH 5MHZ_OUT LED_ACT/COL/AN_EN R k LED_ACT 4R8 LED_SPEED/AN 8 LED_LINK LED_LINK/AN0 RBIAS 4 00MHz R 4k8 % C0 0u PFBOUT 8 C 00n R PFBIN 49R9 % PFBIN RESERVED C 00n RESERVED 0 R4 k RESERVED R5 k RESERVED 0 RESERVED 8 RESERVED 9 RESERVED IO 5 IO D C5 R5 49R9 % 4 CT 00n GRN_LED_C 0 YEL_LED_C YEL_LED_A GRN_LED_A TX+ R4 49R9 % 9 Size Document Number Rev A <Doc> <Rev Code> LED_ACT LED_LINK R59 R0 R R k k 0k 0k Detector Links to the detectors: PEN and glue Kapton boards. Very front-end (on the fridge) = prototype done Antialiasing Pre SS x K Bias and load resistors X Glue Logic DAQ Glue. Logic Main board Bessel Filter Bessel = PEN =Constantan K =Kapton Small Faraday Cages Close to the DAQ Heater Linear DC/DC 48 V Pulser Supply, 9 V, 48 V to / V AC/DC 5 V Calibration Pulse Gen. Power supply system Glue Logic from DAQ to ALL blocks GS, CRC5 May, 0 8 CR 5 RX

9 Electronic System Scheme: production completed Detector Links to the detectors: = production completed PEN and glue Kapton boards. = production almost completed Antialiasing Very front-end (on the fridge) Pre SS x K Bias and load resistors X Glue Logic DAQ Glue. Logic Main board Bessel Filter Small Faraday Cages = PEN =Constantan Close to the DAQ K =Kapton Heater Linear DC/DC 48 V Pulser Supply, 9 V, 48 V to / V AC/DC 5 V Calibration Pulse Gen. Power supply system Glue Logic from DAQ to ALL blocks GS, CRC5 May, 0 9

10 List and status (). PEN very low background link at 0 mk (for CAW): final production is ending;. Detector Link from the fridge to the preamplifier inputs: cables and connectors selected and procured at USC, used and under test with CUORE0;. Front-end, production ended; 4. Main board for preamplifier: prototyped and debugged, preproduction/production starting; 5. Preamplifiers: production ended;. Detector biasing: design done;. Load resistors: production ended; 8. Cabling from front-end to Bessel filters, pending; 9. for Bessel filter: done; 0. Bessel filter: production ended, in population;. Faraday cage for Bessel filter, at Gran Sasso; GS, CRC5 May, 0 0

11 List and status (). Cabling from Bessel filter to DAQ, pending; 4. Pre regulation of the power supply (DC/DC): in final production phase; 5. Linear Power Supply, design ending;. Calibrating Pulse generator: layout under development;. Firmware for glue logic: done; 8. Glue Logic: design ended. 9. Crates for Electronics Housing. GS, CRC5 May, 0

12 Conclusions List of the items in finalization: Linear power supply ( 0 pieces): design complete, schematic and layout underway; Pulser for stabilization (~0 pieces): layout underway; Glue logic board ( 5 pieces): layout pending. GS, CRC5 May, 0