Silvertel. EVALAG5300 Rev 3 Evaluation Board User Manual

Transcription

1 Silvertel EVALAG500 Rev Evaluation Board User Manual Rev. June 0

2 EVALAg500 Rev - Evaluation Board User Manual Table of Contents Table of Contents Table of Figures Introduction Board Description. Input Selection and Classification.... Output adjustment... 5 Typical Set-up Using the Board 5. Typical Application EVALAG500 REV R - Evaluation Board Schematic.... Link settings... Table of Figures Figure : Board Layout... Figure : Basic set-up... Figure : Example set-up... 5 Figure : Board Schematic...

3 EVALAg500 Rev - Evaluation Board User Manual Introduction This manual is intended to be a guide to using the EVALAG500 Rev.0 evaluation board with a Silvertel Ag500 Powered Device (PD) module. Board Description The input data and power is supplied to the board through connector J0. The data is passed through to the peripheral equipment via J00, with the power from the PD module supplied via J to J5 (see Figure & ). The EVALAG500 on-board bridge rectifiers will ensure that the correct input polarity is applied to the PD.. Input Selection and Classification The EVALAG500 board will automatically direct the power from J0 to the Ag500 s input. LED will be illuminated when PoE power is being applied to the board. LK can be removed if you do not want LED to illuminate. If the need for a V-Capacitor filtering arrangement is needed for further noise reductions, C and C can be fitted with LK present. C and C values can be nf to nf and will need to be capable of handling the 500Vdc impulse test because these capacitors cross the isolation barrier. The Ag500 Classification is fixed at Class and does not need any external programming components. When the EVALAG500 board is connected to an IEEE80.at (PoE+) compliant PSE such as a Phihong POEU-AT-R; the PSE will detect Class and output -Event classification pulses. In turn the Ag500 detects these pulses and activates the AT-DET detect output. This output is connected to an opto-isolator to cross the isolation barrier and LED will be illuminated. Note: The EVALAG500 does not have an on-board PHY or µ-controller; so does not perform the Data Link Layer (DLL) classification communications back to the PSE (to confirm its power requirement). Many IEEE80.at PSEs (such as the Phihong POEU-AT-R) do not need this and will automatically supply full Type power at start-up. But there are several Switches (e.g. Cisco) that will only output Type power level (<5.W), until they receive DLL confirmation that the PD is Type and supports the higher power level.

4 EVALAg500 Rev - Evaluation Board User Manual Figure : Board Layout. Output adjustment The Ag500 output has an ADJ pin, which allows the output voltage to be increased or decreased from its nominal value. The EVALAG500 board has an adjust link LK and two resistors R (8K) and R (0R) which allows the Ag500 output to be adjusted to its maximum and minimum values. To increase the output voltage (to its maximum) connect a link to LK in the top position so the link is between the middle and top pin. To reduce the output voltage (to its minimum) connect a link between the bottom pin and middle pin of LK. If the output voltage needs to be set to a different value (within the adjustment range) then connect different resistors instead of the (0R) or (8K) link.

5 EVALAg500 Rev - Evaluation Board User Manual 5 Typical Set-up Figure shows the basic set up using the EVALAG500 evaluation board with a Midspan or Endspan. The equipment required: - Midspan or Endspan PSE (Power Sourcing Equipment) Peripheral (or Test) Equipment CAT5e cables Output power cable Mains cable Figure : Basic set-up

6 EVALAg500 Rev - Evaluation Board User Manual 5 Using the Board. Typical Application Figure shows an example set-up using an Ag500 powered by a Phihong POEU- AT-R Midspan and supplying +V to a Vivotek PZ (or PZ) ethernet camera. The PC ethernet port is connected to the data input of the Phihong POEU-AT-R (PSE) via a short Cat5e patch cable. The Data & Power output from the Phihong POEU-AT-R is connected to the input of the EVALAG500 evaluation board (J0) via a CAT5e crossover cable (up to 00m). The data output of the EVALAG500 evaluation board is connected to the data port of the ethernet camera via a short CAT5e patch cable. The +V (parallel configuration) power output from the EVALAG500 evaluation board (J) connects to the dc input of the Vivotek PZ ethernet camera. Figure : Example set-up

7 EVALAg500 Rev - Evaluation Board User Manual. EVALAG500 REV R - Evaluation Board Schematic J S-88-SMT T00 DA+ XA+ TDA TXA 5 DA- DB+ XB+ 0 XA- TDB TXB 8 DB- XB- DC+ XC+ TDC TXC 8 DC- XC- 0 DD+ XD+ TDD TXD 5 DD- XD J0 00S-88-SMT R00 R0 R0 R0 R0 R05 R0 R0 C00 0nF 50V C0 0nF 50V C0 0nF 50V C0 0nF 50V C0 0nF 50V C05 0nF 50V C0 0nF 50V C0 0nF 50V C08 000pF KV C0 000pF KV BRIDGE BRIDGE BR BR LK LED U LED D +VCC SMAJ58 R R 5R LMM/SO D BZX8C0V R 0R L L L MPZ0S0A MPZ0S0A MPZ0S0A L L5 L MPZ0S0A MPZ0S0A MPZ0S0A R 0R U VIN+ VIN- AT-Det NC 5 NC NC +VDC 8 ADJ -VDC 0 -VDC LK 8K R R 0R LK CON R K LED C + LED 0uF R5 K Power Output J RED J CON J5 BLACK C.nF.5KV LED LED C.nF.5KV LK JUMPER ISO KCP5NT Title EVALAg500 Size Document Number Rev A EVALAg500 Date: Thursday, August, 05 Sheet of Figure : Board Schematic. Link settings LK Connects input power LED circuit LK Output adjust select LK IEEE80.at PSE detection LED LK Option for V-Cap link to be fitted