CLARO QA at Milano-Bicocca

Transcription

1 CLARO QA at Milano-Bicocca Angelo Cotta Ramusino, Massimiliano Fiorini, Roberto Malaguti INFN and University of Ferrara, Italy Paolo Carniti, Lorenzo Cassina, Claudio Gotti, Matteo Maino, Clara Matteuzzi, Gianluigi Pessina INFN and University of Milano Bicocca, Italy Mateusz Baszczyk, Piotr Dorosz, Wojciech Kucewicz INP and AGH-University of Science and Technology, Krakow, Poland Some considerations of these slides have been not previously discussed with people in gray, but people in gray cannot be forgotten as they are part of the business, anyway.

2 A short summary of the system strategy For large volume systems the good practice is to design-for-testability. This is the strategy we tried and try to apply in all our projects. One example for this is the HV distribution board system of the present RICH: the boards were designed to work with 2 configurations, one of which designed only for testing purpose (HV boards had 100 %). IEEE TNS, Vol. 56, pp , 2009; NIMA, vol. A598, pp , 2009; IEEE TNS, Vol. 53, pp , Edinburgh, April 13, 2015 g.pessina 2

3 CL A PM T This was the aim since the first prototypes. RO The CLARO layout has maintained the same approach: it is completely modular, allowing for several ways of testing approaches (maybe too many ). FP GA of the layout NIMA, vol. 652, pp , Edinburgh, April 13, 2015 g.pessina 3

4 The modularity of the layout vs the testability (1) Modularity allows easily to test each part individually. Edinburgh, April 13, 2015 g.pessina 4

5 The modularity of the layout vs the testability (2) A further property: the chip area is small. As a consequence the yield is expected to be quite large. FEB s Edinburgh, April 13, 2015 g.pessina 5

6 The modularity of the layout vs the testability (3) At the end every part of the so called elementary cell is separable from the rest. This gives the maximum flexibility for the test procedure to be adopted. Edinburgh, April 13, 2015 g.pessina 6

7 QA procedure QA procedure can be done following several steps 1. Go-non-go test: in this case only a few significant parameters are verified; 2. Boundary scan procedure: at the design level a series path is implemented that allows to cascade the parts and verify the integrity of the system with few serial signals. This is typical of a digital domain and does not apply to our case; 3. Full-test: all the parameters are tested sequentially. This is our case. We will concentrate on steps 1 and 3. Both steps 1 and 3 can be implemented with the same setup or different setups. Edinburgh, April 13, 2015 g.pessina 7

8 QA option 1 Concerning the CLAROs several options can be considered, listed below. 1. CLAROs are assembled on their FEBs; 2. The FEBs are connected to the Steve s board (previously tested); 3. The FEBs are subjected to a go-non-go test from the FPGA; 4. The FEBs (not working FEBs are substituted) are characterized from the FPGA. 5. Defected FEBs Boards are re-worked. PMT CLARO FEB FPGA Steve s board No PMTs are used at this stage. Partial final cell Edinburgh, April 13, 2015 g.pessina 8

9 QA option 2 1. CLAROs are assembled on their FEBs; 2. The FEBs are connected to FE-FPGA (INFN-FE) board or to a MIB-ARM- Cortex -controller board (INFN-MIB); 3. The FEBs are subjected to a go-non-go test from the MIB- -controller/fe- FPGA; 4. The FEBs (not working FEBs are substituted) are then characterized with the same MIB- -controller/f-fpga card; 5. Defected FEBs Boards are re-worked. CLARO FEB PMT MIB controller or FE FPGA FPGA No PMTs are used at this stage. The system can be designed to test one or more boards at the same time. Steve s board No Steve s board are used at this stage. Edinburgh, April 13, 2015 g.pessina 9

10 QA option 3 1. CLAROs are tested individually with a go-non-go test on a burn-in card; 2. CLAROs are mounted on the FEBs; 3. The FEBs are subjected to a go-non-go test from the MIB- -controller/fe- FPGA (this step can be eventually omitted); 4. The FEBs (not working FEBs are substituted) are then characterized from the MIB- -controller/fe-fpga; 5. Defected FEBs are re-worked. Step 1 Step 2 CLARO FEB MIB controller or FE FPGA Edinburgh, April 13, 2015 g.pessina 10

11 QA status (1) We investigated how to proceed. Opt 1 is part of the cell characterization and must be done in lab. Opts 2 and 3 are time consuming and can be done by an operator. We asked to a good company to do that obtaining a quotation. At the moment we considered only the (very good) company to which we (FE-MIB) refer for our assemblies. The cost of a specialized operator is slightly less than 50 /hour, duties included. CLARO reworking (included re-testing) is 9 /board. Examples: testing single CLARO at 30 sec/chip is about 0,35 /chip. A more conservative 1 min/chip is about 0,7 /chip, or per (5000 PMT readout). Go-non-go on a FEB is about 4 /FEB at 5 min/feb test. Edinburgh, April 13, 2015 g.pessina 11

12 QA status (2) We are now equipped with a working re-working station for last minute problems. Edinburgh, April 13, 2015 g.pessina 12

13 Final considerations Adoption of either of the 3 options is dependent on the CLARO yield. We(-MIB) are in favor of opt 1 or its hybrid opt 2. The next production will be about 250 CLAROs. Based on the yield of this small production we will be in the condition to decide to follow opts 1 or 2 or opt 3. Even in case the yield would be excellent, for the final production, in a conservative way, a few hundred of FEBs could be assembled and tested before to decide for the final opt. Edinburgh, April 13, 2015 g.pessina 13

14 Spare Edinburgh, April 13, 2015 g.pessina 14

15 Documentation: Most of the documentation is, or linked starting from, the new CLARO home page: CLARO was designed following the LHCb upgrade requirements and the characteristics we measured on the MaPMT. CLARO characteristics and RICH specifications are almost the same. Edinburgh, April 13, 2015 g.pessina 15