Saeid Nooshabadi. Overview. Page Table... COMP Translation Lookaside Buffer (TLB) Microprocessors and Embedded Systems

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1 Overview COMP 3221 Microprocessors and Embedded Systems Page Table Translation Lookaside Buffer (TLB) Lectures 37: Virtual - II October, 2003 saeid@unsw.edu.au Some of the slides are adopted from David Patterson (UCB) COMP3221 lec37-vm-ii.1 COMP3221 lec37-vm-ii.2 Cache Virtual { COMP3221 lec37-vm-ii.3 Review: Hierarchy Regs Upper Level Instr. Operands Faster Cache Blocks L2 Cache Blocks Pages Disk Files Tape Larger Lower Level Review: Address Mapping: Page Table Virtual Address: page no. offset (actually, concatenation) Reg #2 in CP #15 in ARM Page Table Page Table... Base Reg V A.R. P. P. A. index Val Access Physical + into -id Rights Page page Number Physical table. Address... Page Table located in physical memory COMP3221 lec37-vm-ii.4

2 Paging/Virtual for Multiple Pocesses User A: Virtual Physical Stack 64 MB 0 Heap Static Code COMP3221 lec37-vm-ii.5 A Page Table 0 B Page Table User B: Virtual 0 Stack Heap Static Code COMP3221 lec37-vm-ii.6 Analogy Book title like virtual address (ARM System On- Chip) Library of Congress call number like (QA76.5.F ) physical address Card (or online-page) catalogue like page table, indicating mapping from book title to call number On card (or online-page) info for book, indicating in local library vs. in another branch like valid bit indicating in main memory vs. on disk On card (or online-page), available for 2-hour in library use (vs. 2-week checkout) like access rights Address Map, Mathematically Speaking V = {0, 1,..., n - 1} virtual page address space (n > m) M = {0, 1,..., m - 1} physical page address space MAP: V --> M U {θ} page address mapping function MAP(a) = a' if data at virtual address a is present in physical address a' and a' = θ if data at virtual address a is not present in M a page fault Name Space V OS fault Processor handler a COMP3221 lec37-vm-ii.7 0 Addr Trans Mechanism a' physical address Main OS performs Disk Comparing the 2 Levels of Hierarchy Cache Version Virtual vers. Block or Line Page Miss Page Fault Block Size: 32-64B Page Size: 4K-8KB Placement: Fully Associative Direct Mapped, N-way Set Associative Replacement: Least Recently Used LRU or Random (LRU) Write Thru or Back Write Back this transfer COMP3221 lec37-vm-ii.8

3 Notes on Page Table Solves Fragmentation problem: all chunks same size, so all holes can be used OS must reserve Swap Space on disk for each process To grow a process, ask Operating System If unused pages, OS uses them first If not, OS swaps some old pages to disk (Least Recently Used to pick pages to swap) Each process has its own Page Table Will add details, but Page Table is essence Virtual Problem #1 Not enough physical memory! Only, say, 64 MB of physical memory N processes, each 4GB of virtual memory! Could have 1K virtual pages/physical page! Spatial Locality to the rescue Each page is 4 KB, lots of nearby references No matter how big program is, at any time only accessing a few pages Working Set : recently used pages of Virtual COMP3221 lec37-vm-ii.9 COMP3221 lec37-vm-ii.10 Virtual Address and a Cache (#1/2) Virtual Address and a Cache (#2/2) Processor VA Cache hit data miss PA Main Processor Translation VA PA miss Translation hit Main Cache data Cache operates on Virtual addresses. ARM Strategy The advantage: If in cache the translation is not required. Disadvantage: Several copies of the the same physical memory location may be present in several cache blocks. (Synonyms problem). Gives rise to some complications! COMP3221 lec37-vm-ii.11 Cache typically operates on physical addresses on most other systems. Address Translation (Page Table access) is another memory access for each program memory access! Accessing memory for Page Table to get Physical address (Slow Operation) Need to fix this! COMP3221 lec37-vm-ii.12

4 Reading Material Steve Furber: ARM System On-Chip; 2nd Ed, Addison-Wesley, 2000, ISBN: Chapter 10. Virtual Problem #2 Map every address 1 extra memory accesses for every memory access Observation: since locality in pages of data, must be locality in virtual addresses of those pages Why not use a cache of virtual to physical address translations to make translation fast? (small is fast) For historical reasons, this cache is called a Translation Lookaside Buffer, or TLB COMP3221 lec37-vm-ii.13 COMP3221 lec37-vm-ii.14 Typical TLB Format Virtual Physical Dirty Ref Valid Access Address Address Rights PROJECTS IN DIGITAL HARDWARE DESIGN FOR 4 th Year TLB just a cache on the page table mappings TLB access time comparable to cache (much less than main memory access time) Ref: Used to help calculate LRU on replacement Dirty: since use write back, need to know whether or not to write page to disk when replaced COMP3221 lec37-vm-ii.15 COMP3221 lec37-vm-ii.16

5 Secondary Serial Port Primary Serial Port Pow er On/Off VA VB VC for Virtex-E (U9, U10, U18, U19) SB SB Power 1 Power 2 Digital Systems Laboratory Hardware LEDs Spartan- XL (U4) Flash ROM (U25) Xilinx Virtex-E (U16) Pow er VS VS LCD Module Pow er Gro und Link Spartan VS Terminals Spartan SA Terminals Spartan SB Terminals System SRAM Modules (U11-U14, U21-U24) SA SA S JTAG Atmel CPU (U17) Ethernet (U7) Power Ethernet S1 S2 S3 RESET LEDs LEDs Connector Switches Connector S6 S4 Boot S7 S8 S9 S10 Expansion Connector 1 Expansion Connector 2 DSL Board is A Board for 21 st Century The State-of-the-Art Development Board DSL Board Contains: Designed by the University of Manchester with lots of collaboration from UNSW An ARM Microcontroller With 2 MB of Flash and up to 4 MB of SRAM 2 Xilinx FPGAs for extended interfacing and specialised coprocessors Optional Ethernet chip LCD Module Lots of uncommitted Switches and LEDs DSLMU Hardware Block Diagram Microcontroller Bus Perip heral Bus (Port s A a nd B) Two Printed circuit Boards COMP3221 lec37-vm-ii.17 Terminal connector Two PCBs to FPGAs COMP3221 lec37-vm-ii.18 Serial Ports Atme l CPU (U17) MU Board Flash ROM (U25) Optional (U9, U10, U18, U19) VA VB System SRAM Modules (U11-U14, U21-U24) Xilinx Virtex-E (U16) VC VS Optional Ethernet (U7) Xilinx Spartan-XL (U4) SA SB Expansion Connector 1 Expansion Connector 2 Power Supply LEDs (D8-D15) Boot Select Switch (U1) LCD Module Uncommitted Switches Uncommitted LEDs Expansion Board Projects with Digital Systems Lab Board Project 1: Design of a Vector Floating Point Co-Processor for ARM Core: Aim: The Aim of this project is to built Floating Point Vector Processor On the Vertex FPGA. Degree of Difficulty: Hard, and Ability: Number Representation, Digital System Design, DSP Project 2: Design of a Fixed Point DSP for ARM Core: Aim: The Aim of this project is to built DSP Optimised Processor (Single Cycle MAC Processor/ Distributed Arithmetic) On the Vertex FPGA. Degree of Difficulty: Hard, and Ability: Number Representation, Digital System Design, DSP COMP3221 lec37-vm-ii.19 COMP3221 lec37-vm-ii.20

6 Project 3: Development of a Simple Multi tasking Operating System Aim: The Aim of this project is Development of a Simple Multi tasking Operating System with Simple Virtual Protection for on-board program monitoring and debugging. Degree of Difficulty: Moderate, and some Challenges Ability: Software Development, Basic Operating Systems Application: Our Undergraduate/Post Graduate Teaching Advantage: Make yourself Immortal! COMP3221 lec37-vm-ii.21 Project 4: Interfacing GNU debugging tool with on-board emulator (Komodo) Aim: The Aim of this project is to Interface GNU debugging tool with on-board emulator program to facilitate source-level debugging and monitoring. Degree of Difficulty: Moderate to Hard with some Challenges Ability: Software Development, Basic Operating Systems Application: Our Undergraduate/Post Graduate Teaching Advantage: Make yourself Immortal! COMP3221 lec37-vm-ii.22 Project 5: Porting of ucliux to DSL Board Aim: The Aim of this project is to port real-time Operating System uclinx to DSL Board. Degree of Difficulty: Hard, and Ability: Software Development, Basic Operating Systems Project 6: Design of an embedded Internet enabled device for remote control and monitoring Aim: The aim of this project is to design an embedded interface device using programmbale microcontrollers and FPGAs, to wireless devices in one hand and modem/lan on the other hand. The unit collects the data through the wireless picodevices and in turn transfers the data via modem or lan to a remote server via TCP/IP stacks. It should also be possible to control the picodevices remotely. The challenge is to build the various software layers, on a realtime operating system like ecos to do the task. Degree of Difficulty: Hard, and Ability: Software Development, Basic Operating Systems, basic Hardware Interfacing COMP3221 Start: lec37-vm-ii.23 COMP3221 lec37-vm-ii.24

7 COMP3221 lec37-vm-ii.25 Project 7: Design of an embedded Internet enabled device for remote control and monitoring Aim: The aim of this project is to design an embedded interface device using programmable microcontrollers and FPGAs, to control and monitor the viewing of cable TV channels.this embedded unit controls a TV tuner, in a real time fashion, based on the control information it receives remotely. The unit is connected to the internet via a cable modem. It can be controlled and monitored via a remote device (a PC). The challenge is to build the various software layers, on a realtime operating system like ecos to do the task. Degree of Difficulty: Hard, and Ability: Software Development, Basic Operating Systems, basic Hardware Interfacing COMP3221 lec37-vm-ii.26 Project 8: PS/2 and USB Controller For DSL Board Aim: The aim of this project is to design an PS/2 and USB Controller using the on-board FPGA chips. Degree of Difficulty: Hard, and Ability: Hardware Development, Basic Software development Project 9: Frame Grabber Device for CMOS Digital Camera Aim: The aim of this project is to build a high resolution web camera using a Kodak KAC-1310 CMOS image sensor. The pixel data would buffered in SRAM /SDRAM, compressed and uploaded through the Internet interface for display on a PC. Degree of Difficulty: Very Hard, and Ability: DSP, Hardware Development, Project 10: Audio Signal Processing Aim: The aim of this project is interface a codec to a DSP Audio Signal Processor/ Compressor built on the on- Board FPGAs Degree of Difficulty: Moderate to Hard, and Ability: DSP, Hardware Development, Basic Software development COMP3221 Basic lec37-vm-ii.27 Software development COMP3221 lec37-vm-ii.28

8 Things to Remember (#1/2) Apply Principle of Locality Recursively Reduce Miss Penalty? add a (L2) cache Manage memory to disk? Treat as cache Included protection as bonus, now critical Use Page Table of mappings vs. tag/data in cache Things to Remember (#2/2) Virtual allows protected sharing of memory between processes with less swapping to disk, less fragmentation than always swap or base/bound Spatial Locality means Working Set of Pages is all that must be in memory for process to run fairly well Virtual memory to Physical Translation too slow? Add a cache of Virtual to Physical Address Translations, called a TLB COMP3221 lec37-vm-ii.29 COMP3221 lec37-vm-ii.30 Things to Remember Spatial Locality means Working Set of Pages is all that must be in memory for process to run fairly well Virtual memory to Physical Translation too slow? Add a cache of Virtual to Physical Address Translations, called a TLB TLB to reduce performance cost of VM COMP3221 lec37-vm-ii.31