VGA Port Companion Circuit

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Wesley Welch
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1 GA Port Companion Circuit Features Single chip solution for the GA port interface Includes ESD protection, level shifting, and RGB termination Seven channels of ESD protection for all GA port connector pins meeting IEC Level-4 ESD requirements (8K contact discharge) ery low loading capacitance from ESD protection diodes on IDEO lines, 4pF typical 75Ω termination resistors for IDEO lines (matched to 1% typ.) TTL to CMOS level-translating buffers with power down mode for HSYNC and SYNC lines Bi-directional level shifting N-channel FETs provided for DDC_CLK & DDC_DATA channels Compact 24-pin QSOP package Lead-free version available Applications Notebook computers with GA port Desktop PCs with GA port Product Description The PACGA200 incorporates seven channels of ESD protection for all signal lines commonly found in a GA port. ESD protection is implemented with current steering diodes designed to safely handle the high surge currents encountered with IEC Level- 4 ESD Protection (8K contact discharge). When a channel is subjected to an electrostatic discharge, the ESD current pulse is diverted via the protection diodes into either the positive supply rail or ground where it may be safely dissipated. Separate positive supply rails are provided for the IDEO, DDC and SYNC channels to facilitate interfacing with low voltage ideo Controller ICs and provide design flexibility in multisupply-voltage environments. Two non-inverting drivers provide buffering for the HSYNC and SYNC signals from the ideo Controller IC (SYNC_IN1, SYNC_IN2). These buffers accept TTL input levels and convert them to CMOS output levelsthat swing between Ground and CC 4 (cont d next page). Simplified Electrical Schematic CC 1 2 CC 2 12 CC 3 14 _BIAS D1 13 CC R S SYNC_OUT1 R C IDEO_1 IDEO_2 IDEO_3 TERM_1 TERM_2 TERM_3 GNDA GNDA DDC_IN1 16 CC 2 R C DDC_IN SYNC_IN1 DDC_OUT1 R B CC 3 CC DDC_OUT2 21 SYNC_IN2 23 SD1 11 PWR_UP R C 22 SYNC_OUT2 R S 24 SD2 490 N. McCarthy Blvd., Milpitas, CA Tel: Fax:

2 Product Description (cont d) These drivers have nominal 60Ω output impedance (R S ) to match the characteristic impedance of the HSYNC & SYNC lines of the video cables typically used in PC applications. Two N-channel FETs provide the level shifting function required when the DDC controller is operated at a lower supply voltage than the monitor. Three 75Ω termination resistors suitable for terminating the video signals from the video DAC are also provided. These resistors have separate input pins to allow insertion of additional EMI filtering, if required, between the termination point and the ESD protection diodes. These resistors are matched to better than 2% for excellent signal level matching for the R/G/B signals. When the PWR_UP input is driven LOW the SYNC inputs can be floated without causing the SYNC buffers to draw any current from the CC 4 supply. When the PWR_UP input is LOW the SYNC outputs are driven LOW. An internal diode (D1 in schematic on previous page) is also provided so that CC 3 can be derived from CC 4, if desired, by connecting CC 3 to _BIAS. In applications where CC 4 may be powered down, diode D1 blocks any DC current paths from the DDC_OUT pins back to the powered down CC 4 rail via the top ESD protection diodes. The PACGA200 device is housed in a 24-pin QSOP package and is available with optional lead-free finishing. PACKAGE / PINOUT DIAGRAM Top iew CC SD2 CC SD1 IDEO_ SYNC_OUT2 IDEO_ SYNC_IN2 IDEO_ SYNC_OUT SYNC_IN1 GNDA 7 18 DDC_OUT2 TERM_ DDC_IN2 TERM_ DDC_IN1 TERM_3 15 DDC_OUT1 PWR_UP CC 3 CC _BIAS Note: This drawing is not to scale. 24-pin QSOP Ordering Information PART NUMBERING INFORMATION Lead-free Finish Pins Package Ordering Part Number 1 Part Marking 24 QSOP-24 PACGA200QR PACGA200QR Note 1: Parts are shipped in Tape & Reel form unless otherwise specified N. McCarthy Blvd., Milpitas, CA Tel: Fax:

3 LEAD(s) NAME DESCRIPTION PIN DESCRIPTIONS 1 CC 4 Positive voltage supply pin. This is an isolated CC pin for the SYNC_1, SYNC_2, SD1 and SD2 circuits. 2 CC 1 Positive voltage supply pin. This is an isolated CC pin for the IDEO_1, IDEO_2 and IDEO_3 ESD circuits. 3-5 IDEO_1, IDEO_2, IDEO_3 RGB ideo Protection Channels. These pins tie to the RGB video lines (for example, the Blue signal) between the GA controller device and the video connector. 6 Digital Ground reference supply pin. 7 GNDA Ground reference supply pin for TERM_1, TERM_2 and TERM_3 pins. 8- TERM_1, TERM_2, TERM_3 RGB ideo Termination Channels. These pins tie to the RGB video lines (for example, the Blue signal) providing a 75Ω termination to GNDA for the given video channel. 11 PWR_UP Sync Signal Output 1. Ties to the video connector side of one of the sync lines (for example the Horizontal Sync signal). 12 CC 2 Positive voltage supply pin. This is an isolated CC pin for the DDC_IN1 and DDC_IN2 input circuits. Defines the logic one level for the DDC_OUTn outputs. 13 _BIAS Used to derive CC3 from CC4 input. 14 CC 3 Positive voltage supply pin. This is an isolated CC pin for the DDC_OUT1 and DDC_OUT2 ESD protection circuits. 15 DDC_OUT1 DDC Signal Output 1. Connects to the connector side of one of the DDC signals (for example, the bidirectional DDC_Data serial line). 16 DDC_IN1 DDC Signal Input 1. Connects to the GA Controller side of one of the DDC signals (for example, the bidirectional DDC_Data serial line). 17 DDC_IN2 DDC Signal Input 2. Connects to the GA Controller side of one of the DDC signals (for example, the bidirectional DDC_Clk). 18 DDC_OUT2 DDC Signal Output 2. Connects to the connector side of one of the DDC signals (for example, the bidirectional DDC_Clk). 19 SYNC_IN1 Sync Signal Buffer Input 1. Connects to the GA Controller side of one of the sync lines (for example, the Horizontal Sync signal). 20 SYNC_OUT1 Sync Signal Buffer Output 1. Connects to the video connector side of one of the sync lines (for example the Horizontal Sync signal). 21 SYNC_IN2 Sync Signal Buffer Input 2. Connects to the GA Controller side of one of the sync lines (for example, the ertical Sync signal). 22 SYNC_OUT2 Sync Signal Buffer Output 2. Connects to the video connector side of one of the sync lines (for example the ertical Sync signal). 23 SD1 Sync Signal Filter 1. Connects to the video connector side of one of the sync lines (for example the ertical Sync signal). 24 SD2 Sync Signal Filter 2. Connects to the video connector side of one of the sync lines (for example the Horizontal Sync signal). 490 N. McCarthy Blvd., Milpitas, CA Tel: Fax:

4 Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNITS CC 1, CC 2, CC 3, and CC 4 Supply oltage [GND - 0.5] to +6.0 Diode D1 Forward DC Current 0 μa Storage Temperature Range -65 to +150 C DC oltage at Inputs IDEO_1, IDEO_2, IDEO_3 TERM_1, TERM_2, TERM_3 DDC_IN1, DDC_IN2 DDC_OUT1, DDC_OUT2 SYNC_IN1, SYNC_IN2 (GND - 0.5) to ( CC ) -6.0, +6.0 (GND - 0.5) to ( CC ) (GND - 0.5) to ( CC ) (GND - 0.5) to ( CC ) Package Power Rating 00 mw STANDARD OPERATING CONDITIONS PARAMETER RATING UNITS Operating Temperature Range 0 to +70 C ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I CC1 CC 1 Supply Current CC 1 = 5.0, IDEO inputs at CC 1 or GND μa level I CC2, CC 2 & CC 3 Supply CC 2 = CC 3 = 5.0 μa I CC3 Current I CC4 CC 4 Supply Current CC 4 = 5.0; SYNC inputs at GND or CC 4 μa level; PWR-UP pin at CC 4; SYNC outputs unloaded CC 4 = 5.0; SYNC inputs at 3.0; PWR-UP pin at CC 4; SYNC outputs unloaded 200 μa CC 4 = 5.0; PWR-UP input at GND; SYNC outputs unloaded μa BIAS BIAS Open Circuit oltage No external current drawn from BIAS pin CC R T ideo Termination Ω Resistance R T Resistance Matching 1 2 % IH Logic High Input oltage CC 4 = 5.0; See Note N. McCarthy Blvd., Milpitas, CA Tel: Fax:

5 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IL Logic Low Input oltage CC 4 = 5.0; See Note OH Logic High Output oltage I OH = -4mA, CC 4 = 5.0; See Note OL Logic Low Output oltage I OL = 4mA, CC 4 = 5.0; See Note R OH Output Resistance See Note Ω R OL Ω R B,R P Resistor alue PWR_UP = CC 3 = MΩ R C I N I OFF ON C IN t PLH t PHL t R, t F ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) (CONT D) CC 2 Pull-down Resistor alue Input Current IDEO inputs HSYNC, SYNC inputs Off-state Leakage Current, Level-shifting NFET oltage drop across level shifting NFET when turned ON Input Capacitance IDEO_1,IDEO_2 & IDEO_3 inputs SYNC Drivers L => H Propagation Delay SYNC Drivers H => L Propagation Delay SYNC Drivers Output Rise & Fall Times CC 2 = MΩ CC 1= 5.0; IN = CC 1 or GND CC 4 = 5.0; IN = CC 4 or GND ( CC 2 - DDC_IN ) < 0.4; DDC_OUT = CC 2 ( CC 2 - DDC_OUT ) < 0.4; DDC_IN = CC 2 CC 2= 2.5; S = GND; I DS = 3mA 0.15 Note 4 applies for all cases; CC 1 = 5.0; IN = 2.5; measured at 1MHz CC 1 = 2.5; IN = 1.25; measured at 1MHz C L = 50pF; CC =5.0,Input t R and t F < 5ns ns C L = 50pF; CC =5.0; Input t R and t F < 5ns ns C L = 50pF; CC =5.0; Input t R and t F < 5ns (measured % - 90%) μa μa μa μa pf pf ns ESD ESD Withstand oltage CC 1 = CC 3 = CC 4 = 5; Notes 3 & 4 ±8 k Note 1: All parameters specified over standard operating conditions unless otherwise noted. Note 2: This parameter applies only to the HSYNC and SYNC channels. HSYNC and SYNC have 8mA drivers with R S added in series to terminate transmission line. Note 3: Per the IEC International ESD Standard, Level 4 contact discharge method. CC 1, CC 3 and CC 4 must be bypassed to GND via a low impedance ground plane with a 0.2uF, low inductance, chip ceramic capacitor at each supply pin. ESD pulse is applied between the applicable pins and GND. ESD pulse can be positive or negative with respect to GND. Applicable pins are: IDEO_1, IDEO_2, IDEO_3, SYNC_OUT1, SD1, SYNC_OUT2, SD2, DDC_OUT1 and DDC_OUT2. All other pins are ESD protected to the industry standard 2k per the Human Body Model (MIL-STD-883, Method 3015). Note 4: This parameter is guaranteed by design and characterization. 490 N. McCarthy Blvd., Milpitas, CA Tel: Fax:

6 Test Circuit Information Average Current through CC 4 (I CC 4) The circuit in Figure 1 was used to characterize I CC 4 current as SYNC_IN signal frequency varies. A square wave signal was connected to the input of one of the SYNC buffers (i.e. pin 19 or pin 21). The frequency of this signal was varied between 0 and 0 khz. The risetime and falltime was kept constant at ns. Three different values of C1 were used: 0pF, 50pF and 0pF. The results are plotted in Figure 2. CC 4 +5 I CC SYNC_IN SYNC_OUT 0 C1 Figure 1. Sync Buffer I CC 4 Test Circuit 0 I CC4 vs. SYNC_IN Frequency ICC4, ua Frequency, khz 0pF 50pF 0pF Figure 2. I CC 4 vs. SYNC_IN Frequency Performance Data N. McCarthy Blvd., Milpitas, CA Tel: Fax:

7 Application Information DDC_ CC IDEO_DAC_ CC DDC_Data DDC_Clk R1 R2 0.2uF CC 2 CC 1 DDC_IN1 DDC_IN2 0.2uF 0.2uF CC 3_BIAS CC 4 PWR_UP 0.2uF ideo Connector ideo Controller H-Sync -Sync Red Grn Blue F** F** F** SYNC_IN1 SYNC_IN2 TERM_1 TERM_2 TERM_3 PACGA200 DDC_OUT1 DDC_OUT2 SYNC_OUT1 SYNC_OUT SF** SF** DDC_Data DDC_Clk F** - IDEO EMI Filter SF** - SYNC EMI Filter 3 IDEO_1 4 IDEO_2 5 IDEO_3 SD1 23 SD2 24 H-Sync -Sync GNDA 7 6 R G B Figure 3. Typical Connection Diagram A resistor may be necessary between the CC 3 pin and ground if protection against a stream of ESD pulses is required while the PACGA200 is in the power-down state. The value of this resistor should be chosen such that the extra charge deposited into the CC 3 bypass capacitor by each ESD pulse will be discharged before the next ESD pulse occurs. The maximum ESD repetition rate specified by the IEC standard is one pulse per second. When the PACGA200 is in the power-up state, an internal discharge resistor is connected to ground via an FET switch for this purpose. For the same reason, CC 1 and CC 4 may also require bypass capacitor discharging resistors to ground if there are no other components in the system to provide a discharge path to ground. GNDA, the reference voltage for the 75Ω resistors is not connected internally to and should ideally be connected to the ground of the video DAC IC. 490 N. McCarthy Blvd., Milpitas, CA Tel: Fax:

8 Mechanical Details QSOP Mechanical Specifications: PACGA200 devices are packaged in 24-pin QSOP packages. Dimensions are presented below. Mechanical Package Diagrams For complete information on the QSOP-24 package, see the California Micro Devices QSOP Package Information document TOP IEW D PACKAGE DIMENSIONS Package QSOP (JEDEC name is SSOP) H Pin 1 Marking E Pins 24 Dimensions Millimeters Inches Min Max Min Max A A B SIDE IEW C D E SEATING PLANE A B e A1 e 0.64 BSC BSC H L END IEW # per tube 55 pcs* # per tape 2500 pcs and reel Controlling dimension: inches C L * This is an approximate number which may vary. Package Dimensions for QSOP N. McCarthy Blvd., Milpitas, CA Tel: Fax:

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