PI2EQX5964ZFE EvalBoard Rev.A User Guide

Transcription

1 PIEQX5964ZFE EvalBoard Rev.A User Guide Introduction Pericom Semiconductor s PIEQX5964ZFE is a low power, PCIE compliant signal redriver. The device provides programmable equalization, amplification, and de-emphasis by using 8 elect bits, to optimize performance over a variety of physical mediums by reducing Inter-Symbol Interference. PIEQX5964ZFE supports eight 00-Ohm Differential CML data I/O s between the Protocol ASIC to a switch fabric, across a backplane, or to extend the signals across other distant data pathways on the user s platform. The integrated equalization circuitry provides fl edibility with signal integrity of the signal before the re-driver, whereas the integrated emphasis circuitry provides flexibility with signal integrity of the signal after the redriver. In addition to providing signal re-conditioning, Pericom s PIEQX5964ZFE also provides power management Standby mode operated by a Power Down pin. This user guide describes how to use PIEQX5964ZFE ReDriver in the evaluation board. Figure shows top view and bottom view of PIEQX5964ZFE EVB. Figurea Top View of PIEQX5964ZFE EVB Page of 9 AN 05/05/04

2 Figureb Bottom View of PIEQX5964ZFE EVB Board Operation Logical Block Diagram Figure shows the logical block diagram of PIEQX5964ZFE. Figure. Logical Block Diagram of PIEQX5964ZFE Page of 9 AN 05/05/04

3 Board Circuit ) Power Supply On the EVB, the power supply is from 3-Pin header- and GND mark as below. Figure3. and GND pin Header Location ) Configuration Control PIEQX5964ZFE provides IC configuration control depending on the state of the MODE pin input (red circle in Figure4). When MODE is set LOW, reprogramming of the control registers via IC is allowed. MODE pin has internal 00K pullup resistor. So it should be pull down by Jumper MODE pin externally. Figure4 shows the Mode pin location on EVB. Figure4. MODE pin Header Location Page 3 of 9 AN 05/05/04

4 The integrated IC interfaces operate as a slave device, supporting standard rate operation of 00Kbps, with 7- bit addressing mode and LSB indication either a read or write operation as shown below. The address for a specific device is determined by A0, A and A4 pins with internal PULL-UP resistors. So up to eight PIEQX5964 devices can be connected to a single IC bus. Figure4 shows A4, A and A0 pin header location in Blue circle. Data bytes must be 8-bits long and transferred with MSB first. Please see IC data transfer diagram in Page6 of datasheet. For data byte definition as below, please see Page8 - of datasheet in detail. For IC inputs, SCL and SDA pin are tolerant with +3.3V power. Figure5 is SCL and SDA pins location on EVB. Figure5. SCL and SDA pin Header Location NOTE: Other pins, PD#, RXD_A, RXD_B, LB# and RES# should be NC if IC mode is selected. Page 4 of 9 AN 05/05/04

5 IC Configuration Sequence Figure6 is WRITE sequence. Figure6 IC WRITE Sequence Diagram Note: there is one DUMMY byte to be added into sequence. Figure 7 is one sample for write sequence at Address=C0 (A4, A, A0 are pulled down) and Data byte[0..]=00,00,f0,00,00,ff,ff,ff,00,00,00,ef. C0 DUMMY BYTE Figure8 is READ sequence. Figure7 IC WRITE Sequence Sample Figure8 IC READ Sequence Diagram Note: there is NO DUMMY byte to be added into sequence. Figure9 is one sample for read sequence sample at Address=C (A4, A, A0 are pulled down) and Data byte[0..]=08,00,f0,00,00,ff,ff,ff,00,00,00,ef. Page 5 of 9 AN 05/05/04

6 C 08 Figure9 IC READ Sequence Sample Note: Byte0=08 means Channel-A has signal input. Page 6 of 9 AN 05/05/04

7 Appendix A: PCB Schematic C 0.u NC SCL SDA PD# A0RX+ A0RX- C36 0.u_0306 U HEATGND 57 GND 56 GND 55 NC SCL SDA 5 5 PD# RXD_A 50 B0TX+ C37 0.u_ C3 0.u_0306 B0RX+ A0TX+ 47 B0TX- C6 0.u_ A0RX+ A0TX- 46 C3 0.u_0306 B0RX- 4 A0RX- B0RX B0TX+ B0RX- 6 B0TX- 44 ARX+ C7 0.u_ C30 0.u_0306 ATX+ 7 ATX+ 4 ARX- C8 0.u_ ARX+ ATX- 4 C9 0.u_0306 ATX- 9 ARX- BRX BTX- BRX+ BTX+ 39 BTX- C9 0.u_ C8 0.u_0306 BRX- ATX+ 37 BTX+ C0 0.u_ ARX+ ATX- 36 C7 0.u_0306 BRX+ 4 ARX- BRX BTX- BRX+ 6 BTX+ 34 ARX+ C 0.u_ C6 0.u_0306 ATX+ 7 A3TX+ 3 ARX- C 0.u_ A3RX+ A3TX- 3 C5 0.u_0306 ATX- 9 A3RX- B3RX B3TX+ B3RX- B3TX- 9 BTX- C3 0.u_0306 C4 0.u_0306 BRX- BTX+ C4 0.u_0306 C3 0.u_0306 BRX+ PIEQX5964ZFE@TQFN56 RXD_B MODE RESET# A4 A0 A LB# C33 0.u_0306 C5 0.u_0306 A3RX- C6 0.u_0306 C 0.u_0306 A3TX- B3TX+ C7 0.u_0306 C0 0.u_0306 B3RX+ C8 0.u_0306 C9 0.u_0306 B3RX- RXD_B MODE RES# A4 A0 A LB# 3 C43 0.u C4 0.u C4 0.u C40 0.u C39 0.u C38 0.u C 0.u C3 0.u C4 0.u C5 0u GND 3 RXD_A C35 0.u_0306 C34 0.u_0306 A0TX+ A0TX- A3RX+ C 0.u_0306 A3TX+ B3TX- Page 7 of 9 AN 05/05/04

8 Appendix A: PCB TOPVIEW Page 8 of 9 AN 05/05/04

9 History Version.0 Original Version Nov. 4, 00 Page 9 of 9 AN 05/05/04