PI2EQX6804-ANJE Four-lane SAS/SATA ReDriver Application Information May 13, 2011

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Contents General Introduction How to use pin strap and I2C control External Components Requirement Layout Design Guide Power Supply

application circuit PCB Layout Sample Pericom SATA/SAS ReDriver Selection Table PI2EQX6804-ANJE Four-lane SAS/SATA ReDriver Application

optimum signal to precompensate for losses across long trace or noisy environments so that the receiver gets a clean with good eye

Packaging: 100-contact LFBGA (11x11mm) for PI2EQX6804-ANJE Main Application: Server Desktop Storage/Workstation Figure1 is typical

1 Contents General Introduction How to use pin strap and I2C control External Components Requirement Layout Design Guide Power Supply Bypassing Power Supply Sequencing Equalization Setting Output Swing Setting De-emphasis Setting I2C Configuration Sequence Typical application circuit PCB Layout Sample Pericom SATA/SAS ReDriver Selection Table PI2EQX6804-ANJE Four-lane SAS/SATA ReDriver Application Information May 13, 2011 General Introduction PI2EQX6804-ANJE provides flexible output strength and de-emphasis controls to provide the optimum signal to precompensate for losses across long trace or noisy environments so that the receiver gets a clean with good eye opening. PI2EQX6804-ANJE provides pin strap and I2C function to set output swing/de-emphasis and input equalization. Packaging: 100-contact LFBGA (11x11mm) for PI2EQX6804-ANJE Main Application: Server Desktop Storage/Workstation Figure1 is typical application sample. Figure1a Typical Application Sample Pericom Semiconductor Corp., 3545 N. First Street, San Jose, California, USA Page 1

2 How to use pin strap and I2C control for output swing/de-emphasis and input equalization of PI2EQX6804-A For PI2EQX6804-A, it provides two ways as below to set output swing/de-emphasis and input equalization. But for PI2EQX6864-A only provides one way-i2c function which is completely the same as PI2EQX6804-A. 1, pin-strap function 2, I2C function And they depend on the state of the MODE pin with 100k internal pull-up resistor. When MODE pin is set HIGH, all the configuration input pins determine all the configuration settings. Note that all of these control pins have 100k internal PULL-UP resistor, so only external pull-down resistor is required. All the configuration input pins include D0_A, D1_A, D2_A, S0_A, S1_A, SEL0_A, SEL1_A, SEL2_A, D0_B, D1_B, D2_B, S0_B, S1_B, SEL0_B, SEL1_B, SEL2_B, DE_A, DE_B, LB# and PD#. When MODE pin is LOW, all the internal configuration registers can be programmed by I2C function. Note that during initial power-on, the value at the configuration input pins will be latched to the configuration registers as initial startup states. The integrated I2C interfaces operate as a slave device, supporting standard rate operation of 100Kbps, with 7- bit addressing mode and LSB indication either a read or write operation as shown below. The address for a specific device is determined by A0, A1 and A4 pins with internal pull-up resistors. So up to eight PI2EQX6804-A devices can be connected to a single I2C bus. Data bytes must be 8-bits long and transferred with MSB first. Please see I2C data transfer diagram in Page13 of datasheet. For data byte definition as below, please see Page8-11 of datasheet in detail. For I2C inputs, SCL and SDA pin are tolerant with +3.3V power. For I2C configuration sequence in detail, please see Page6-7 in this file. External Components Requirement PI2EQX6804-A requires AC coupling capacitors for all redriver inputs and outputs. High-quality, low-esr, X7R, 10nF, 0402-sized capacitors are recommended. Pericom Semiconductor Corp., 3545 N. First Street, San Jose, California, USA Page 2

Layout Design Guide Layout Considerations for Differential Pairs The trace length miss-matching shall be less than 5 mils for the + and traces in the same pairs Use wider trace width, with 100ohm

3 Layout Design Guide Layout Considerations for Differential Pairs The trace length miss-matching shall be less than 5 mils for the + and traces in the same pairs Use wider trace width, with 100ohm differential impedance, to minimize the loss for long routes Target differential Zo of 100ohm ±20% More pair-to-pair spacing for minimal crosstalk coupling, it is recommended to have >3X gap spacing between differential pairs. It is preferable to route differential lines exclusively on one layer of the board, particularly for the input traces The use of vias should be avoided if possible, if vias must be used, they should be used sparingly and must be placed symmetrically for each side of a given differential pair. Route the differential signals away from other signals and noise sources on the printed circuit board Route the differential pairs with the difference length in 2 before and after PI2EQX6804-A part only if the PIN CONTROL is used because all the setting will be effective on four ports at the same time. PCB Layout Trace Routings Figure2 Layout Sample for Trace Routings Power-Supply bypass More careful attention must be paid to the details associated with high-speed design as well as providing a clean power supply; there are some approaches as recommendation. The supply (VDD) and ground () pins should be connected to power planes routed on adjacent layers of the printed circuit board. The distance to plane should be <50mil. The layer thickness of the dielectric should be minimized so that the VDD and planes create a low inductance supply with distributed capacitance. Pericom Semiconductor Corp., 3545 N. First Street, San Jose, California, USA Page 3

4 Careful attention to supply bypassing through the proper use of bypass capacitors is required. A low-esr 0.01uF bypass capacitor should be connected to each VDD pin such that the capacitor is placed as close as possible to PI2EQX6804-A. Smaller body size capacitors can help facilitate proper component placement. The distance of capacitors to IC body should be <100mil. One capacitor with capacitance in the range of 1uF to 10uF should be incorporated in the power supply bypassing design as well. It is can be either tantalum or an ultra-low ESR ceramic. Power Supply Sequencing Proper power supply sequencing is recommened for all devices. Always apply and VDD before applying signals., especially if the signal is not current limited. Caution: Do NOT exceed the absolute maximum ratings because stresses beyond the listed ratings can cause permanent damage to the device. Equalization Setting Various Input Trace and Eye Test with different EQ setting Figure3 is PI2EQX6804-A test setup for different EQ setting, R is PI2EQX6804-A. Signal Source: PRBS2^7-1 pattern, Differential Voltage is 600mV, Pre-emphasis is 0dB Signal Generator Input Trace SELx[2..0] Setting Fixture 24inch SMA Cable R Tektronic Sampling Scope TP3 D[2..0]=000 S[1..0]=00 TP4 Figure3 PI2EQX6804-A test setup for different equalization setting Table1 Eye Diagram at TP4 vs. Input FR4 trace and EQ setting at 6Gb/s for PI2EQX6804-A Input Trace Length SEL[2..0] Setting Input Eye at TP3 Output Eye at TP4 6 inch 3.2dB FR4 Lab trace (SEL[2,1,0] (-2dB loss at 6GHz) =010) Eye Diagram vs. EQ setting at 6Gb/s 18 inch FR4 Lab trace (-6dB loss at 3GHz) 30 inch FR4 Lab trace (-10dB at 3GHz) 48 inch FR4 Lab trace (-16dB at 3GHz) 6.9dB (SEL[2,1,0] =100) 10.4dB (SEL[2,1,0] =110) 13.8dB (SEL[2,1,0] =111) Pericom Semiconductor Corp., 3545 N. First Street, San Jose, California, USA Page 4

.0]=000 TP4 Figure4 PI2EQX6804-A test setup for different output swing setting Table2 Output Swing at TP4 vs. OS setting at 3Gb/s and 6Gb/s for PI2EQX6804-A S[1..0]=00 S[1..0]=01 S[1..0]=10 S[1.

5 Output Swing Setting Figure4 is PI2EQX6804-A test setup for different output swing setting, R is PI2EQX6804-A. Signal Source: PRBS2^7-1 pattern, Differential Voltage is 500mV, Pre-emphasis is 0dB MB S[1..0] Setting Fixture 5cm 100ohm Trace R Agilent Sampling Scope D[2..0]=000 SELx[2..0]=000 TP4 Figure4 PI2EQX6804-A test setup for different output swing setting Table2 Output Swing at TP4 vs. OS setting at 3Gb/s and 6Gb/s for PI2EQX6804-A S[1..0]=00 S[1..0]=01 S[1..0]=10 S[1..0]=11 Output Swing at TP4 vs. OS setting at 3Gb/s Output Swing at TP4 vs. OS setting at 6Gb/s De-emphasis Setting Figure5 is PI2EQX6804-A test setup for different De-emphasis setting, R is PI2EQX6804-A. Signal Source: PRBS2^7-1 pattern, Differential Voltage is 500mV, Pre-emphasis is 0dB MB D[2..0] Setting Fixture 5cm 100ohm Trace R Agilent Sampling Scope S[1..0]=00 SELx[2..0]=000 TP4 Figure5 PI2EQX6804-A test setup for different De-emphasis setting Pericom Semiconductor Corp., 3545 N. First Street, San Jose, California, USA Page 5

Table3 De-emphasis at TP4 vs. D[2..0] setting at 3Gb/s and 6Gb/s for PI2EQX6804-A D[2..0]=000 D[2..0]=010 D[2.

De-em setting at 6Gb/s I2C Configuration Sequence Figure6 is WRITE sequence.

Figure 7 is one sample for write sequence at Address=C0 (A4, A1, A0 are pulled down) and Data byte[0.

6 Table3 De-emphasis at TP4 vs. D[2..0] setting at 3Gb/s and 6Gb/s for PI2EQX6804-A D[2..0]=000 D[2..0]=010 D[2..0]=111 Output De-emphasis at TP4 vs. De-em setting at 3Gb/s Output De-emphasis at TP4 vs. De-em setting at 6Gb/s I2C Configuration Sequence Figure6 is WRITE sequence. Figure6 I2C WRITE Sequence Diagram Note: there is one DUMMY byte to be added into sequence. Figure 7 is one sample for write sequence at Address=C0 (A4, A1, A0 are pulled down) and Data byte[0..11]=00,00,f0,00,00,ff,ff,ff,00,00,00,ef. C0 DUMMY BYTE Figure7 I2C WRITE Sequence Sample Pericom Semiconductor Corp., 3545 N. First Street, San Jose, California, USA Page 6

7 Figure8 is READ sequence. Figure8 I2C READ Sequence Diagram Note: there is NO DUMMY byte to be added into sequence. Figure9 is one sample for read sequence sample at Address=C1 (A4, A1, A0 are pulled down) and Data byte[0..11]=08,00,f0,00,00,ff,ff,ff,00,00,00,ef. C1 08 Figure9 I2C READ Sequence Sample Note: Byte0=08 means Channel-A2 has signal input. Pericom Semiconductor Corp., 3545 N. First Street, San Jose, California, USA Page 7

Typical Application Circuit Figure10 shows typical application circuit of PI2EQX6804-A. +1.2V +3.3V +3.3V EC1 + 22u_3528 C1 0.1u_0402 C2 C3 C4 0.1u_0402 0.

2V R10 470 R7 470 HOST_TX Close to TX C32 C34 C35 C36 C37 C38 C31 C33 VDD A1 VDD A4 VDD A7 VDD A10 VDD B6 VDD D1 VDD D4 VDD D7 VDD D10 VDD G1 VDD G4 VDD G7 VDD G10 VDD K1 VDD K4 VDD K7 VDD K10 U1 C4

8 Typical Application Circuit Figure10 shows typical application circuit of PI2EQX6804-A. +1.2V +3.3V +3.3V EC1 + 22u_3528 C1 0.1u_0402 C2 C3 C4 0.1u_ u_ u_0402 Q3 MMBT3904 SIG_AR D3 LED Q2 MMBT3904 SIG_BR D2 LED +1.2V R R7 470 HOST_TX Close to TX C32 C34 C35 C36 C37 C38 C31 C33 VDD A1 VDD A4 VDD A7 VDD A10 VDD B6 VDD D1 VDD D4 VDD D7 VDD D10 VDD G1 VDD G4 VDD G7 VDD G10 VDD K1 VDD K4 VDD K7 VDD K10 U1 C4 B4 A0RX+ B1 A0RX- C1 A1RX+ G3 A1RX- G2 A2RX+ K2 A2RX- K3 A3RX+ A3RX- A0TX+ A0TX- A1TX+ A1TX- A2TX+ A2TX- A3TX+ A3TX- C7 B7 B10 C10 G8 G9 K9 K8 C15 C16 C17 C18 C19 C20 C21 C22 Device_RX HOST Controller HOST_RX R1 DE_A R2 SEL0_A R3 SEL1_A R4 SEL2_A R9 S0_A R12 S1_A R14 D0_A R20 D1_A R22 D2_A SIG_A Close to TX C23 C24 C25 C26 C27 C28 C29 C30 B5 E1 E2 E3 E6 E8 E4 E5 D5 E9 A3 A2 D2 D3 H1 J1 J4 H4 SIG_B D2_B D1_B D0_B S1_B S0_B SEL2_B SEL1_B SEL0_B DE_B B0RX+ B0RX- B1RX+ B1RX- B2RX+ B2RX- B3RX+ B3RX- DE_A SEL0_A SEL1_A SEL2_A S0_A S1_A D0_A D1_A D2_A SIG_A B0TX+ B0TX- B1TX+ B1TX- B2TX+ B2TX- B3TX+ B3TX- PI2EQX6804-A@LBGA100 F2 K5 J6 G6 F3 F5 F7 F9 F10 H5 A8 A9 D9 D8 H10 J10 J7 H7 D2_B D1_B D0_B S1_B S0_B SEL2_B SEL1_B SEL0_B DE_B R6 R13 R15 R21 R23 R25 R26 R27 R28 SIG_B Close to TX C39 C41 C43 C45 C46 C40 C42 C44 Device or Connector Device_TX R32 R33 R35 MODE LB# PD# G5 F8 C6 MODE LB# PD# SCL SDA A0 A1 A4 A5 A6 H6 F6 K6 A0 A1 A2 R34 R36 R37 SCL SDA +3.3V R30 10k_0402 R29 10k_0402 B2 B3 B8 B9 C2 C3 C8 C9 H2 H3 H8 H9 J2 J3 J8 J9 J5 E7 E10 D6 C5 F4 F1 Figure10 Typical Application Circuit of PI2EQX6804-A HOST_SCLTo I2C Host Controller HOST_SDA PCB Layout Sample Figure11 shows typical layout routing of PI2EQX6804-A. Top Layer View Bottom Layer View Figure11 Typical Layout Routing of PI2EQX6804-A Pericom Semiconductor Corp., 3545 N. First Street, San Jose, California, USA Page 8

9 Pericom SATA/SAS ReDriver Selection Table Pericom Semiconductor Corp., 3545 N. First Street, San Jose, California, USA Page 9

10 History Version 1.0 Original Version May. 13, 2011 Version 1.1 Add product selection table May.29, 2013 Pericom Semiconductor Corp., 3545 N. First Street, San Jose, California, USA Page 10

PI2EQX6874ZFE 4-lane SAS/SATA ReDriver Application Information

PI2EQX6874ZFE 4-lane SAS/SATA ReDriver Application Information Contents General Introduction How to use pin strap and I2C control External Components Requirement Layout Design Guide Power Supply Bypassing Power Supply Sequencing Equalization Setting Output Swing Setting