PI3EQX1204-BZHE minisas EVB User Guide
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1 PIEQX0-BZHE minisas EVB User Guide Introduction The PIEQX0-B is a SAS/0Gb Ethernet, differential channels ReDriver. It provides 6 steps programmable equalization, steps output swing, pre-shoot and de-emphasis by IC control to optimize performance over a variety of physical mediums by reducing inter-symbol interference. The intergrated equalization circuitry provides flexibility with signal integrity of the signal before the ReDriver, whereas the integrated de-emphasis and pre-shoot circuity provides flexibility with signal integrity of the signal after the ReDriver. This user guide describes how to use PIEQX0-BZHE minisas EVB in the system. Figure shows top view and bottom view of PIEQX0-BZHE minisas EVB. Figurea. TOP view of PIEQX0-BZHE minisas EVB Figureb. Bottom view of PIEQX0-BZHE minisas EVB Page of 9 AN 05/05/0 6//0
2 Board Operation Logical Block Diagram Figure shows the logical block diagram of PIEQX0-BZHE. Figure. Logical Block Diagram of PIEQX0-BZHE Board Setting and Operation ) Power Supply On the EV board, there are two ways for the power supply below.. From two -Pin headers (JP as.v input, JP as ground). For this.v current, it must be keep A capability for EVB.. From two Banana Jacks (JP7 (RED) as V input, JP8 (Black) as ground). For this V current, it must be keep 800mA capability for EVB. JP7 Banana Jack V EC5 00u_7 JP8 Banana Jack EC 00u_7 SW7 SW_PUSH BUTTON 5 U VIN ON/OFF Pow_DNTSMD05 VOUT TRIM GND R7.k R7 NP R7 NP EC7 u_58 EC6 70u_7 JP JP C 0.u_00 C 0.u_00 C 0.u_00 C 0.u_00 C5 0u_0805 Figure. Power Circuit for PIEQX0-BZHE minisas EVB Page of 9 AN 05/05/0 6//0
3 Figure shows the power supply input locations on EVB. Figure. Power Supply Input Location on PIEQX0-BZHE minisas EVB ) Configuration Control PIEQX0-BZHE provides IC configuration control and Pin control depending on the state of the Pin_MODE pin input. This EV board has two PIEQX0-BZHE parts, one (U) for TX side from host to device, another (U) for RX side from device to host. When Pin_Mode is set to high or Open, each channel is programmed by the external pin voltage level. When Pin_Mode is set to low, each channel is programmed by the data stored in the IC bus. In EV board, the Figure5. PIN_MODE Location on PIEQX0-BZHE minisas EVB In PIEQX0-BZHE EVB, the DEFAULT is IC configuration control. So JP and JP5 are shorted to ground. And also the IC address was set to C0 for U and C for U. NOTE: there are pins for IC address, A0/A/A. And the address assignment is below, so the user can get total 8 addresses for 8 different ReDrivers. Table, the relations between address pins and IC address Address Pin A A A0 IC address ReDriver No. L L L 0xC0 L L H 0xC L H L 0xC L H H 0xC6 H L L 0xE0 5 H L H 0xE 6 H H L 0xE 7 H H H 0xE6 8 Page of 9 AN 05/05/0 6//0
4 Figure6. Configuration Pins Location on PIEQX0-BZHE minisas EVB Below are configuration tables for equalization, de-emphasis, Pre-shoot and swing control setting. Equalization Setting BST[0:] are the selection pins for the equalization selection for each direction in Table below. It is available for pin configuration and IC configuration control. Table. Equalizer Configuration Selection Table for PIEQX0-BZHE Page of 9 AN 05/05/0 6//0
![De-emphasis Setting: DE[0:]_A/B are the selection bits for the de-emphasis value in Table](/docs-images/80/80704462/images/5-3.jpg "below. It is available for pin configuration and IC configuration control. Table.")
5 De-emphasis Setting: DE[0:]_A/B are the selection bits for the de-emphasis value in Table below. It is available for pin configuration and IC configuration control. Table. De-emphasis Configuration Selection Table for PIEQX0-BZHE Pre-shoot Setting: PS[0:]_A/B are the selection bits for the pre-shoot value in Table below. It is available for pin configuration and IC configuration control. Values of 6db can only be selected when de-emphasis is set for 0 or.5db..5db can only be Table. Pre-shoot Configuration Selection Table for PIEQX0-BZHE Swing Setting: VOD[0:]_A/B are the selections for the output swing value in Table5 below. It is only available for IC configuration Table5. Swing Configuration Selection Table for PIEQX0-BZHE Part Enable Setting: PEN pin is for disable or enabling the PIEQX0-A part when necessary. In default, it is OPEN for normally operation. ) IC Configuration Function For detail IC configuration function please refer to Page6-9 on the datasheet. There is one connector-j as Figure7 on the EV board for IC connection. Figure7. IC Pins Location on PIEQX0-AZHE minisas EVB Page 5 of 9 AN 05/05/0 6//0
6 Below is IC configuration data format sample based on this EVB default setting for the reference. Figure8 is WRITE sequence. Figure8 IC WRITE Sequence Diagram Figure9 is one sample for write sequence. (0xC0, 00,00,F0,00,00,AA,00,55,F0,00,00,00,00,00,00,00) Figure0 is READ sequence. Figure9 IC WRITE Sequence Sample Figure0 IC READ Sequence Diagram Page 6 of 9 AN 05/05/0 6//0
7 Figure is one sample for read sequence. (0xC0, 00,00,F0,00,00,AA,00,55,F0,00,00,00,00,00,00,00) C Figure IC READ Sequence Sample Table6 is the relations between minisas ports and lanes of PIEQX0-BZHE on EVB. MiniSAS Port Pin Name at CONN JP Lane of PIEQX0-BZHE Pin Name at CONN JP Port0 Port Port Port RX0 U_A TX0 TX0 U_A RX0 RX U_A TX TX U_A RX RX U_A TX TX U_A RX RX U_A0 TX TX U_A0 RX ) EVB Function Test Connection Table6. Relations between minisas ports and lanes of PIEQX0-BZHE USB/IC tool to PC for IC write/read From HOST minisas HD cable JP JP To Device minisas HD cable Power Supply for.v Power and GND Page 7 of 9 AN 05/05/0 6//0
8 Appendix A: PCB Schematic JP JP A A6 A9 B B6 B9 C C6 C9 D D6 D9 JP C5 0u_0805 JP D D5 TX0 C5 TX0- C TX- D8 TX D7 TX- C7 TX C8 TX TX- RX0 RX0- RX- RX RX- RX RX RX- C 0.u_00 B B5 A5 A B8 B7 A7 A8 C 0.u_00 U_A0RX_P U_A0RX_N U_ARX_P U_ARX_N U_ARX_P U_ARX_N U_ARX_P U_ARX_N C C C6 C5 C8 C7 C9 C0 C 0.u_00 C 0.u_00 SW 8 U_BST0 7 U_BST 6 U_BST 5 U_BST SW_X_Half _Pitch U_ARXC_P U_ARXC_N U_ARXC_P U_ARXC_N U_ARXC_P U_ARXC_N U_A0RXC_P U_A0RXC_N U_DE U_DE0 U_A U_A U DE DE0 A0RX A0RX- GND ARX ARX- ARX ARX- GND ARX ARX- A A HGND BST BST 0 BST 9 BST0 PEN PIN_MODE U_BST U_BST U_BST U_BST0 8 PS 7 PS0 6 5 A0TX A0TX- ATX ATX- GND 0 9 ATX 8 ATX- 7 6 ATX 5 ATX- VOD A0 U_PS U_PS0 U_ATX_P U_ATX_N U_ATX_P U_ATX_N U_ATX_P U_ATX_N U_A0TX_P U_A0TX_N U_VOD U_A0 JP C7 C8 C C C0 C9 C5 C6 SW U_DE0 6 U_DE 5 U_PS0 U_PS U_VOD 5 U_A0 6 U_A 7 0 U_A 8 9 SW_X8_Half _Pitch U_A0TXC_P U_A0TXC_N U_ATXC_P U_ATXC_N U_ATXC_P U_ATXC_N U_ATXC_P U_ATXC_N A A6 A9 B B6 B9 C C6 C9 D D6 D9 RSRD A IntL A Vact B ModPrsl B minisas_ C minisas_ C Vman D Vact D C 0u_0805 Reserved IntL Vact ModPrsl Vman Vact TX0 TX0- TX- TX TX- TX TX TX- D D5 C5 C D8 D7 C7 C8 CON_Mini_SAS HD X Recept C7 0.u_00 C8 0.u_00 U_A0TXC_P U_A0TXC_N U_ATXC_P U_ATXC_N U_ATXC_P U_ATXC_N U_ATXC_P U_ATXC_N C9 0.u_00 C0 0.u_00 C8 C7 C C C6 C5 C C SW_X_Half _Pitch U_ATX_P U_ATX_N U_ATX_P U_ATX_N JP SW 8 U_BST0 7 U_BST 6 U_BST 5 U_BST U_PS U_PS0 U_A0TX_P U_A0TX_N U_ATX_P U_ATX_N U_VOD U_A0 U_PEN U DE DE0 A0RX A0RX- GND ARX ARX- ARX ARX- GND ARX ARX- A A HGND BST BST 0 BST 9 BST0 PEN PIN_MODE PIEQX0-BZHE@TQFN U_BST0 U_BST U_BST U_BST U_PIN MODE 8 PS 7 PS0 6 5 A0TX A0TX- ATX ATX- GND 0 9 ATX 8 ATX- 7 6 ATX 5 ATX- VOD A0 U_DE U_DE0 U_A U_A U_ARXC_P U_ARXC_N U_ARXC_P U_ARXC_N U_ARXC_P U_ARXC_N U_A0RXC_P U_A0RXC_N JP5 C9 U_A0RX_PB A RSRD C B5 RX0 Reserved U_A0RX_N A IntL C50 U_ARX_PA5 RX0- IntL B Vact C0 A RX- Vact U_ARX_N B ModPrsl C5 RX ModPrsl U_ARX_PB8 C minisas_ C5 B7 RX- U_ARX_N minisas_ A7 RX C C5 U_ARX_P D Vman C5 A8 RX Vman U_ARX_N D Vact RX- Vact CON_Mini_SAS HD X Recept SW U_DE0 6 U_DE 5 U_PS0 U_PS U_VOD 5 U_A0 6 U_A 7 0 U_A 8 9 SW_X8_Half _Pitch JP PIEQX0-BZHE@TQFN U_PIN MODE D JP7 Banana Jack V EC5 EC 00u_7 00u_7 JP8 Banana Jack SW7 U VIN VOUT TRIM 5 ON/OFF GND Pow_DNTSMD05 R7 R7 NP R7 EC7 u_58 U_PEN EC6 70u_7 _EE R0 R9 0k_00 0k_00 B050LW F D B050LW C6 0.u_00 J p-.5mm Connector SW_PUSH BUTTON.k NP Pericom Semiconductor Corporation Size Document Name Rev B PIEQX0-BZHE minisas Conn Evaluaiton Board A Thursday, February 0, 0 Date: Sheet of Appendix B: PCB Stack-up Page 8 of 9 AN 05/05/0 6//0
9 History Version.0 Original Version 0// Page 9 of 9 AN 05/05/0 6//0
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