PI3EQX6801ZDE PI3EQX6801ZDE Evaluation Board Rev.A User Guide Nov. 11, 2011

Transcription

1 Contents Introduction Board Operation Power options Device configuration System connection Power-on sequence Board Design Information PCB Schematic PCB Layout Reference PCB BOM List PIEQX0ZDE PIEQX0ZDE Evaluation Board Rev.A User Guide Nov., 0 Introduction The PIEQX0ZDE Evaluation Board has been designed to allow convenient testing of the operation and features of Pericom s PIEQX0ZDE SATA ReDriver. This board is designed to work with readily available SATA and esata cables for easy connection to SATA.0 HDD, SSD, OMD storage components and PC system hosts. This board allows the PIEQX0ZDE device to be powered in either +.V, or.v with an on-board regulator provided or directly from external power. This User Guide describes the setup, configuration and operation of PIEQX0ZDE Eval Board Rev.A. Figure provides a top view of PIEQX0ZDE Eval Board Rev.A, and Figure is bottom view of the board. Figure. Top view of PIEQX0ZDE Eval board Rev.A Pericom Semiconductor Corp., N. First Street, San Jose, California, USA Page

2 Figure. Bottom view of PIEQX0ZDE Eval board Rev.A Board Operation PIEQX0ZDE is a -port (-channel), bi-directional, signal SATA.0 re-driver. Figure shows the logical block diagram of PIEQX0ZDE. Both channels of the PIEQX0ZDE are fully independent in operation and configuration, except for the chip Enable function. Either SATA data connector, J or J can be connector to either the host controllers or target disk drive interchangeably. Channel configuration of output pre-emphasis, output swing and input equalization must be set appropriately to match the attached cable/trace length and type. Figure. Logical Block Diagram of PIEQX0ZDE Pericom Semiconductor Corp., N. First Street, San Jose, California, USA Page

3 Power Options The PIEQX0ZDE Evaluation Board provides two options for supplying +.V or +.V power to the ReDriver. Figure circles the important connections. ) Using the +V power supplied by miniusb connector (J). The on-board LDO down-steps the voltage to +.V or +.V. When using this source, note that jumper JP must be shorted (closed). ) Using +.V or +.V power input directly by JP power pin header and JP ground pin header. When using this method, JP must be open. ) For PIEQX0ZDE power supply, the evaluation board is shipped from the factory with +.V default from miniusb port. Jumper JP must be shorted for normal operation. JP0 and JP must be open. Please note ONLY when the power supply is +.V, JP0 and JP must be shorted. J VBUS D- D+ ID GND CON_USB.0_MiniB_SMT +V D LED_G + EC u_ C 0.u_00 U VIN VOUT ADJ/GND CJ-ADJ R NP_00 + EC u_ C 0.u_00 JP R 0ohm_00 R 0_00 JP : +.V or.v for PIEQX0ZDE JP + EC u_ C 0.u_00 C 0.u_00 C 0.u_00 C 0.u_00 Figure. Power supply of PIEQX0ZDE Device Configuration The PIEQX0ZDE SATA ReDriver supports analog emphasis and swing adjustment for continuous tuning via external resistor value for optimum operation and signal margins. For the input equalizer, equalization is controlled via tri-level input pin. The location of configuration switch and jumpers is shown in Figure. Configuration begins with the Enable A_EN# (JP) and B_EN# (JP), which must be open for normal operation. The x_en# pin of the PIEQX0ZDE has an internal 00K pull-down resistor to define a low level default for normal operation. When both of A_EN# and B_EN# are shorted to, device operation is disabled. This is useful for checking PIEQX0ZDE disabled-state power consumption. Pericom Semiconductor Corp., N. First Street, San Jose, California, USA Page

4 ) Output pre-emphasis Configuration Output signal pre-emphasis can be tuned continuously from 0dB to over db as determined by external resistor value. The PIEQX0ZDE Eval Board implements resistors for adjusting output pre-emphasis on each channel as detailed in Table below. If adjustment beyond what is provided is needed, the resistors can be replaced with other values as needed (refer to the PIEQX0ZDE datasheet for additional information on pre-emphasis tuning). Table. Pre-Emphasis Settings on PIEQX0ZDE Eval Board A_EM(channel A) or Effective Output Recommended Use B_EM(channel B) Resistance emphasis Open Do Not 0db Default Factory Setting Connect R R.0k-Ohm About.0dB Short trace of 0 inches, or cable of inches R R 0.0k-Ohm.0dB Trace of inches, or cable of inches R R.k-Ohm About.0dB Trace 0 inches, or cable of 0 inches ) Output Swing Configuration Output signal swing can be tuned continuously by external resistor value. The PIEQX0ZDE Evaluation Board implements resistors for adjusting output swing on each channel as detailed in Table below. If adjustment beyond what is provided is needed, the resistors can be replaced with other values as needed (refer to the PIEQX0ZDE datasheet for additional information on swing tuning). Table. Swing Settings on PIEQX0ZDE Eval Board A_OS(channel A) or Effective Output Swing Recommended Use B_OS(channel B) Resistance at Gbps Open - - No Swing output R R.k-Ohm 0mV Default Factory Setting, SATA port use R R.k-Ohm 0mV For SAS/SATA port use R R0.0k-Ohm 00mV For SAS port use ) Equalizer Configuration A_EQ sets channel-a input equalization, while B_EQ sets channel-b equalization, as shown in Table. The equalization control inputs to the PIEQX0ZDE, A_EQ and B_EQ, each have tri-level control input. Please refer to the table below for equalization selection. Table. EQ Settings on PIEQX0ZDE Eval Board (x means Open, 0 means short) x_en# x_eq Equalization Level of PIEQX0 at.0ghz System Use (A_EQ&B_EQ) 0 x n/a Channel disabled x 0 db Medium trace x Open db Short trace Default Factory Setting x db Long trace Pericom Semiconductor Corp., N. First Street, San Jose, California, USA Page

5 A_OS A_EM A_EQ SW 0 R R R R R R R.k_00.k_00 k_00 k_00 0k_00.k_00 0k_00 JP A_EN# JP SW_X_Half _Pitch JP CON_SATA_SMT AI_P AI_N BO_N BO_N C C0 C C 0n_00 0n_00 0n_00 0n_00 AI_P AI_N BO_N BO_P U JP0 0 HGND A_OS A_EM A_EQ B_EQ B_EM B_OS AI+ AI- A_EN# BO- BO+ AO+ AO- B_EN# BI- BI+ B_EN# AO_PC AO_NC BI_N C BI_P C JP PIEQX0ZDE@TQFN0 0 0n_00 0n_00 0n_00 0n_00 AO_P AO_N BI_N BI_P JP CON_SATA_SMT B_OS B_EM B_EQ SW 0 R R R0 R R R R.k_00.k_00 k_00 k_00 0k_00.k_00 0k_00 SW_X_Half _Pitch Short Open Open Short Figure. Configuration Switch and Jumper and their PCB location Pericom Semiconductor Corp., N. First Street, San Jose, California, USA Page

6 System Connection The diagrams below show some example system test setups with the PIEQX0ZDE Eval Board. Figure shows the connection using a NB PC and esata Express Card. Note that many notebooks PCs already offer an esata port which can be used as the test signal source without the add-in card. PIEQX0 EVB Figure. esata HDD connection Test Setup using NB+eSATA Express Card with PIEQX0ZDE Figure shows the connection using Intel MB PIEQX0 EVB Figure. internal HDD connection Test Setup using Intel MB with PIEQX0ZDE Power-on Sequence It is recommended as good practice, that all system components be powered off while connections and configuration settings are made. There is no specific power-on sequence required when applying power to the PIEQX0ZDE Eval Board. When connected to the system and powered by USB as shown above, then all devices will power-up together. If the host PC and/or HDD are powered on, while the Eval Board is off, there will be no damage to the PIEQX0 under typical conditions. If the Eval Board is then powered on, the system will generally detect the SATA HDD as a hot-plug event, and the HDD will begin to operate properly. Note that some PC systems offer BIOS control over hot plug events, and if the HDD is not recognized, this BIOS setting is the most likely cause and should be changed. When connecting to the system as shown above, all devices will power on together and avoid this BIOS issue. Pericom Semiconductor Corp., N. First Street, San Jose, California, USA Page

7 Board Design Information PCB Schematic JP JP : +.V or.v for PIEQX0ZDE + EC u_ C 0.u_00 C 0.u_00 C 0.u_00 C 0.u_00 A_OS A_EM A_EQ SW 0 R R R R R R R.k_00.k_00 k_00 k_00 0k_00.k_00 0k_00 JP A_EN# JP SW_X_Half _Pitch JP CON_SATA_SMT AI_P AI_N BO_N BO_N C C0 C C 0n_00 0n_00 0n_00 0n_00 AI_P AI_N BO_N BO_P U HGND JP0 0 A_OS A_EM A_EQ B_EQ B_EM B_OS 0 AI+ AI- A_EN# BO- BO+ AO+ AO- B_EN# BI- BI+ B_EN# PIEQX0ZDE@TQFN0 AO_PC AO_NC BI_N C BI_P C JP 0n_00 0n_00 0n_00 0n_00 AO_P AO_N BI_N BI_P JP CON_SATA_SMT B_OS B_EM B_EQ SW 0 R R R0 R R R R.k_00.k_00 k_00 k_00 0k_00.k_00 0k_00 SW_X_Half _Pitch J VBUS D- D+ ID GND CON_USB.0_MiniB_SMT +V D LED_G + EC u_ C 0.u_00 U VIN VOUT ADJ/GND CJ-ADJ R NP_00 + EC u_ C 0.u_00 JP R 0ohm_00 R 0_00 PCB Layout Reference a. Stack Up: b. Isolation Spacing = 0 mil c. Width & Spacing (W/S) of 00Ω Differential Trace = 0 / mil Pericom Semiconductor Corp., N. First Street, San Jose, California, USA Page

8 PCB BOM List Reference Description Package Qty U.V Regulator SOT U PIEQX0ZDE TQFN0- ZD D LED 00 JP,JP SATA L-type connector L-type J miniusb connector B-type JP,JP,JP,JP0,JP PIN HEADER.mm JP,JP PIN HEADER.mm SW,SW x Switch mini C,C0,C,C,C,C, C,C Ceramic Capacitor, 0nF 00 C,C,C,C,C,C Ceramic Capacitor, 0.uF 00 EC,EC,EC Tan cap, u R,R Chip Resistor,.Kohm 00 R,R0 Chip Resistor,.0Kohm 00 R,R Chip Resistor,.0Kohm 00 R,R,R,R Chip Resistor, 0.0Kohm 00 R,R Chip Resistor,.Kohm 00 R,R Chip Resistor,.Kohm 00 R Chip Resistor, 0ohm 00 R Chip Resistor, 0ohm 00 Pericom Semiconductor Corp., N. First Street, San Jose, California, USA Page

9 History Version.0 Original Version Nov., 0 Pericom Semiconductor Corp., N. First Street, San Jose, California, USA Page