THC63LVD823(B)/THC63LVD824A Application Note

Size: px

Start display at page:

Download "THC63LVD823(B)/THC63LVD824A Application Note"

Naomi Ella Palmer
5 years ago
Views:

1 Application Note / Application Note Mode settings, System Diagram and PCB Design Guide Copyright 010 THine Electronics, Inc. 1/13 THine Electronics, Inc.

2 1.Mode Settings Input/Output Single In/ Single Out Single In/ Dual Out Dual In/ Single Out Dual In/ Dual Out Option DDRN O/E Input mode Output mode DDR Output Enable H: Single H: Single H or Hi-Z: DDR o L: Dual L: Dual L: DDR on - Output Disable(Hi-Z) H H * L Output Enable(Fig-1,3-1) H H * H Output Disable(Hi-Z) H L * L Output Enable/DDR o(fig-,3-4) H L H or Hi-Z H Output Enable/DDR on(fig-3,3-4) H L L H Output Disable(Hi-Z) L H * L Output Enable(Fig-4,3-) L H * H Output Disable(Hi-Z) L L * L Output Enable(Fig-5,3-5) L L * H Input/Output Single In/ Dual Out Dual In/ Dual Out Option Output mode L: Dual Input mode H: Single L: Dual Output Enable(Fig-,3-1) L H Output Enable(Fig-7,3-5) L L Copyright 010 THine Electronics, Inc. /13 THine Electronics, Inc.

3 .Signal Flow or Each Setting Single In / Single Out Hysnc IN TA1+/- TB1+/- TC1+/- TD1+/- T1+/- Hi-z Or H or L Fix TA+/- TB+/- TC/- TD+/- T+/- Hi-z Fig-1 Single In / Dual Out DDR o Single In / Dual Out DDR on Rate Hysnc1 IN TA1+/- TB1+/- TC1+/- TD1+/- T1+/- / Rate / / Rate Hysnc IN TA1+/- TB1+/- TC1+/- TD1+/- T1+/- / Rate / Hi-z Or H or L Fix TA+/- TB+/- TC/- TD+/- T+/- / Rate / Hi-z Or H or L Fix TA+/- TB+/- TC+/- TD+/- T+/- / Rate / Fig- =T1+/- Fig-3 =T1+/- Dual In / Single Out Dual In / Dual Out Hysnc IN TA1+/- TB1+/- TC1+/- TD1+/- T1+/- Hysnc IN TA1+/- TB1+/- TC1+/- TD1+/- T1+/- TA+/- TB+/- TC+/- TD+/- T+/- Hi-z TA+/- TB+/- TC+/- TD+/- T+/- Fig-4 Fig-5 =T1+/- Single In / Dual Out Dual In / Dual Out RA1+/- RB1+/- RC1+/- RD1+/- R1+/- Hysnc OUT RA1+/- RB1+/- RC1+/- RD1+/- R1+/- Hysnc OUT Hi-z Or H or L Fix RA+/- RB+/- RC+/- RD+/- R+/- RA+/- RB+/- RC+/- RD+/- R+/- Fig- Synchronous to R1+/- Fig-7 Copyright 010 THine Electronics, Inc. 3/13 THine Electronics, Inc.

4 3.TTL Timing Diagram Following are TTL data input timing example or SXGA+(1400 x 1050). Dot R1x/G1x/B1x #1 #3 #5 # #1397 #1399 Rx/Gx/Bx # #4 # # 139 #139 #1400 #1 # #1399 #1400 TFT Panel (1400 x 1050) Note: 1) MSB LSB R1x G1x B1x Rx Gx Bx R17 R1 R15 R14 R13 R1 R11 R10 G17 G1 G15 G14 G13 G1 G11 G10 B17 B1 B15 B14 B13 B1 B11 B10 R7 R R5 R4 R3 R R1 R0 G7 G G5 G4 G3 G G1 G0 B7 B B5 B4 B3 B B1 B0 ) For single and dual link applications, min. pulse width o // are pixels. Copyright 010 THine Electronics, Inc. 4/13 THine Electronics, Inc.

5 1) Single Link(1) Example : : Falling edge / bit / Single in(ttl)-single out(lvds) : Falling edge / bit / Single in(lvds)-dual out(ttl) / Output driverbility Low L L LVDS LVDS *1 JP IN (5~11MHz) 0.01uF RS OE IN P P TA1+ TB1+ TA1- TB1- TC1- TC1+ twist pair Cable or PCB trace PLL PLL RA1+ RB1+ RA1- RB1- RC1- RC1+ DRVSEL OUT OUT (1.5~5MHz) T1+ T1- TD1- TD1+ R1+ R1- RD1- RD1+ TA- RA- TA+ RA+ * DDRN PRBS N/C TB- TB+ TC- TC+ RB- RB+ RC- RC+ T- R- T+ R+ TD- RD- TD+ *3 RD+ PCB(Transmitter) PCB(Receiver) Fig3-1 *1 : I RS pin tied to, LVDS swing is 350mV. I RS pin tied to, LVDS swing is 00mV. *: Reer to datasheet *3: Connect each PCB Copyright 010 THine Electronics, Inc. 5/13 THine Electronics, Inc.

6 ) Single Link() Example : : Falling edge / bit / Dual in(ttl)-single out(lvds) : Falling edge / bit / Single in(lvds)-dual out(ttl) / Output driverbility Low *1 JP RS OE L P twist pair Cable or PCB trace LVDS PLL DRVSEL 0.01uF L P T1+ T1- TD1- TD1+ LVDS PLL R1+ TA1- RA1- TA1+ RA1+ IN IN OUT OUT (1.5~5MHz) TB1- RB1- (1.5~5MHz) TB1+ RB1+ TC1- RC1- TC1+ RC1+ R1- RD1- RD1+ TA- RA- TA+ RA+ * DDRN PRBS N/C TB- TB+ TC- TC+ T- RB- RB+ RC- RC+ R- T+ R+ TD- RD- TD+ *3 RD+ PCB(Transmitter) PCB(Receiver) Fig3- *1 : I RS pin tied to, LVDS swing is 350mV. I RS pin tied to, LVDS swing is 00mV. *: Reer to datasheet *3: Connect each PCB Copyright 010 THine Electronics, Inc. /13 THine Electronics, Inc.

7 3) Single Link(3) Example : : Falling edge / bit / Dual in(ttl)-single out(lvds) : Falling edge / bit / Single in(lvds)-dual out(ttl) / Output driverbility Low L L LVDS LVDS *1 JP 0.01uF RS OE P P TA1- TA1+ twist pair Cable or PCB trace PLL PLL RA1- RA1+ DRVSEL R7 - R G7 - G B7 - B R7 - R G7 - G B7 - B R11 - R10 G11 - G10 B11 - B10 R1 - R0 G1 - G0 B1 - B0 DDRN PRBS N/C PCB(Transmitter) T1+ TD1+ TA+ TB+ TC+ T+ TD1- TA- TB- TC- T- TD- TD+ * R1+ RD1+ RA+ RB+ RC+ R+ TB1- RB1- IN IN OUT OUT (1.5~5MHz) TB1+ RB1+ (1.5~5MHz) TC1- RC1- R17 - R1 R17 - R1 R17 - R1 G17 - G1 TC1+ RC1+ R17 - R1 G17 - G1 G17 - G1 B17 - B1 G17 - G1 B17 - B1 B17 - B1 T1- R1- B17 - B1 RD1- RA- RB- RC- R- RD- RD+ PCB(Receiver) R7 - R G7 - G B7 - B R11 - R10 G11 - G10 B11 - B10 R1 - R0 G1 - G0 B1 - B0 R7 - R G7 - G B7 - B Fig3-3 *1 : I RS pin tied to, LVDS swing is 350mV. I RS pin tied to, LVDS swing is 00mV. *: Connect each PCB Copyright 010 THine Electronics, Inc. 7/13 THine Electronics, Inc.

8 4) Dual Link(1) Example : : Falling edge/ bit / Single in(ttl)-dual out(lvds) / DDR O or On : Falling edge / bit / Dual in(lvds)-dual out(ttl) / Output driverbility Low Note1: tint = ttcip*n (n=integer) Note: tint >= 4*tTCIP Note3: th >= k*ttcip, tl >= m*ttcip (k,m = integer) (tint = Period, ttcip = IN Period, th = High Time, tl = Low Time ) * *1 JP RS OE L P twist pair Cable or PCB trace LVDS PLL DRVSEL 0.01uF L P TA1- TA1+ T1+ T1- TD1- TD1+ LVDS PLL RA1+ R1+ RA1- IN IN TB1- RB1- OUT OUT TB1+ RB1+ TC1- RC1- TC1+ RC1+ R1- RD1- RD1+ *4 *4 TA- TA+ RA- RA+ TB- TB+ RB- RB+ * DDRN DDRN PRBS N/C TC- TC+ T- T+ RC- RC+ R- R+ TD- TD+ PCB(Transmitter) *3 RD- RD+ PCB(Receiver) Fig3-4 *1 : I RS pin tied to, LVDS swing is 350mV. I RS pin tied to, LVDS swing is 00mV. *: Reer to datasheet *3: Connect each PCB *4 DDR o on IN 50~150MHz 5~75MHz OUT 5~75MHz 1.5~37.5MHz Copyright 010 THine Electronics, Inc. /13 THine Electronics, Inc.

9 5) Dual Link() Example : : Falling edge / bit / Dual in(ttl)-dual out(lvds) : Falling edge / bit / Dual in(lvds)-dual out(ttl) / Output driverbility Low L L LVDS LVDS *1 JP IN (5~5MHz) 0.01uF RS OE IN P P TA1+ TB1+ TA1- TB1- TC1- TC1+ twist pair Cable or PCB trace PLL PLL RA1+ RB1+ RA1- RB1- RC1- RC1+ DRVSEL OUT OUT (5~5MHz) T1+ T1- TD1- TD1+ R1+ R1- RD1- RD1+ TA- TA+ RA- RA+ * DDRN PRBS N/C TB- TB+ TC- TC+ T- T+ RB- RB+ RC- RC+ R- R+ TD- TD+ *3 RD- RD+ PCB(Transmitter) PCB(Receiver) Fig3-5 *1 : I RS pin tied to, LVDS swing is 350mV. I RS pin tied to, LVDS swing is 00mV. *: Reer to datasheet *3: Connect each PCB Copyright 010 THine Electronics, Inc. 9/13 THine Electronics, Inc.

10 4. Note 1)Output Control OE Input(TTL) Output(LVDS) L L Open or Hi-z Hi-z L L Input Hi-z L H Open or Hi-z Hi-z L H Input Hi-z H L Open or Hi-z Hi-z H L Input Hi-z H H Open or Hi-z Hi-z H H Input *1 Data, Out Input(LVDS) Output(TTL) L Open or Hi-z All Low L Input All Low H Open or Hi-z Unstable H Input *1 * Data *, Out *1 With in the range o Recommended Operating Conditions. Reer to Recommended Operating Conditions on data sheet. Without the range, the Output(TTL) may unixed Data, Out. * Open or Hi-z Input Data channel outputs unixed Data(TTL). )Power On Sequence Power on ater. 3)Cable Connection and Disconnection Don t connect and disconnect the LVDS cable, when the power is supplied to the system. 4) Connection Connect the each o the PCB which and on it. It is better or EMI reduction to place cable as close to LVDS cable as possible. 5)Multi Drop Connection Multi drop connection is not recommended. THC3LVD3B T+ T- Copyright 010 THine Electronics, Inc. 10/13 THine Electronics, Inc.

11 )Asynchronous use Asynchronous use such as ollowing systems are not recommended. OUT THC3LVD3B T+ T- LVDS-Rx OUT OUT THC3LVD3B T+ T- LVDS-Rx OUT LVDS-Tx T+ T- OUT OUT LVDS-Tx T+ T- OUT THC3LVD3B T+ T- OUT THC3LVD3B T+ T- T+ T- OUT T+ T- Copyright 010 THine Electronics, Inc. 11/13 THine Electronics, Inc.

12 5. PCB Design Guide Line General Guideline Use 4 layer PCB (minimum). Locate by-pass capacitors adjacent to the device pins as close as possible. Make the loop minimum which is consist o Power line and Gnd line. LVDS Traces Interconnecting media between Transmitter and Receiver (i.e. PCB trace, connector, and cable) should be well balanced.(keep all these dierential impedance and the length o media as same as possible.). Minimize the distance between traces o a pair (S1) to maximize common mode rejection. See ollowing igure. Place adjacent LVDS trace pair at least twice (> x S1) as ar away as much as possible. Avoid 90 degree bends. Minimize the number o VIA on LVDS traces. Match impedance o PCB trace, connector, media (cable) and termination to minimize relections (emissions) or cabled applications (typically 100ohm dierential mode characteristic impedance). Place Terminal Resister adjacent to the Receiver. Copyright 010 THine Electronics, Inc. 1/13 THine Electronics, Inc.

13 Attentions and Requests 1. The product speciications described in this material are subject to change without prior notice.. The circuit diagrams described in this material are examples o the application which may not always apply to the customer's design. We are not responsible or possible errors and omissions in this material. Please note i errors or omissions should be ound in this material, we may not be able to correct them immediately. 3. This material contains our copy right, know-how or other proprietary. Copying or disclosing to third parties the contents o this material without our prior permission is prohibited. 4. Note that i inringement o any third party's industrial ownership should occur by using this product, we will be exempted rom the responsibility unless it directly relates to the production process or unctions o the product. 5. This product is presumed to be used or general electric equipment, not or the applications which require very high reliability (including medical equipment directly concerning people's lie, aerospace equipment, or nuclear control equipment). Also, when using this product or the equipment concerned with the control and saety o the transportation means, the traic signal equipment, or various Types o saety equipment, please do it ater applying appropriate measures to the product.. Despite our utmost eorts to improve the quality and reliability o the product, aults will occur with a certain small probability, which is inevitable to a semi-conductor product. Thereore, you are encouraged to have suiciently redundant or error preventive design applied to the use o the product so as not to have our product cause any social or public damage. 7. Please note that this product is not designed to be radiation-proo.. Customers are asked, i required, to judge by themselves i this product alls under the category o strategic goods under the Foreign Exchange and Foreign Trade Control Law. THine Electronics, Inc. sales@thine.co.jp Copyright 010 THine Electronics, Inc. 13/13 THine Electronics, Inc.

THC63LVD1023B/THC63LVD1024 Application Note

THC63LVD1023B/THC63LVD1024 Application Note Application Note / Application Note Mode setting, System Diagram and PCB Design Guide Date Revision Contents 200/09/0 Rev.1.00_E New created 200//15 Rev.1.01_E Typo 2008/08/06 Rev.1._E Add Some igures