LVDS Product. +3.3V LVDS 18Bit Flat Panel Display (FPD) Receiver - 85MHz. Features PLL. RCLK+/- (20MHz ~ 85MHz)
|
|
|
- Abel Hines
- 6 years ago
- Views:
Transcription
1 LVDS Product DTC33LF86L/ DTC33LR86L (Rev. 2.2) REVISED APR V LVDS 18Bit Flat Panel Display (FPD) Receiver - 85MHz General Description The DTC33LF86L/DTC33LR86L receivers convert the LVDS (Low Voltage Differential Signaling) data streams back into 21 bits of CMOS/TTL data with falling edge (DTC33LF86L) or rising edge (DTC33LR86L) clock for convenient interface with a variety of LCD panel controllers. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. A transmitter (DTC33LM85AL) will inter-operate with a Falling / Rising edge receiver (DTC33LF86L / LR86L) without any translation logic. Using a 85 MHz clock, the data throughputs is 223 Mbytes/sec. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces. Features Wide frequency range : 20 to 85 MHz shift clock support Narrow bus (8 lines) reduces cable size Single 3.3V supply Power-Down Mode Single pixel per clock XGA (1024x768) ready Supports VGA, SVGA, XGA and SXGA Up to 223 Megabytes/sec bandwidth Up to 1.78 Gbps throughput 300mV swing LVDS devices for low EMI PLL requires no external components Low profile 48-lead TSSOP package (PB Free) Compatible with TIA/EIA-644 LVDS standard Compatible with the National DS90C366, Thine THC63LVDF64A Block Diagram DTC33LF86L/DTC33LR86L CMOS/TTL OUTPUTS 6 RED LVDS DATA ( 140 TO 595Mbit/s On Each LVDS Channel ) LVDS - TO - TTL PARALLEL 6 6 GRN BLU HSYNC VSYNC DE(Data Enable) RCLK+/- (20MHz ~ 85MHz) PLL (20MHz ~ 85MHz) /PDN(Power Down) DOESTEK Co., Ltd.
2 Electrical Characteristics Vcc=3.0 ~ Ta=-10 ~ +70 C CMOS/TTL DC SPECIFICATIONS Symbol Parameter Conditions Min Typ Max Units V IH High Level Input Voltage 2.0 Vcc V V IL Low Level Input Voltage 0.8 V V OH High Level Output Voltage I OH = -4mA 2.4 V V OL Low Level Output Voltage I OL = 4mA 0.4 V I IN Input Current 0V V IN Vcc ±10 ua I OS Output Short Circuit Current V OUT = 0V -50 ma LVDS RECEIVER DC SPECIFICATIONS Symbol Parameter Conditions Min Typ Max Units V TH V TL Differential Input High Threshold Differential Input Low Threshold V OC = +1.2V +100 mv -100 mv I IN Input Current V IN = +2.4V/0V, Vcc= 3.6V ±10 ua RECEIVER SUPPLY CURRENT Symbol Parameter Conditions Typ Max Units ICC RG Receiver Supply Current (16 Grayscale) CL = 8pF, f = 85MHz, Vcc = 3.6V 16 Grayscale Pattern 55 ma ICC RW Receiver Supply Current (Worst Case) CL = 8pF, f = 85MHz, Vcc = 3.6V Worst Case Pattern 80 ma ICC RP Receiver Supply Current (Power Down) /PDN=0V 10 ua Absolute Maximum Ratings (Note1) Supply Voltage (Vcc) -0.3 to +4.0V CMOS/TTL Input Voltage -0.3V to (Vcc + 0.3V) CMOS/TTL Output Voltage -0.3V to (Vcc + 0.3V) LVDS Driver Output Voltage -0.3V to (Vcc + 0.3V) Output Short Circuit Duration Continuous Junction Temperature +150 C Storage Temperature Range 65 C to 150 C Lead Temperature (Soldering, 4 sec.) +260 C Maximum Power C 1.4W (Note 1) "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation DOESTEK Co., Ltd.
3 Receiver Switching Characteristics Vcc=3.0 ~ 3.6V Ta=-10 ~ +70 C, T=1/f Symbol Parameter Min Typ Max Units t RCP Period T 50 ns t RCH High Time ns t RCL Low Time ns t RCD RCLK+/- to Delay 7.0 ns t RS TTL Data Setup to 3.5 ns t RH TTL Data Hold from 3.5 ns t TLH TTL Low to High Transition Time 3 ns t THL TTL High to Low Transition Time 3 ns t RDP5 Receiver Input Data Position 0 (85MHz) ns t RDP6 Receiver Input Data Position 1 (85MHz) T/7-0.4 T/7 T/7+0.4 ns t RDP0 Receiver Input Data Position 2 (85MHz) 2T/ T/7 2T/7+0.4 ns t RDP1 Receiver Input Data Position 3 (85MHz) 3T/ T/7 3T/7+0.4 ns t RDP2 Receiver Input Data Position 4 (85MHz) 4T/ T/7 4T/7+0.4 ns t RDP3 Receiver Input Data Position 5 (85MHz) 5T/ T/7 5T/7+0.4 ns t RDP4 Receiver Input Data Position 6 (85MHz) 6T/ T/7 6T/7+0.4 ns t RPLLS Receiver Phase Lock Loop Set 10 ms PIN OUT PACKAGE 48 Lead Molded Thin Shrink Small Outline Package, JEDEC RX17 1 RX RX19 4 RX20 5 N/C 6 LVDS 7 RL0-8 RL0+ 9 RL1-10 RL1+ 11 LVDS 12 LVDS 13 RL2-14 RL2+ 15 RCLK- 16 RCLK+ 17 LVDS 18 PLL 19 PLL 20 PLL 21 /PDN RX0 24 DTC33LF/LR86L RX16 RX15 RX14 RX13 RX12 RX11 RX10 RX9 RX8 RX7 RX6 RX5 RX4 RX3 RX2 RX1 8.1 ± Unit : millimeters ± ± (1.0) 1.2MAX 0.5 TYP TYP 0.10 ± 0.05 TYP DOESTEK Co., Ltd.
4 AC Timing Diagram FIGURE 1. Test Pattern 16 Grayscale Test Pattern Device Pin Name Signal Signal Pattern Signal Frequency RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 RX8 RX9 RX10 RX11 RX12 RX13 RX14 RX15 RX16 RX17 RX18 RX19 RX20 Dot CLK R0 R1 R2 R3 R4 R5 G0 G1 G2 G3 G4 G5 B0 B1 B2 B3 B4 B5 HSYNC VSYNC DE f f/16 f/8 f/4 f/2 f/16 f/8 f/4 f/2 f/16 f/8 f/4 f/2 Steady State High Steady State High Steady State High FIGURE 2. Test Pattern Worst Case Pattern T ODD RX EVEN RX FIGURE 3. TTL Output TTL OUTPUT LOAD TTL OUTPUT 8pF 80% 80% TTL OUTPUT 20% 20% ttlh tthl DOESTEK Co., Ltd.
5 AC Timing Diagram (Continued) FIGURE 4. Phase Lock Loop Set Time /PDN 2V 3.6V 3V trplls RCLK+/- 2V FIGURE 5. Receiver Device Operation trdp4 trdp3 trdp2 trdp1 trdp0 trdp6 trdp5 RX+/- Rx0 Rx1 Rx2 Rx3 Rx4 Rx5 Rx6 Rx0 Rx1 Rx2 Rx3 Rx4 Rx5 Rx6 RCLK+ Vdiff=0V Note : 1) Vdiff = (RL+) - (RL-),... (RCLK+) - (RCLK-) DOESTEK Co., Ltd.
6 FIGURE 6. LVDS Inputs Mapped Parallel TTL Data Outputs DTC33LF86L/DTC33LR86L RCLK (Differential) Previous Cycle Next Cycle RL2 (Single Ended) RX15-1 RX14-1 RX20 RX19 RX18 RX17 RX16 RX15 RX14 RL1 (Single Ended) RX8-1 RX7-1 RX13 RX12 RX11 RX10 RX9 RX8 RX7 RL0 (Single Ended) RX1-1 RX0-1 RX6 RX5 RX4 RX3 RX2 RX1 RX0 FIGURE 7. Setup/Hold and High/Low Times 2.0V 2.0V 0.8V 0.8V trch trcl RX0 ~ RX27 trs trh 2.0V Setup Hold 2.0V 0.8V 0.8V Note : 1) for DTC33LF86L, denoted as solid line(dotted line is for DTC33LR86L), FIGURE 8. RCLK to Delay RCLK +/- Vdiff = 0V trcd 2.0V 2.0V 1.5V trcp Note : 1) Vdiff = (RL+) - (RL-),... (RCLK+) - (RCLK-) DOESTEK Co., Ltd.
7 FIGURE 9. Package Pin Description Pin Name Pin # Type RL0+,RL0-8, 9 LVDS IN RL1+, RL1-10, 11 LVDS IN RL2+, RL2-14, 15 LVDS IN RCLK+, RCLK- 16, 17 LVDS IN RX0 ~ RX6 24,26,27,29,30,31,33 OUT RX7 ~ RX13 34,35,37,39,40,41,43 OUT RX14 ~ RX20 45,46,47,1,2,4,5 OUT 23 OUT LVDS differential data inputs. LVDS differential clock inputs. Description TTL level data outputs. This includes : 6 Red, 6 Green, 6 Blue, and 3 control lines (HSYNC, VSYNC, DE) TTL level clock output. This falling edge acts as data strobe /PDN 22 IN TTL level input. H : Normal operation L : Power down (all output are low) 28,36,42,48 Power 3,25,32,38,44 Ground LVDS 12 Power LVDS 7,13,18 Ground PLL 20 Power PLL 19,21 Ground Power supply pins for TTL outputs. Ground pins for TTL outputs. Power supply pin for LVDS inputs. Ground pins for LVDS inputs. Power supply for PLL. Ground pin for PLL. IMPORTANT NOTICE : - The contents of this data sheet are subject to change without prior notice. DOESTEK Co., Ltd. ( ) 6F TechnoComplex Korea Univ., Anam-Dong5-Ga, Songbuk-Gu, SEOUL, KOREA Tel) DOESTEK Co., Ltd.
LVDS Product. +3.3V LVDS 24Bit Flat Panel Display (FPD) Receiver - 85MHz. Features PLL. RCLK+/- (20MHz ~ 85MHz)
LVDS Product DTC34LF86L/DTC34LR86L (Rev. 2.2) REVISED APR. 2009 +3.3V LVDS 24Bit Flat Panel Display (FPD) Receiver - 85MHz General Description The DTC34LF86L/LR86L receivers convert the LVDS (Low Voltage
LVDS Product. +3.3V LVDS 24Bit Flat Panel Display (FPD) Transmitter - 85MHz DTC34LM85AL TTL PARALLEL -TO- LVDS
LVDS Product DTC34LM85AL ( Rev. 1.0) REVISED APR. 2009 +3.3V LVDS 24Bit Flat Panel Display (FPD) Transmitter - 85MHz General Description The DTC34LM85AL transmitter converts 28 bits of CMOS/TTL data into
LVDS Product. +3.3V LVDS 60Bit Flat Panel Display (FPD) Receiver 135MHz
LVDS Product DTC30LM36 (Rev. 1.1) REVISED AUGUST 2008 +3.3V LVDS 60Bit Flat Panel Display (FPD) Receiver 135MHz General Description Features The DTC30LM36 receiver is designed to support Wide frequency
Features RX0+ RX0- RX1+ RX1- RX2+ RX2- RX3+ RX3- RCK+ RCK- PWRDWN
General Description The V386 is an ideal LVDS receiver that converts 4-pair LVDS data streams into parallel 28 bits of CMOS/TTL data with bandwidth up to 2.38 Gbps throughput or 297.5 Mbytes per second.
DS90CF583/DS90CF584 LVDS 24-Bit Color Flat Panel Display (FPD) Link 65 MHz
DS90CF583/DS90CF584 LVDS 24-Bit Color Flat Panel Display (FPD) Link 65 MHz General Description The DS90CF583 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling)
THC63LVDF84B. 24bit COLOR LVDS RECEIVER (Falling Edge Clock) Features. Figure 1. Block Diagram
THC63LVDF84B 24bit COLOR LVDS RECEIVER (Falling Edge Clock) General Description The THC63LVDF84B receiver supports wide VCC range as 2.5 to 3.6V. At single 2.5V supply, the THC63LVDF84B reduces EMI and
THC63LVDM83R/THC63LVDM63R
THC63LVDM83R/THC63LVDM63R_Rev2.0 THC63LVDM83R/THC63LVDM63R REDUCED SWING LVDS 24Bit/18Bit COLOR HOST-LCD PANEL INTERFACE General Description The THC63LVDM83R transmitter converts 28bits of CMOS/TTL data
To Our Customers.
To Our Customers CEL continues to offer industry leading semiconductor products from Japan. We are pleased to add new communication products from Electronics to our product portfolio. www.cel.com 112MHz
DS90C363/DS90CF V Programmable LVDS 18-Bit-Color Flat Panel Display (FPD) Features. General Description. Block Diagrams.
DS90C363/DS90CF364 +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link 65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link 65 MHz General Description The DS90C363 transmitter
Link-65 MHz, +3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz +3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz General Description The transmitter converts 28 bits of
IDTVP386. General Description. Features. Block Diagram DATASHEET ADVANCE INFORMATION 8/28-BIT LVDS RECEIVER FOR VIDEO
DATASHEET ADVANCE INFORMATION IDTVP386 General Description The VP386 is an ideal LVDS receiver that converts 4-pair LVDS data streams into parallel 28 bits of CMOS/TTL data with bandwidth up to 2.8 Gbps
DS90C385A +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display Link-85 MHz
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display Link-85 MHz General Description The DS90C385A is a pin to pin compatible replacement for DS90C383, DS90C383A and DS90C385. The DS90C385A has
FIN3385 FIN3383 Low Voltage 28-Bit Flat Panel Display Link Serializers
October 2003 Revised January 2004 FIN3385 FIN3383 Low Voltage 28-Bit Flat Panel Display Link Serializers General Description The FIN3385 and FIN3383 transform 28 bit wide parallel LVTTL (Low Voltage TTL)
Features. Typical Application National Semiconductor Corporation DS
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link 65 MHz, +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link 65 MHz General Description The DS90C383 transmitter converts 28
High Speed 10-bits LVDS Transmitter EP103. User Guide V0.6
High Speed 10-bits LVDS Transmitter EP103 User Guide V0.6 Revised: Feb 16, 2007 Original Release Date: Oct 31, 2003, Taiwan reserves the right to make changes without further notice to any products herein
To Our Customers.
To Our Customers Continuing it s rich tradition of partnering with high quality Japanese semiconductor suppliers, CEL is now partnering with THine from May of 2015 onwards. www.cel.com THC63LVDR84C 24bit
Figure 1. Block Diagram
THC63LVD1022 30Bit Color/150Mpps Dual-Link LVDS to LVCMOS converter General Description The THC63LVD1022 LVDS (Low Voltage Differential Signaling) converter is designed to support pixel data transmission
THC63DV161. Termination Control. Recovery/ Decoder/ Deserializer PLL. General Description. Features. Block Diagram THC63DV161
THC63DV161 170MHz 24Bit COLOR DVI Compliant Receiver General Description The THC63DV161 is a receiver compliant with DVI Rev.1.0. The THC63DV161 supports display resolution from VGA to UXGA(25-170MHz),
THC63LVD1024. General Description. Features. Block Diagram. 135MHz 67Bits LVDS Receiver
THC63LVD1024 135MHz 67Bits LVDS Receiver General Description The THC63LVD1024 receiver is designed to support Dual Link transmission between Host and Flat Panel Display up to 1080p/QXGA resolutions. The
UT54LVDS218 Deserializer Data Sheet September, 2015
Standard Products UT54LVDS218 Deserializer Data Sheet September, 2015 The most important thing we build is trust FEATURES 15 to 75MHz shift clock support 50% duty cycle on receiver output clock Low power
4bit LVDS Driver BU90LV047A. LVDS Interface ICs
LVDS Interface ICs 4bit LVDS Driver BU90LV047A Description LVDS Interface IC of ROHM "Serializer" "Deserializer" operate from 8MHz to 150MHz wide clock range, and number of bits range is from 35 to 70.
THC63LVD103D. 160MHz 30bit COLOR LVDS TRANSMITTER. Features
THC63LVD103D 160MHz 30bit COLOR LVDS TRANSMITTER General Description The THC63LVD103D transmitter is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to 1080p(60Hz).
To Our Customers.
To Our Customers CEL continues to offer industry leading semiconductor products from Japan. We are pleased to add new communication products from THine Electronics to our product portfolio. www.cel.com
FIN1102 LVDS 2 Port High Speed Repeater
LVDS 2 Port High Speed Repeater General Description This 2 port repeater is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The FIN1102 accepts and
THC63LVDM83D-Z. 24bit COLOR OPEN LDI(LVDS) TRANSMITTER
THC63LVDM83D-Z 24bit COLOR OPEN LDI(LVDS) TRANSMITTER General Description The THC63LVDM83D-Z transmitter is designed to support pixel data transmission between Host and Flat Panel Display up to 1080p/WUXGAresolutions.
DS90CR281/DS90CR Bit Channel Link
DS90CR281/DS90CR282 28-Bit Channel Link General Description The DS90CR281 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked
THCV213 and THCV214. General Description. Features. Block Diagram. LVDS SerDes transmitter and receiver. THCV _Rev.2.50_E
THCV213214_Rev.2.50_E THCV213 and THCV214 LVDS SerDes transmitter and receiver General Description THCV213 and THCV214 are designed to support pixel data transmission between the Host and Display. The
DS90C387A/DS90CF388A Dual Pixel LVDS Display Interface / FPD-Link
Dual Pixel LVDS Display Interface / FPD-Link General Description Generalized Transmitter Block Diagram February 2006 The DS90C387A/DS90CF388A transmitter/receiver pair is designed to support dual pixel
FIN1101 LVDS Single Port High Speed Repeater
FIN1101 LVDS Single Port High Speed Repeater General Description This single port repeater is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. It accepts
PART. *EP = Exposed pad. LVDS IN+ IN- PCB OR TWISTED PAIR. Maxim Integrated Products 1
19-0849; Rev 1; 12/07 10-Bit LVDS Serializer General Description The serializer transforms 10-bit-wide parallel LVCMOS/LVTTL data into a serial high-speed, low-voltage differential signaling (LVDS) data
Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. DS90CR285/DS90CR286 +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66
TF10CP02 / TF10CP Gbps 2x2 LVDS Crosspoint Switches. Features. Description. Applications. Function Diagram. Ordering Information.
Features DC to 1.5 Gbps low jitter, low skew, low power operation Pin configurable, fully differential, non-blocking architecture eases system design and PCB layout On-chip 100W input termination minimizes
Features. with Reduced Swing Differential Signaling (RSDS ) Outputs. FIGURE 1. Block Diagram of the LCD Module
Low EMI, Low Dynamic Power (SVGA) XGA/WXGA TFT-LCD Timing Controller with Reduced Swing Differential Signaling (RSDS ) Outputs General Description The FPD87346BXA is a timing controller that combines an
PTN3310/PTN3311 High-speed serial logic translators
INTEGRATED CIRCUITS Supersedes data of 2002 Oct 24 2004 Feb 24 FEATURES Meets LVDS EIA-644 and PECL standards 2 pin-for-pin replacement input/output choices: PIN CONFIGURATIONS GND1 1 8 V CC1 LVDS in,
DS90C383/DS90CF V Programmable LVDS Transmitter 24-Bit Flat Panel. Display (FPD) Link-65 MHz, +3.3V LVDS Receiver 24-Bit Flat Panel Display
DS90C383 DS90C383/DS90CF384 +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz Literature Number: SNLS124A
MAX9210/MAX9214/ MAX9220/MAX9222. Programmable DC-Balance 21-Bit Deserializers. Features. General Description. Applications. Ordering Information
General Description The MAX9210/MAX9214/ deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/ LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing
SY89645L. General Description. Features. Block Diagram. Applications. Markets. Precision Low Skew, 1-to-4 LVCMOS/LVTTL-to-LVDS Fanout Buffer
Precision Low Skew, 1-to-4 LVCMOS/LVTTL-to-LVDS Fanout Buffer General Description The is a 3.3V, fully differential, low skew, 1:4 LVDS fanout buffer that accepts LVTTL or LVCMOS inputs. It is capable
THC63LVD823B. 160MHz 51Bits LVDS Transmitter. Features. Data Formatter 1) DEMUX 2) MUX PLL
THC63LVD823B 160MHz 51Bits LVDS Transmitter General Description The THC63LVD823B transmitter is designed to support Single Link transmission between Host and Flat Panel Display and Dual Link transmission
SPECIFICATION APPROVAL SHEET
This product is RoHS compliant SPECIFICATION APPROVAL SHEET Fdt Tech Module No Description: SPEC No.: Version: Issue Date: LT070T8xA0-FDR 7 Digital TFT-LCD Module SAS-1012007 1.1 August 7, 2015 This approval
MC74C Digit BCD Display Controller/Driver. General Description. Ordering Code: Connection Diagram. Features. Version 1.0
6-Digit BCD Display Controller/Driver General Description The display controllers are interface elements, with memory, that drive a 6-digit, 8-segment LED display. The display controllers receive data
PI6CEQ PCIe Gen2 / Gen3 Buffer. Features. Description. Applications. Block Diagram. Pin Configuration (20-Pin TSSOP & 20-Pin QSOP)
PCIe Gen2 / Gen3 Buffer Features ÎÎPCIe Gen2/ Gen3* compliant clock buffer/zdb * Gen3 performance only available in Commercial temp ÎÎInternal equalization for better signal integrity ÎÎ2 HCSL outputs
TF90LVDS047-6CG. Quad LVDS Line Driver with Flow-Through Pinout. Description. Features. Applications. Function Diagram. Ordering Information
Features Companion driver to Quad Extended Common Mode LVDS Receiver TF0LVDS048 DC to 400 Mbps / 200 MHz low noise, low skew, low power operation t 350 ps (max) channel-to-channel skew t 250 ps (max) pulse
PI6C20800S. PCI Express 1:8 HCSL Clock Buffer. Features. Description. Pin Configuration. Block Diagram
Features Phase jitter filter for PCIe application Eight Pairs of Differential Clocks Low skew < 50ps (PI6C20800S),
74F00 Quad 2-Input NAND Gate
Quad 2-Input NAND Gate General Description This device contains four independent gates, each of which performs the logic NAND function. Ordering Code: December 1994 Revised September 2000 Order Number
HM628128BI Series. 131,072-word 8-bit High speed CMOS Static RAM
131,072-word 8-bit High speed CMOS Static RAM ADE-203-363A(Z) Rev. 1.0 Apr. 28, 1995 The Hitachi HM628128BI is a CMOS static RAM organized 131,072-word 8-bit. It realizes higher density, higher performance
2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS ICS Description. Features. Block Diagram DATASHEET
DATASHEET 2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS ICS557-08 Description The ICS557-08 is a 2:1 multiplexer chip that allows the user to select one of the two HCSL (Host Clock Signal Level) or LVDS input pairs
Description OUT0 1 OUTA1 OUTA1 2 OUTA2 3 OUTA3 OUTA4 OUTB1 6 OUTB2 7 OUTB2 OUTB3 OUTB4. All trademarks are property of their respective owners.
Features Maximum rated frequency: 133 MHz Low cycle-to-cycle jitter Input to output delay, less than 200ps Internal feedback allows outputs to be synchronized to the clock input Spread spectrum compatible
CD4023BC Buffered Triple 3-Input NAND Gate
CD4023BC Buffered Triple 3-Input NAND Gate General Description These triple gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P- channel enhancement mode transistors.
Features. Applications
2.5/3.3V 1-to-1 Differential to LVCMOS/LVTTL Translator Precision Edge General Description Micrel s is a 1-to-1, differential-to-lvcmos / LVTTL translator. The differential input is highly flexible and
SPECIFICATION APPROVAL SHEET
This product is RoHS compliant SPECIFICATION APPROVAL SHEET Fdt Tech Module No Description: SPEC No.: Version: Issue Date: LT070T8xA0-FDR 7 Digital TFT-LCD Module SAS-1012007 0.0 March 7, 2011 This approval
LP621024E-I Series 128K X 8 BIT CMOS SRAM. Document Title 128K X 8 BIT CMOS SRAM. Revision History. AMIC Technology, Corp.
128K X 8 BIT CMOS SRAM Document Title 128K X 8 BIT CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue January 14, 2008 Preliminary 1.0 Final version release September 21, 2010
SPECIFICATION APPROVAL SHEET
This product is RoHS compliant SPECIFICATION APPROVAL SHEET Fdt Tech Module No Description: SPEC No.: Version: Issue Date: LT035V20A0-FJR 3.5 Digital TFT-LCD Module SAS-1012006 0.0 January 17, 2011 This
2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS ICS Features
DATASHEET 2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS ICS557-08 Description The ICS557-08 is a 2:1 multiplexer chip that allows the user to select one of the two HCSL (Host Clock Signal Level) input pairs and
Item Symbol Absolute Maximum Rating Unit Remarks
7 TFT LCD asi LCD Color Module The is a compact full color TFT LCD module, that is suitable for portable products, industrial products, hand-held products, security products, instrument displays and office
I.C. PCLK_IN DE_IN GND CNTL_IN1 RGB_IN0 RGB_IN1 RGB_IN2 RGB_IN3 RGB_IN4 RGB_IN5 RGB_IN6 RGB_IN7 CNTL_IN7 CNTL_IN6 CNTL_IN5 CNTL_IN4 CNTL_IN3 CNTL_IN2
19-3558; Rev 4; 8/09 EVALUATION KIT AVAILABLE 27-Bit, 3MHz-to-35MHz General Description The digital video parallel-to-serial converter serializes 27 bits of parallel data into a serial data stream. Eighteen
EVALUATION KIT AVAILABLE High-Bandwidth, VGA 2:1 Switch with ±15kV ESD Protection
19-5; Rev ; 1/9 EVALUATION KIT AVAILABLE High-Bandwidth, VGA :1 Switch General Description The integrates high-bandwidth analog switches, level-translating buffers, and level-translating FET switches to
DS90CF386/DS90CF V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 85 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link
DS90CF366,DS90CF386 +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 85 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link - 85 MHz Literature Number: SNLS055H April 7, 2011 +3.3V
CD4010C Hex Buffers (Non-Inverting)
Hex Buffers (Non-Inverting) General Description The CD4010C hex buffers are monolithic complementary MOS (CMOS) integrated circuits. The N- and P-channel enhancement mode transistors provide a symmetrical
RHFLVDS217. Rad-hard LVDS serializer. Datasheet. Features. Description
Datasheet Rad-hard LVDS serializer Features 15 to 75 MHz shift clock support Fail-safe function 8 kv HBM on LVDS pins Power-down mode < 216 µw (max.) Cold sparing all pins Narrow bus reduces cable size
ICS548A-03 LOW SKEW CLOCK INVERTER AND DIVIDER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS548A-03 Description The ICS548A-03 is a low cost, low skew, high-performance general purpose clock designed to produce a set of one output clock, one inverted output clock, and one clock divided-by-two.
PI6C20800B. PCI Express 3.0 1:8 HCSL Clock Buffer. Features. Description. Pin Configuration (48-Pin TSSOP)
PCI Express 3.0 1:8 HCSL Clock Buffer Features Î ÎPhase jitter filter for PCIe 3.0 application Î ÎEight Pairs of Differential Clocks Î ÎLow skew < 50ps (PI6C20800B),
74VHC132 Quad 2-Input NAND Schmitt Trigger
74VHC132 Quad 2-Input NAND Schmitt Trigger General Description The VHC132 is an advanced high speed CMOS 2-input NAND Schmitt Trigger Gate fabricated with silicon gate CMOS technology. It achieves the
ASM5P2308A. 3.3 V Zero-Delay Buffer
3.3 V Zero-Delay Buffer Description ASM5P2308A is a versatile, 3.3 V zero delay buffer designed to distribute high speed clocks. It is available in a 16 pin package. The part has an on chip PLL which locks
www.smarterglass.com 978 997 4104 sales@smarterglass.com This product is RoHS compliant SPECIFICATION APPROVAL SHEET Fdt Tech Module No Description: SPEC No.: Version: Issue Date: LT035V2xA0-FDR 3.5 Digital
CKSET V CC _VCO FIL SDO+ MAX3952 SCLKO+ SCLKO- PRBSEN LOCK GND TTL
19-2405; Rev 0; 4/02 10Gbps 16:1 Serializer General Description The 16:1 serializer is optimized for 10.3Gbps and 9.95Gbps Ethernet applications. A serial clock output is provided for retiming the data
Display Colors. Outline Dimension. Diplay Mode / Surface
640 x 480 Pixels LCD Color Monitor The is a compact full color TFT LCD module, whose driving board is capable of converting composite video signals to the proper interface of LCD panel and is suitable
SPECIFICATION APPROVAL SHEET
This product is RoHS compliant SPECIFICATION APPROVAL SHEET Fdt Tech Module No Description: SPEC No.: Version: Issue Date: LT056N5xA0-FDR 5.6 Digital TFT-LCD Module SAS-1103003 1.3 June 11, 2014 This approval
PI6C :4 Clock Driver for Intel PCI Express Chipsets. Features. Description. Block Diagram. Pin Configuration
Features Four Pairs of Differential Clocks Low skew < 50ps Low jitter < 50ps Output Enable for all outputs Outputs tristate control via SMBus Power Management Control Programmable PLL Bandwidth PLL or
Description. EPPL (2) Target Temp. range. Notes: (1) SMD = standard microcircuit drawing. (2) EPPL = ESA preferred part list
Rad-hard LVDS serializer Datasheet - production data Features 15 to 75 MHz shift clock support Fail-safe function 8 kv HBM on LVDS pins Power-down mode < 216 µw (max) Cold sparing all pins Narrow bus reduces
THCV220 THCV220. Features
THC220 -by-one HS High-speed video data receiver General Description THC220 is designed to support video data transmission between the host and display. One high-speed lane can carry up to 32bit data and
MC FPGA Bridge IC. for. MIPI D-PHY Systems and SLVS to LVDS Conversion DATASHEET. Version August Meticom GmbH
FPGA Bridge IC for MIPI D-PHY Systems and SLVS to LVDS Conversion DATASHEET Version 1.09 August 2016 Meticom GmbH Meticom GmbH Page 1 of 14 Revision History Version Date of Issue Change 1.01 April 25,
SPECIFICATION APPROVAL SHEET
This product is RoHS compliant SPECIFICATION APPROVAL SHEET Fdt Tech Module No Description: SPEC No.: Version: Issue Date: LT056N5xA0-FDR 5.6 Digital TFT-LCD Module SAS-1103003 0.0 March 4, 2011 This approval
HI-8683, HI ARINC INTERFACE DEVICE ARINC 429 & 561 Serial Data to 8-Bit Parallel Data APPLICATIONS DESCRIPTION. PIN CONFIGURATIONS (Top View)
October 2008 DESCRIPTION HI-8683, HI-8684 ARINC INTERFACE DEVICE ARINC 429 & 561 Serial Data to 8-Bit Parallel Data APPLICATIONS The HI-8683 and HI-8684 are system components for interfacing incoming ARINC
250 Mbps Transceiver in LC FB2M5LVR
250 Mbps Transceiver in LC FB2M5LVR DATA SHEET 650 nm 250 Mbps Fiber Optic Transceiver with LC Termination LVDS I/O IEC 61754-20 Compliant FEATURES LC click lock mechanism for confident connections Compatible
PI6C20400A. 1:4 Clock Driver for Intel PCIe Chipsets. Features. Description. Pin Configuration. Block Diagram
Features Phase jitter filter for PCIe 2.0 application Four Pairs of Differential Clocks Low skew < 50ps Low jitter < 50ps cycle-to-cycle < 1 ps additive RMS phase jitter Output Enable for all outputs Outputs
SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN
9 Channel Bus LVDS Transceiver w/ Boundary SCAN General Description The SCAN92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane
PC POWER SUPPLY SUPERVISOR
` HY510N PC POWER SUPPLY SUPERVISOR Data Sheet REV. 1.30 September 21, 2004 The information in this document is subject to change without notice. 1 11 TEL:886-2-23775117 FAX:886-2-23773189 Email:salesdep@hawyang.com.tw
T1/E1 CLOCK MULTIPLIER. Features
DATASHEET ICS548-05 Description The ICS548-05 is a low-cost, low-jitter, high-performace clock synthesizer designed to produce x16 and x24 clocks from T1 and E1 frequencies. Using IDT s patented analog/digital
3.3V, 3.2Gbps DIFFERENTIAL 4:1 LVDS MULTIPLEXER with INTERNAL INPUT TERMINATION
3.3V, 3.2Gbps DIFFERENTIAL 4:1 LVDS MULTIPLEXER with TERNAL PUT TERMATION FEATURES Selects among four differential inputs Guaranteed AC performance over temp and voltage: DC-to > 3.2Gbps data rate throughput
74LVT244 74LVTH244 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs
Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs General Description The LVT244 and LVTH244 are octal buffers and line drivers designed to be employed as memory address drivers, clock drivers
2 TO 4 DIFFERENTIAL CLOCK MUX ICS Features
DATASHEET 2 TO 4 DIFFERENTIAL CLOCK MUX ICS557-06 Description The ICS557-06 is a two to four differential clock mux designed for use in PCI-Express applications. The device selects one of the two differential
PI6C557-01BQ. PCIe 3.0 Clock Generator with 1 HCSL Outputs. Features. Description. Pin Configuration (16-Pin TQFN) Block Diagram
s Features ÎÎPCIe 3.0 compliant à à Phase jitter - 0.45ps RMS (High Freq. Typ.) ÎÎLVDS compatible output ÎÎSupply voltage of 3.3V ±10% ÎÎ25MHz crystal or clock input frequency ÎÎHCSL outputs, 0.8V Current
ASNT2032-MBL Digital DMUX 12-to-24 with LVDS Interfaces
-MBL Digital DMUX 12-to-24 with LVDS Interfaces Digital demultiplexer (DMUX) 12-to-24 with LVDS output interface Programmable LVDS/CML/ECL input interface Supports data rates from 1.0Mbps to 3.6Gbps Preset
Pin Configuration and Selector Guide appear at end of data sheet. Typical Operating Circuits
Rev 2; 4/08 106.25MHz/212.5MHz/425MHz General Description The DS4106, DS4212, and DS4425 ceramic surfacemount crystal oscillators are part of Maxim s DS4-XO series of crystal oscillators. These devices
1-Megabit (128K x 8) 5-volt Only Flash Memory AT29C010A. Features. Description. Pin Configurations
Features Fast Read Access Time - 70 ns 5-Volt Only Reprogramming Sector Program Operation Single Cycle Reprogram (Erase and Program) 1024 Sectors (128 bytes/sector) Internal Address and Data Latches for
2.5V, 3.2Gbps, DIFFERENTIAL 4:1 LVDS MULTIPLEXER WITH INTERNAL INPUT TERMINATION
2.5V, 3.2Gbps, DIFFERENTIAL 4:1 LVDS MULTIPLEXER WITH TERNAL PUT TERMATION FEATURES Selects among four differential inputs Guaranteed AC performance over temp and voltage: DC-to > 3.2Gbps data rate throughput
DS92LV MHz 10 Bit Bus LVDS Deserializer
DS92LV1224 30-66 MHz 10 Bit Bus LVDS Deserializer General Description The DS92LV1224 is a 300 to 660 Mb/s deserializer for high-speed unidirectional serial data transmission over FR-4 printed circuit board
Low Voltage 1.65 V to 3.6 V, Bidirectional Logic Level Translation, Bypass Switch ADG3233
Data Sheet Low Voltage. V to. V, Bidirectional Logic Level Translation, Bypass Switch ADG FEATURES Operates from. V to. V supply rails Bidirectional level translation, unidirectional signal path -lead
74VCX00 Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and Outputs
74CX00 Low oltage Quad 2-Input NAND Gate with 3.6 Tolerant Inputs and Outputs General Description The CX00 contains four 2-input NAND gates. This product is designed for low voltage (1.65 to 3.6) CC applications
ICE27C Megabit(128KX8) OTP EPROM
1- Megabit(128KX8) OTP EPROM Description The is a low-power, high-performance 1M(1,048,576) bit one-time programmable read only memory (OTP EPROM) organized as 128K by 8 bits. It is single 5V power supply
2.5 V/3.3 V, 1-Bit, 2-Port Level Translator Bus Switch in SOT-66 ADG3241
2. V/3.3 V, -Bit, 2-Port Level Translator Bus Switch in SOT-66 ADG324 FEATURES FUNCTIONAL BLOCK DIAGRAM 22 ps propagation delay through the switch A B 4. Ω switch connection between ports Data rate. Gbps
High- Performance Flash PLD ATF16V8B. Features. Block Diagram. Pin Configurations
Features Industry Standard Architecture Emulates Many 20-Pin PALs Low Cost Easy-to-Use Software Tools High-Speed Electrically Erasable Programmable Logic Devices 7.5 ns Maximum Pin-to-Pin Delay Several
1.8V to 3.3V LVCMOS High Performance Clock Buffer Family
1.8V to 3.3V LVCMOS High Performance Clock Buffer Family 5PB11xx DATASHEET Description The 5PB11xx is a high-performance LVCMOS Clock Buffer Family. It has best-in-class Additive Phase Jitter of 50fsec
Features. Applications
6GHz, 1:4 CML Fanout Buffer/Translator with Internal I/O Termination General Description The is a 2.5V/3.3V precision, high-speed, fully differential 1:4 CML fanout buffer. Optimized to provide four identical
t RP Clock Frequency (max.) MHz
3.3 V 32M x 64/72-Bit, 256MByte SDRAM Modules 168-pin Unbuffered DIMM Modules 168 Pin unbuffered 8 Byte Dual-In-Line SDRAM Modules for PC main memory applications using 256Mbit technology. PC100-222, PC133-333
VGA Port Companion Circuit
GA Port Companion Circuit Features Single chip solution for the GA port interface Includes ESD protection, level shifting, and RGB termination Seven channels of ESD protection for all GA port connector
RW CH Segment Driver
Functions: Dot matrix LCD driver with two 40 channel outputs Bias voltage (V1 ~ V4) Input/output signals Input : Serial display data and control pulse from controller IC Output : 40 X 2 channels waveform
QUICKSWITCH PRODUCTS 2.5V / 3.3V QUAD ACTIVE LOW, HIGH BANDWIDTH BUS SWITCH
QUICKSWITCH PRODUCTS 2.5V / 3.3V QUAD ACTIVE LOW, HIGH BANDWIDTH BUS SWITCH IDTQS3VH125 FEATURES: N channel FET switches with no parasitic diode to VCC Isolation under power-off conditions No DC path to
UNISONIC TECHNOLOGIES CO., LTD
UNINIC TECHNOLOGIES CO., LTD 20-BIT SERIAL TO PARALLEL CONVERTER DESCRIPTION The UTC LS3718 is a 20-bit serial to parallel converter utilizing CMOS Technology. It is incorporates control circuit, shift
Two-wire Serial EEPROM 4K (512 x 8) 8K (1024 x 8) AT24C04B AT24C08B. Features. Description. Low-voltage and Standard-voltage Operation 1.
Features Low-voltage and Standard-voltage Operation.8 (V CC =.8V to.v) Internally Organized x 8 (K), or 0 x 8 (8K) Two-wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional