MachXO2, MachXO3 and ECP5 7:1 LVDS Video Interface

Transcription

1 September 25 Introduction Reference Design RD93 Source synchronous interfaces consisting of multiple data bits and clocks have become a common method for moving image data within electronic systems. A prevalent standard is the : LVDS video interface (employed in Channel Link, Flat Link, and Camera Link), which has become a common standard in many electronic products including consumer devices, industrial control, medical, and automotive telematics. In many of these applications, the practice of using low-cost PLDs for image processing has become quite common. The MachXO2, Mach XO3 PLD and ECP5 device families have been specifically engineered to support Display Interface (: LVDS) video standard with built-in dedicated hardware interface blocks. This document describes the implementation methods and the advantages of using MachXO2, MachXO3 and ECP5 devices for implementing this interface. By extension, support for Display Interface in these devices proves the feasibility of hardware implementation for all other LVDS source synchronous requirements as well. Two designs are included in the discussion of this document. The first design is a simple loopback test that illustrates the use of the Display Interface transmitter and Display Interface receiver. The second design is an example that brings video data into the PLD through the Display Interface receiver, processes it and transmits it out via the Display Interface transmitter. Both designs are verified using the MachXO2 Control Evaluation Board. Display Interface Requirement The Display Interface is a source synchronous LVDS interface. Seven data bits are serialized for each cycle of the low-speed clock as shown in Figure. Typically, the interface consists of four (three data, one clock) or five (four data, one clock) LVDS pairs. The four pairs translate to 2 parallel data bits and five pairs translate to 28 parallel data bits. Note that there is a 2-bit offset between the clock rising edge and the word boundary. Each word is bits long. Figure. Basic Timing of the Display Interface MachXO2, MachXO3 and ECP5 : LVDS Video Interface Clock D (n-) D (n-) D6 D D D6 D (n-) D (n-) D6 D D D6 D (n-) D (n-) D6 D D D6 D (n-) D (n-) D6 D D D6 Previous Cycle Current Cycle Next Cycle Each channel includes a serial LVDS data pair along with a source synchronous LVDS clock pair. The receiver receives this serial LVDS data, deserializes it and aligns it to the original word boundary to generate seven parallel 25 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. RD93_.4

2 : LVDS Video Interface data bits. The : transmitter serializes the seven parallel data bits to a single LVDS data bit and transmits this serial data channel along with a LVDS clock. Figure 2 shows the Display Interface receiver receiving four LVDS data channels. When deserialized, it generates 28-bit wide parallel data. Similarly, the Display Interface transmitter serializes 28-bit parallel data to generate four LVDS data channels. Figure 2. Display Interface Receiver and Transmitter Function 4-Bit LVDS Serial Data 28-bit 28-bit 4 28 Parallel Data Parallel Data Bit LVDS Serial Data LVDS Clk : Display Interface Receiver Pixel Rate Clock () 3.5x Clock () 3.5x Clock () : Display Interface Transmitter LVDS Clk The requirements for an FPGA-based solution to the Channel Link and Flat Link style interfaces consist of four key components: high-speed LVDS buffers, a PLL for generating the de-serialization clock, input data capture and gearing, and data formatting. In previous devices, input data capture, gearing and formatting required user logic design and qualification. MachXO2, MachXO3 and ECP5 devices simplify this task with built-in hardware transmit and receive gearing to compliment the high-speed LVDS buffers and sysclock PLLs to provide a full featured, pre-qualified Display Interface solution. The data and clock are received or transmitted in LVDS format, with the data at relatively high speed. The exact speed depends on the resolution, frame rate and color depth used by the display. For example, 8x6 to 24x68 displays require pixel data to be transmitted from 4 MHz to 8.5 MHz for 6 Hz to 5 Hz refresh rates. This translates to LVDS data rates of 28 Mbps to 549 Mbps. Higher resolution displays, such as the 28x24 6 Hz require pixel data to be transmitted at 8 MHz. For these systems, the LVDS data will transmit at 56 Mbps. Clock Generation In MachXO2, MachXO3 and ECP5 devices, the Display Interface input capture circuitry uses Double Data Rate (DDR) registers with data captured on both the rising and falling edges of the clock. When operating as a receiver, the low-speed clock that is provided with the data must be multiplied 3.5X in order to capture the data on both clock edges. The multiplied clock must have relatively low jitter since its jitter must be accounted for in the overall timing budget. Similarly, the skew of the clock distribution network used to provide this clock to input or output registers must be accounted for in any timing analysis. In order to transmit high-speed data, a transmitter similarly must use or create the 3.5X high-speed DDR edge clock. Again, the jitter of the clock and the skew of its distribution are important as they impact the timing budget for the interface. Figure 3 shows the DDR transmit clock and how the R, G, B bits, Vsync, Hsync, and DE of a pixel on line 2 of a video frame get assigned to the four LVDS data pairs. The data bits are sampled on both rising and falling edges of the DDR transmit clock (). 2

3 : LVDS Video Interface Figure 3. Timings of Video Signals and the Display Interface Vsync Hsync DE R/G/B Line Line 2 Line 3 Line 49 Line 48 Hsync DE Pixel Clock R[:] Pixel() R[:] Pixel(2) R[:] Pixel(3) R[:] Pixel(639) R[:] Pixel(64) R[:] G[:] Pixel() G[:] Pixel(2) G[:] Pixel(3) G[:] Pixel(639) G[:] Pixel(64) G[:] B[:] Pixel() B[:] Pixel(2) B[:] Pixel(3) B[:] Pixel(639) B[:] Pixel(64) B[:] PLL RCLK_in CLKOP (RCLK_in x 3.5) CLKOS (RCLK_in x phase shift) (pll feedback) eclk RCLK_in RD_in R (n-) R (n-) G R5 R4 R3 R2 R R G R5 R4 R3 R2 RC_in G2 (n-) G (n-) B B G5 G4 G3 G2 G B B G5 G4 G3 RB_in B3 (n-) B2 (n-) DE Vsync Hsync B5 B4 B3 B2 DE Vsync Hsync B5 B4 RA_in R (n-) R6 (n-) Rsrv B B6 G G6 R R6 Rsrv B B6 G G6 eclk 3

4 Data Capture and Formatting MachXO2, MachXO3 and ECP5 : LVDS Video Interface The registers that follow the LVDS input buffer must accurately capture the data. A tight control of the clock and data relationship is important to capture the incoming high-speed data stream. It is also necessary to gear, or reduce, the speed of the data before it is passed on to the FPGA fabric. MachXO2 devices specify the operation of individual circuit elements to around 35 MHz. A practical operating frequency with a reasonable amount of logic is 5-2 MHz. Therefore, the greater the gearing that can be done in the I/O structure, the lower the likelihood that the FPGA fabric will be the limit on overall performance. A similar discussion is applicable to the transmit path. The final step is to take the data from the I/O cells and format it into the original -bit width clocked by the low-speed clock. In MachXO2 and ECP5 devices, the task of DDR data capture, gearing and : formatting has been greatly simplified. The architecture includes embedded Display Interface primitives for both receive and transmit data paths. These elements provide an ideal solution for this low-cost, high-confidence video interface solutions. MachXO2 Display Interface The MachXO2 architecture provides an ideal solution for this interface. This section describes implementation of the Display Interface receiver and Display Interface transmitter utilizing the specialized MachXO2 Display I/O structures. Similar architecture has been implemented in the ECP5 designs. Display Interface Receiver Figure 4 shows the block diagram of the receive side of an intra-system display interface within a MachXO2 device. The receiver receives four LVDS data channels and one LVDS clock. Figure 4. Display Interface Receiver DISPLAY I/O XO2_RX.v DISPLAY I/O LOGIC IDDRXA RA_in D RB_in ALIGNWD RC_in RD_in ALIGN_WORD RST SLIP CLK CLKWD EN CLKBUFA Z A EHXPLLJ CLKDIVC ALIGNWD CLKI CDIV RST CDIVX CLKI div by 3.5 RST Q(6:) RA_out RB_out RC_out RD_out DISPLAY I/O ALIGN_BIT RST LOCK EN DIR CLK STEP CLKWD CLKFB CLKOP CLKI CLKOS CLKI x3.5, phase-shifted PHASEDIR PHASESTEP LOCK I O STOP SYNCA DISPLAY I/O LOGIC D IDDRXA ALIGNWD RCLK_in RST STOP RST Q(6:) RCLK_out RST_CTL 4

5 : LVDS Video Interface The data and clock enter the MachXO2 device through Display I/O buffers. These buffers operate at up to 33 MHz (66 Mbps), supporting high resolution and display refresh rates with up to a 85 MHz pixel rate (SXGA). The source synchronous LVDS input clock is fed into a PLL. The PLL is used to multiply the clock by 3.5 and create a phase shift (nominally 9 degrees). This phase shift allows for placing the clock in the middle of the data valid window. This faster phase-shifted clock () is then distributed via a low skew edge clock net to the DDR capture registers. An additional block (SYNCA) is used in conjunction with the RST_CTL block to ensure a controlled startup alignment of all subtended divider circuits driven by. The start-up timing is shown in Figure 5. Figure 5. Synchronization Start-up Timing (SYNCA) STOP RST Minimum 2 cycles The output of the synchronizer block drives a dedicated div-by-3.5 clock divider circuit (CLKDIVC) to produce a pixel-rate clock () phase aligned with. The pixel clock is used to clock parallel pixel data at a lower FPGA clock rate into the FPGA fabric. The LVDS data is fed to the Display I/O Logic Cell s double data-rate (DDR) registers with : gearing function (IDDRXA). The gearing allows demuxing of the I/O data clocked with the high-speed edge clock () to the slower-speed FPGA clock rate (). As shown in Figure 6, the output data is driven by the rising edge of. The first serial bit received becomes bit of the output word. 5

6 : LVDS Video Interface Figure 6. Receive : Gearing in Display I/O Logic Cell (IDDRXA) D Q6 54 Q5 43 Q4 32 Q3 2 Q2 Q - Q SEL UPDATE The output word is delineated using two control signals, SEL and UPDATE. These signals are generated internally to the I/O logic cell by dividing down. The timing of these signals is shown in Figure. 6

7 : LVDS Video Interface Figure. Deserializer Timing D UPDATE SEL Q(6:) " " The Display Interface includes logic for auto-aligning the PLL output clock to the optimum sample position for sampling the input LVDS data stream (bit_align.v), plus logic for auto-aligning the FPGA clock to the input data word (word_align.v). These soft logic pieces work in concert with the hard primitive resources to provide the full Display Interface solution. After a global reset event, or the establishment of the input Clock link, the Bit Alignment module (bit_align.v) is activated to find the best sample point for the incoming data. The module slews the PLL clock output across 8 of phase in 8 steps, or 22.5 increments. (8 is sufficient because of the Dual Data Rate nature of the input data.) During this initialization, the circuit tests each phase for coherent data. After determining the extent of the good data, the module selects the phase in the middle of the good data window and indicates initialization complete by asserting DPHASE_LOCK. This process is illustrated in Figure 8. Figure 8. Bit-alignment Search Selected phase 8 phase search Failed phases Data_in The Word Alignment module (word_align.v) simply compares RCLK_out against the expected output pattern of. If the expected alignment is not found, the module issues asserts ALIGNWD to CLKDIVC and IDDRXA to accomplish a shift in UPDATE, SEL, and, ultimately, the received data. Each rising edge of ALIGNWD causes a 2-bit shift, or slip, relative to the input stream. (ALIGNWD may be asynchronous to the domain. Both high and low pulses must remain for a minimum of 4 cycles.) This action is repeated until the correct data word alignment is found. Figure 9 shows the effect of a slip action.

8 : LVDS Video Interface Figure 9. Slip Action in Response to ALIGNWD Rising Edge Slip Action D UPDATE SEL Q(6:) " " Display Interface Transmitter Figure shows the block diagram of the transmit side of an intra-system display interface within a MachXO2 device. The module receives four channels of -bit parallel data and the fast DDR clock (). The transmitter transmits four LVDS data channels and one LVDS clock. Figure. Display Interface Transmitter XO2_TX.v DISPLAY I/O LOGIC ODDRXA dataout dataout dataout2 dataout3 D(6:) RST Q dout dout dout2 DISPLAY I/O TA_out TA_out TA_out CLKDIVC dout3 TA_out ALIGNWD CLKI CDIV eclk I O STOP RST CDIVX CLKI div by 3.5 sclk SYNCA DISPLAY I/O LOGIC ODDRXA D(6:) RST STOP RST_CTL RST Q clkout DISPLAY I/O TCLK_out 8

9 : LVDS Video Interface All 28 bits of parallel data are registered at the transmitter inputs on the rising edge of the locally generated system clock (). Care must be taken as the parallel data is sourced from a separate clock domain. For example, data from the Display I/O receiver module, generated by a separate and distinct domain, must be phase aligned with the generated locally by CLKDIVC within the transmit module. This is possible by releasing the STOP port of each SYNCA (rcv and xmt) in unison. Timing analysis can then calculate the correct set-up times based upon data path delay and clock skews from the common. The parallel data is fed to the Display I/O Logic Cell with : gearing function (ODDRXA). The gearing allows the multiplexing of the input data clocked in with the low-speed system clock () to the higher-speed DDR output edge clock rate (). As shown in Figure, the output data is driven by both edges of. Bit of the input data word becomes the first bit of the serial output. 9

10 : LVDS Video Interface Figure. : Gearing in Tx Display I/O Logic Cell (ODDRXA) 6_ D D D Q _ SEL UPDATE The output word is serialized using two control signals, SEL and UPDATE. These signals are generated internally to the I/O Logic Cell by dividing down. The timing of these signals is illustrated in Figure 2. SEL and UPDATE are synchronized with (generated by CLKDIVC) by the use of SYNCA.

11 : LVDS Video Interface Figure 2. Serializer Timing D(6:) " " UPDATE SEL Q Design Example : Loopback Test The loopback test design included with this document uses a MachXO2, MachXO3 or ECP5 device to implement both the : Display Interface transmitter and receiver. Figure 3 shows the design implementation. For more detailed information about the : Display Interface transmitter and receiver, refer to Figures 4 and. Figure 3. Loopback Test Block Diagram CLK_Tx Transmit Data Generator 28 Div3.5 eclk sclk : Display Interface Transmitter TCLK_out TDATA_out 4 LEDs DIPSW 4 4 Data Compare/ Error Logic 28 : Display Interface Receiver RDATA_in 4 RCLK_in 28-bit transmit data is generated in the device logic using counter values. This data is then serialized and transmitted as four bits of LVDS data using the : Display Interface Transmitter. The 4-bit LVDS data is then looped back externally into the MachXO2 device receiver side and deserialized using the : Display Interface Receiver. This deserialized data is then fed to the data compare logic module which compares the deserialized receiver data to the original counter values transmitted. Errors are detected and latched for visual display through an LED port. The information displayed by the LEDs is selected by a DIPSW array input port. In addition, the DIPSW may be used to override the automated phase detection (see Bit Alignment search, above). The relationship between the DIPSW setting and the LED display is given in Table.

12 : LVDS Video Interface Table. LED Display Options DIPSW(3:) LE LE LED LED Bit-alignment module phase determination (-) Ch. A error detect Ch. B error detect Ch. C error detect Ch. D error detect Rx PLL lock Bit-align lock Rx data lock Free-running blink Ch. A Tx data(6:5) Ch. A Rx data(6:5) Ch. B Tx data(6:5) Ch. B Rx data(6:5) Ch. C Tx data(6:5) Ch. C Rx data(6:5) Ch. D Tx data(6:5) Ch. D Rx data(6:5) xxx Ch. A error detect Ch. B error detect Ch. C error detect Ch. D error detect Table 2. Input Sample Clock () Phase Adjustment DIPSW(3) Action Automatic input clock sample phase adjustment Manual input clock sample phase adjustment: DIPSW(2:) Phase Adjustment from Nominal

13 : LVDS Video Interface Implementation Table 3. Performance and Resource Utilization ECP5 3 Device Family Language Speed Grade Utilization (LUTs) fmax (MHz) I/Os MachXO3L 2 MachXO2 Design Example 2: PassThru Test Verilog-LSE Verilog-Syn VHDL-LSE VHDL-Syn Verilog-Syn Verilog-LSE VHDL-Syn VHDL-LSE Verilog-LSE Verilog-Syn VHDL-LSE 6 3 VHDL-Syn 6 3. Performance and utilization characteristics are generated using LCMXO2-2HC-6MG32C with Lattice Diamond 3.4 design software. When using this design in a different device, density, speed, or grade, performance and utilization may vary. 2. Performance and utilization characteristics are generated using LCMXO3L-43C-6BG256C with Lattice Diamond 3.4 design software. When using this design in a different device, density, speed, or grade, performance and utilization may vary. 3. Performance and utilization characteristics are generated using LFE5UM-85F-8BG65S with Lattice Diamond 3.4 design software. When using this design in a different device, density, speed, or grade, performance and utilization may vary. In order to verify the operation of Display Interfaces within the MachXO2 device, Lattice has developed the MachXO2 Control Evaluation Board. This system takes video data supplied in DVI format from a source such as a PC or a DVD player and converts it to the : LVDS source synchronous format using a Texas Instruments DVI Decoder and a National Semiconductor Channel Link Transmitter Device. This image data is fed to the MachXO2 where the Display Interface Receiver is used to deserialize the data. This data is then converted back into serial data using the Display Interface Transmitter within the MachXO2 device. It is then transmitted using a source synchronous : LVDS interface to a National Semiconductor Channel Link Receiver device and Texas Instruments DVI Encoder, then ultimately to a display. A simplified block diagram of the platform is shown in Figure 4. 3

14 : LVDS Video Interface Figure 4. MachXO2 Control Board Simplified Block Diagram Rx LVDS: MDR Connector J Rx DVI Connector J2 Texas Instruments TFP4A U2 National Semiconductor DS9CR28 U3 LED 2 3 Texas Instruments TFP4 U3 National Semiconductor DS9CR288A U2 Tx DVI Connector J3 MachXO2 2 LCMXO2-2HC- 6MG32C U4 SW 3 Tx LVDS: MDR Connector J8 Figure 5 shows a block diagram of the MachXO2 PassThru design. Other than the receiver and transmitter modules, the center logic block can be any customized video processing design. For demonstration purposes, the design shown in Figure 5 was created to include the following features: Independent control over red, green and blue channels Individual channel pass, suppress, invert, and rotate Simple color bars insertion 4

15 : LVDS Video Interface Figure 5. PassThru Test Block Diagram RA_in RB_in RC_in RD_in RCLK_in : Display Interface Receiver LED(3:) eclk sclk rx_d rx_c rx_b rx_a Rx Signal Mapping r_vsync r_r r_g r_b r_hsync r_de DIPSW(3:) RGB Transform Color Bar Generator t_vsync t_r t_g t_b t_hsync t_de Tx Signal Mapping TA_out TB_out TC_out TD_out TCLK_out tx_d tx_c tx_b tx_a : Display Interface Transmitter The PassThru design example includes four sub-modules: Receiver, RGB Transform, Color Bars Generator, and Transmitter. On the MachXO2 Control Evaluation Board, the 4-position DIP-switch SW is used for manipulating the RGB channels. The functions of SW are listed in Table 4. 5

16 : LVDS Video Interface Table 4. RGB Transform Control DIPSW(3:) SW Red Channel Output Green Channel Output Blue Channel Output Inverted Red Inverted Green Inverted Blue Blue Red Green Green Blue Red PassThru Insert Colorbars PassThru PassThru PassThru Suppressed Suppressed Suppressed Suppressed Suppressed Blue Suppressed Green Suppressed Suppressed Green Blue Red Suppressed Suppressed Red Suppressed Blue Red Green Suppressed PassThru. and translate to off and on, respectively, in the physical switch. When selected, the Color Bar Generation module overwrites the active video frame with a color bar pattern. The blanking data is passed unchanged. The active video line is divided into eight columns. The color sequence is: White, Yellow, Cyan, Green, Magenta, Red, Blue, Black. Table 5 describes the LED diplay function. Table 5. LED Display LE LE LED LED On: Rx Bit-align locked Bit-alignment module phase determination (-) 6

17 : LVDS Video Interface Implementation Table 6. Performance and Resource Utilization Device Family Language Speed Grade Utilization f MAX (MHz) I/Os ECP5 3 MachXO3L 2 Verilog-LSE Verilog-Syn VHDL-LSE VHDL-Syn Verilog-Syn Verilog-LSE VHDL-Syn VHDL-LSE Verilog-LSE Verilog-Syn MachXO2 VHDL-LSE VHDL-Syn Performance and utilization characteristics are generated using LCMXO2-2HC-6MG32C with Lattice Diamond 3.4 design software. When using this design in a different device, density, speed, or grade, performance and utilization may vary. 2. Performance and utilization characteristics are generated using LCMXO3L-43C-6BG256C with Lattice Diamond 3.4 design software. When using this design in a different device, density, speed, or grade, performance and utilization may vary. 3. Performance and utilization characteristics are generated using LFE5UM-85F-8BG65S with Lattice Diamond 3.4 design software. When using this design in a different device, density, speed, or grade, performance and utilization may vary.

18 : LVDS Video Interface Technical Support Assistance Submit a technical support case through Revision History Date Version Change Summary September 25.4 Changed document title to MachXO2, MachXO3 and ECP5 : LVDS Video Interface. Updated Technical Support Assistance section. January 25.3 Updated Table 6, Performance and Resource Utilization. Updated to support Lattice Diamond 3.4 Added LSE support for all the device families. March 24.2 Updated Sapphire device to ECP5 device. Updated Table 6, Performance and Resource Utilization. Added support for MachXO3L device family. Updated to support ECP5 device family. September 23. Changed document title to Display Interface Added support for Sapphire device family. Updated corporate logo. Updated Technical Support Assistance information. Changed RD_in data from G to G in the Timings of Video Signals and the Display Interface figure. November 2. Initial release. 8