A (Very Hand-Wavy) Introduction to. PCI-Express. Jonathan Heathcote
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1 A (Very Hand-Wavy) Introduction to PCI-Express Jonathan Heathcote
2 Motivation Six Week Project Before PhD Starts: SpiNNaker Ethernet I/O is Sloooooow How Do You Get Things In/Out of SpiNNaker, Fast? Build a High-Speed Interface Via Onboard FPGAs 2/37
3 Motivation Six Week Project Before PhD Starts: SpiNNaker Ethernet I/O is Sloooooow How Do You Get Things In/Out of SpiNNaker, Fast? Build a High-Speed Interface Via Onboard FPGAs Obviously Too Big For Six Weeks Mainly Been Looking at Guts of PCI-Express 2/37
4 Outline PCI & PCI-Express Background The Software Perspective Bottom-up Through the Protocol Layers Physical Layer Data-Link Layer Transaction Layer SpiNNaker & PCI-Express on FPGA 3/37
5 Peripheral Component Interconnect (PCI) Intel, 1993 (I was 2 years old) Widely Used, Even Today Extension of Processor Bus Memory Mapped Peripherals Parallel Signalling (32/64 bit) Multi-drop Bus Originally MHz Later MHz/64 bit 4/37
6 (PCIe) Intel, Dell, HP, IBM 2004 (I m still only 13) Backward Compatible API Point-to-Point, Packet-Based One or More High-Speed Serial Lanes (more later) Revision 1.0: GHz 64 Gb/s, 15 PCI Speed ( GHz) Revision 3.0: GHz State-of-the-art: Gb/s (32 8 GHz) 5/37
7 PCIe Hierarchy CPU Memory Root Complex PCIe Graphics Switch Switch PCIe Endpoint PCIe Endpoint PCIe Endpoint PCI Bridge PCI Bus 6/37
8 PCIe Software Interface Memory PCIe Config Space PCIe Configuration Space Device Information Base Address Registers (BARs) Control Address Decoding BARs Configured By OS...FFFF 7/37
9 PCIe Software Interface Memory PCIe Config Space Device 1 Device 2 PCIe Configuration Space Device Information Base Address Registers (BARs) Control Address Decoding BARs Configured By OS Device Spaces Device Specific Contents Driver Given Pointer...FFFF 7/37
10 PCIe Protocol Layers Transaction Transaction Data-Link Physical Logical Electrical tx rx Data-Link Physical Logical Electrical tx rx 8/37
11 PCIe Protocol Layers Transaction Transaction Data-Link Physical Logical Electrical tx rx Data-Link Physical Logical Electrical tx rx 8/37
12 Mechanical Interface x1 x4 x8 x16 Power Data 9/37
13 PCIe Protocol Layers (Again) Transaction Transaction Data-Link Physical Logical Electrical tx rx Data-Link Physical Logical Electrical tx rx 10/37
14 Electrical Interface e.g. Device A Root Complex e.g. Device B Graphics Card Transmit & Receive Differential Pairs (Per Lane) Peer-to-Peer Arrangement AC Coupled via capacitor in transmitter 11/37
15 PCIe Protocol Layers (Yet Again) Transaction Transaction Data-Link Physical Logical Electrical tx rx Data-Link Physical Logical Electrical tx rx 12/37
16 Clock Recovery Data Unlucky Data H e l @ No Clock Signal Must Extract Clock From Data Requires Frequent Transitions 13/37
17 8b/10b Coding (PCIe 2.1) Raw D.00.2 D.00.2 D.00.2 D.00.2 Encodes 8-bit bytes into 10-bit symbols Transitions at least every 5 bits (for clock recovery) Bonus: Maintains DC Balance (due to AC coupling) Bonus: 8 Special K Symbols (out-of-band) 14/37
18 8b/10b Coding (PCIe 2.1) Raw D.00.2 D.00.2 D.00.2 D.00.2 Encodes 8-bit bytes into 10-bit symbols Transitions at least every 5 bits (for clock recovery) Bonus: Maintains DC Balance (due to AC coupling) Bonus: 8 Special K Symbols (out-of-band) Cereal Signalling... 14/37
19 A Quick Aside b/130b encoding introduced in PCIe v3.0 Different mechanism (scrambling, not lookup table) Reduces overhead from 20% to 1.54% Not covered in this presentation 15/37
20 Aligning 8b/10b Symbols xf20xf6P??d0xfd0xf9P0xbf?0xf5?0xa2P0xf60xfd0xdc?0 xfd0xf9p0xbf?0xf5?0xa2p0x xf20xf6p??d0xfd0xf9p0xbf? 0xf5?0xa2P0xf60xfd0xdc?0x... Where does one code end and another begin? 16/37
21 Aligning 8b/10b Symbols xf20xf6P??d>0xfd0xf9P0xb f?0xf5?0xa2p0xf60xfd0xdc? d0xfd0xf9p0xbf?0xf5?0xa2p Ux0xf20xf6P??d0xfd0xf9P0x bf?0xf5?0xa2>p0xf60xfd0xd... Where does one code end and another begin? Comma K Symbol inserted periodically 16/37
22 Aligning 8b/10b Symbols xf20xf6P??orld! Hello World! Hello World! Hello World! Hello World! Hello World! Hello World!... Where does one code end and another begin? Comma K Symbol inserted periodically When a comma is found, align bits 16/37
23 Clock Rate Disparity Tolerance Reference Clock 600 PPM Off-by-one every 1666 bits At 8 GHz, 0.5MB extra sent/received per second Solved by inserting extra SKP Ordered Sets (A Sequence of K Symbols) 17/37
24 SKP Example: Sender Faster Fills faster than empties Eventually falls above high mark SKP Sequence skipped to empty buffer faster Incoming Handled High Low Data SKP 18/37
25 SKP Example: Sender Faster Fills faster than empties Eventually falls above high mark SKP Sequence skipped to empty buffer faster Incoming Handled High Low Data SKP 18/37
26 SKP Example: Sender Faster Fills faster than empties Eventually falls above high mark SKP Sequence skipped to empty buffer faster Incoming Handled High Low Data SKP 18/37
27 SKP Example: Sender Faster Fills faster than empties Eventually falls above high mark SKP Sequence skipped to empty buffer faster Incoming Handled High Low Data SKP 18/37
28 SKP Example: Sender Faster Fills faster than empties Eventually falls above high mark SKP Sequence skipped to empty buffer faster Incoming Handled High Low Data SKP 18/37
29 PCIe Lanes Resync Sender Receiver Allows Some Speed Up by Adding Hardware N Serial Signals N Consecutive Bytes Sent in Parallel Resynchronised at Receiver (More Later) 19/37
30 PCIe Lanes Resync Sender Receiver Allows Some Speed Up by Adding Hardware N Serial Signals N Consecutive Bytes Sent in Parallel Resynchronised at Receiver (More Later) 19/37
31 PCIe Lanes Resync Sender Receiver Allows Some Speed Up by Adding Hardware N Serial Signals N Consecutive Bytes Sent in Parallel Resynchronised at Receiver (More Later) 19/37
32 PCIe Lanes Resync Sender Receiver Allows Some Speed Up by Adding Hardware N Serial Signals N Consecutive Bytes Sent in Parallel Resynchronised at Receiver (More Later) 19/37
33 Lane-to-Lane De-skew Data SKP Sender Receiver Lanes have varying skew Buffer each lane separately SKP sequences sent simultaneously on all lanes De-skew on such packets 20/37
34 Lane-to-Lane De-skew Data SKP Sender Receiver Lanes have varying skew Buffer each lane separately SKP sequences sent simultaneously on all lanes De-skew on such packets 20/37
35 Lane-to-Lane De-skew Data SKP Sender Receiver Lanes have varying skew Buffer each lane separately SKP sequences sent simultaneously on all lanes De-skew on such packets 20/37
36 Lane-to-Lane De-skew Data SKP Sender Receiver Lanes have varying skew Buffer each lane separately SKP sequences sent simultaneously on all lanes De-skew on such packets 20/37
37 Lane-to-Lane De-skew Data SKP Sender Receiver Lanes have varying skew Buffer each lane separately SKP sequences sent simultaneously on all lanes De-skew on such packets 20/37
38 Lane-to-Lane De-skew Data SKP Sender Receiver Lanes have varying skew Buffer each lane separately SKP sequences sent simultaneously on all lanes De-skew on such packets 20/37
39 Lane-to-Lane De-skew Data SKP Sender Receiver Lanes have varying skew Buffer each lane separately SKP sequences sent simultaneously on all lanes De-skew on such packets 20/37
40 Lane-to-Lane De-skew Data SKP Sender Receiver Lanes have varying skew Buffer each lane separately SKP sequences sent simultaneously on all lanes De-skew on such packets 20/37
41 Lane-to-Lane De-skew Data SKP Sender Receiver Lanes have varying skew Buffer each lane separately SKP sequences sent simultaneously on all lanes De-skew on such packets 20/37
42 Lane-to-Lane De-skew Data SKP Sender Receiver Lanes have varying skew Buffer each lane separately SKP sequences sent simultaneously on all lanes De-skew on such packets 20/37
43 Lane-to-Lane De-skew Data SKP Sender Receiver Lanes have varying skew Buffer each lane separately SKP sequences sent simultaneously on all lanes De-skew on such packets 20/37
44 Lane-to-Lane De-skew Data SKP Sender Receiver Lanes have varying skew Buffer each lane separately SKP sequences sent simultaneously on all lanes De-skew on such packets 20/37
45 Lane-to-Lane De-skew Data SKP Sender Receiver Lanes have varying skew Buffer each lane separately SKP sequences sent simultaneously on all lanes De-skew on such packets 20/37
46 Packet Framing STP (K27.7) Transaction Layer Packet TLP END (K29.7) SDP (K28.2) Data-Link Layer Packet DLLP END (K29.7) K Symbol Marks Start/End of Higher-Level Packets Distinguishes Target Protocol Layer 21/37
47 PCIe Protocol Layers (Yet Again, Again) Transaction Transaction Data-Link Physical Logical Electrical tx rx Data-Link Physical Logical Electrical tx rx 22/37
48 Data-Link Layer Reliable Delivery of Transaction Layer Packets (TLPs) Uses: Memory Transactions, Interrupt Signalling Error Detection Retransmission Out-of-band Data-Link Layer Packets (DLLPs) Uses: ACK/NACK, Power Management Error Detection No Retransmission Uses Must Tolerate Non-Delivery 23/37
49 Transaction Layer Packet (TLP) Framing Rsvd Sequence Number Transaction Layer Packet CRC Variable Length Seq. number allows many TLPs to be ACKed at once CRC for error detection: send NACK 24/37
50 Data-Link Layer Packets (DLLPs) DLLP Type [Type Specific Data] CRC Fixed (Short) Length Smaller CRC (As Less Data) 25/37
51 PCIe Protocol Layers (Yet Again, Again, One Last Time) Transaction Transaction Data-Link Physical Logical Electrical tx rx Data-Link Physical Logical Electrical tx rx 26/37
52 PCIe Transaction Layer Usually Exposed by FPGAs Transaction Types Memory Read/Write I/O Read/Write (Deprecated) Configuration Read/Write Message ( Interrupts ) Split Transactions (Requests & Completions) No Completion for Posted Requests (e.g. writes) 27/37
53 Transaction Layer Packets Type Type Specific Type Specific Type Specific 28/37
54 Transaction Layer Packets Type Type Specific Type Specific Type Specific Has Payload (i.e. Is Write) 28/37
55 Transaction Layer Packets Type Type Specific Type Specific Type Specific Payload Has Payload (i.e. Is Write) 28/37
56 Transaction Layer Packets Type Type Specific Type Specific Type Specific Header Length (3 or 4 words) Usually Specifies Either 32 or 64 bit Address 28/37
57 Transaction Layer Packets Type Type Specific Type Specific Type Specific Type Specific Header Length (3 or 4 words) Usually Specifies Either 32 or 64 bit Address 28/37
58 Transaction Layer Packets Type Type Specific Type Specific Type Specific Memory, I/O, Configuration, Message, Completion 28/37
59 Memory & I/O Request Packets Type 0 TC 0 Requester ID Attr H T D T P E Attr AT Length Tag Last DW BE First DW BE Address[31:2] 00 Data 29/37
60 Memory & I/O Request Packets Type 0 TC 0 Requester ID Attr H T D T P E Attr AT Length Tag Last DW BE First DW BE Address[31:2] 00 Data Word-Aligned Address Determines Target 29/37
61 Memory & I/O Request Packets Type 0 TC 0 Requester ID Attr H T D T P E Attr AT Length Tag Last DW BE First DW BE Address[31:2] 00 Data Length of Data Words 29/37
62 Memory & I/O Request Packets Type 0 TC 0 Requester ID Attr H T D T P E Attr AT Length Tag Last DW BE First DW BE Address[31:2] 00 Data Determines Completion Target Derived From Physical Slot 29/37
63 Memory & I/O Request Packets Type 0 TC 0 Requester ID Attr H T D T P E Attr AT Length Tag Last DW BE First DW BE Address[31:2] 00 Data Identifies Outstanding Transactions 29/37
64 Memory & I/O Completion Packets Type 0 TC 0000 D T P E Attr00 Length Completer ID Compl. Status +2 BCM +3 Byte Count Requester ID Tag 0 Lower Address Data 30/37
65 Memory & I/O Completion Packets Type 0 TC 0000 D T P E Attr00 Length Completer ID Compl. Status +2 BCM +3 Byte Count Requester ID Tag 0 Lower Address Data Length of Data Words 30/37
66 Memory & I/O Completion Packets Type 0 TC 0000 D T P E Attr00 Length Completer ID Compl. Status +2 BCM +3 Byte Count Requester ID Tag 0 Lower Address Data Determines Completion Target Derived From Physical Slot 30/37
67 Memory & I/O Completion Packets Type 0 TC 0000 D T P E Attr00 Length Completer ID Compl. Status +2 BCM +3 Byte Count Requester ID Tag 0 Lower Address Data Identifies Outstanding Transactions 30/37
68 Packet Routing Methods Address Based Based on BARs Used By Memory & I/O Requests ID Based Based on Physical Location Used By Configuration Requests Used By All Completions Implicit e.g. Send to Root Complex Message Requests 31/37
69 Credit-Based Flow Control Receive Buffer Credit Credit Due: 0 Sender Receiver Sender Has A Limited Supply Of Credit Sending Data Uses Credit Receiver Returns Credit When Buffer Space Is Freed 32/37
70 Credit-Based Flow Control Receive Buffer Credit Credit Due: 0 Sender Receiver Sender Has A Limited Supply Of Credit Sending Data Uses Credit Receiver Returns Credit When Buffer Space Is Freed 32/37
71 Credit-Based Flow Control Receive Buffer Credit Credit Due: 0 Sender Receiver Sender Has A Limited Supply Of Credit Sending Data Uses Credit Receiver Returns Credit When Buffer Space Is Freed 32/37
72 Credit-Based Flow Control Receive Buffer Credit Credit Due: 0 Sender Receiver Sender Has A Limited Supply Of Credit Sending Data Uses Credit Receiver Returns Credit When Buffer Space Is Freed 32/37
73 Credit-Based Flow Control Receive Buffer Credit Credit Due: 0 Sender Receiver Sender Has A Limited Supply Of Credit Sending Data Uses Credit Receiver Returns Credit When Buffer Space Is Freed 32/37
74 Credit-Based Flow Control Receive Buffer Credit Credit Due: 0 Sender Receiver Sender Has A Limited Supply Of Credit Sending Data Uses Credit Receiver Returns Credit When Buffer Space Is Freed 32/37
75 Credit-Based Flow Control Receive Buffer Credit Credit Due: 0 Sender Receiver Sender Has A Limited Supply Of Credit Sending Data Uses Credit Receiver Returns Credit When Buffer Space Is Freed 32/37
76 Credit-Based Flow Control Receive Buffer Credit Credit Due: 0 Sender Receiver Sender Has A Limited Supply Of Credit Sending Data Uses Credit Receiver Returns Credit When Buffer Space Is Freed 32/37
77 Credit-Based Flow Control Receive Buffer Credit Credit Due: 0 Sender Receiver Sender Has A Limited Supply Of Credit Sending Data Uses Credit Receiver Returns Credit When Buffer Space Is Freed 32/37
78 Credit-Based Flow Control Receive Buffer Credit Credit Due: 1 Sender Receiver Sender Has A Limited Supply Of Credit Sending Data Uses Credit Receiver Returns Credit When Buffer Space Is Freed 32/37
79 Credit-Based Flow Control Receive Buffer Credit Credit Due: 1 Sender Receiver Sender Has A Limited Supply Of Credit Sending Data Uses Credit Receiver Returns Credit When Buffer Space Is Freed 32/37
80 Credit-Based Flow Control Receive Buffer Credit Credit Due: 1 Sender Receiver Sender Has A Limited Supply Of Credit Sending Data Uses Credit Receiver Returns Credit When Buffer Space Is Freed 32/37
81 Credit-Based Flow Control Receive Buffer Credit Credit Due: 1 Sender Receiver Sender Has A Limited Supply Of Credit Sending Data Uses Credit Receiver Returns Credit When Buffer Space Is Freed 32/37
82 Credit-Based Flow Control Receive Buffer Credit Credit Due: 1 Sender Receiver Sender Has A Limited Supply Of Credit Sending Data Uses Credit Receiver Returns Credit When Buffer Space Is Freed 32/37
83 Credit-Based Flow Control Receive Buffer Credit Credit Due: 2 Sender Receiver Sender Has A Limited Supply Of Credit Sending Data Uses Credit Receiver Returns Credit When Buffer Space Is Freed 32/37
84 Credit-Based Flow Control Receive Buffer Credit Credit Due: 2 Sender Receiver Sender Has A Limited Supply Of Credit Sending Data Uses Credit Receiver Returns Credit When Buffer Space Is Freed 32/37
85 Credit-Based Flow Control Receive Buffer Credit Credit Due: 2 Sender Receiver Sender Has A Limited Supply Of Credit Sending Data Uses Credit Receiver Returns Credit When Buffer Space Is Freed 32/37
86 Credit-Based Flow Control Receive Buffer Credit Credit Due: 2 Sender Receiver Sender Has A Limited Supply Of Credit Sending Data Uses Credit Receiver Returns Credit When Buffer Space Is Freed 32/37
87 Credit-Based Flow Control Receive Buffer Credit Credit Due: 2 Sender Receiver Sender Has A Limited Supply Of Credit Sending Data Uses Credit Receiver Returns Credit When Buffer Space Is Freed 32/37
88 Credit-Based Flow Control Receive Buffer Credit Credit Due: 3 Sender Receiver Sender Has A Limited Supply Of Credit Sending Data Uses Credit Receiver Returns Credit When Buffer Space Is Freed 32/37
89 Credit-Based Flow Control Receive Buffer Credit 3 Credit Due: 0 Sender Receiver Sender Has A Limited Supply Of Credit Sending Data Uses Credit Receiver Returns Credit When Buffer Space Is Freed 32/37
90 Credit-Based Flow Control Receive Buffer Credit 3 Credit Due: 0 Sender Receiver Sender Has A Limited Supply Of Credit Sending Data Uses Credit Receiver Returns Credit When Buffer Space Is Freed 32/37
91 Credit-Based Flow Control Receive Buffer Credit 3 Credit Due: 0 Sender Receiver Sender Has A Limited Supply Of Credit Sending Data Uses Credit Receiver Returns Credit When Buffer Space Is Freed 32/37
92 Credit-Based Flow Control Receive Buffer Credit Credit Due: 0 Sender Receiver Sender Has A Limited Supply Of Credit Sending Data Uses Credit Receiver Returns Credit When Buffer Space Is Freed 32/37
93 Credit-Based Flow Control Receive Buffer Credit Credit Due: 0 Sender Receiver Sender Has A Limited Supply Of Credit Sending Data Uses Credit Receiver Returns Credit When Buffer Space Is Freed 32/37
94 Credit-Based Flow Control Receive Buffer Credit Credit Due: 0 Sender Receiver Sender Has A Limited Supply Of Credit Sending Data Uses Credit Receiver Returns Credit When Buffer Space Is Freed 32/37
95 Credit-Based Flow Control Receive Buffer Credit Credit Due: 0 Sender Receiver Sender Has A Limited Supply Of Credit Sending Data Uses Credit Receiver Returns Credit When Buffer Space Is Freed 32/37
96 Credit-Based Flow Control Receive Buffer Credit Credit Due: 0 Sender Receiver Sender Has A Limited Supply Of Credit Sending Data Uses Credit Receiver Returns Credit When Buffer Space Is Freed 32/37
97 Protocol Layers Recap Physical Layer Send/Receive Raw Data Data-Link Layer Send/Receive Some Data Reliably Transaction Layer Send/Receive High-Level Requests 33/37
98 PCI-Express on SpiNNaker I/O Via Ethernet is Slow Three FPGAs per Board Some Spare S-ATA Cable Connectors Use S-ATA Cable to PCIe Card Adapter Implement PCIe on FPGA 34/37
99 Xilinx Spartan-6 PCIe IP Core PCIe Signals GPE Transceiver (Hard IP) Spartan-6 Integrated Endpoint Block for PCIe Transaction Stream (AXI4) Configuration Interface clk & reset CoreGenerator IP PCIe v1.1 x1 (2 Gb/s) Comes Free With FPGA 35/37
100 Summary SpiNNaker Needs a Fast Host Interface PCI-Express Widely Used In PCs Bottom-up Through the Protocol Layers Physical Layer Data-Link Layer Transaction Layer SpiNNaker & FPGAs 36/37
101 37/37
102 A n y Q u e s t i o n s? 37/37
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