PCI Express: Evolution, Deployment and Challenges

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Freescale Technology Forum, Beijing Track: Enabling

1 PCI Express: Evolution, Deployment and Challenges Nick Ma 马明辉 Field Applications Engineer, PLX Freescale Technology Forum, Beijing Track: Enabling Technologies Freescale Technology Forum, Beijing - November

2 Agenda Interconnect Evolution PCI to PCI Express PCI Based Systems Usage models PCI Express Systems Usage models Design considerations of PCIe systems Freescale Processors Market Trends Q & A Freescale Technology Forum, Beijing - November

3 Evolution of PCI to PCI Express PCI/PCIe has a significant Ecosystem available in the market today! Many different devices spanning a large number of various functionalities Large investment made in drivers and other software PCI Express (PCIe) completely leverages the software model developed for PCI PCI/PCIe is a de facto standard on PC, Server, Workstation, Blade, and Embedded Processors PCI/PCIe is replacing proprietary Bus Architectures found in Embedded designs of yesterday: Chip-to-Chip interconnects Control Backplane busses Embedded system busses Freescale Technology Forum, Beijing - November

4 Evolution of PCI to PCI Express PCI MHz Introduced in 1993 Limited to 10 loads per bus Can run at lower speed to accommodate more loads Peak Bandwidth: 133MB/sec PCI MHz Introduced in 1995 Limited to 5 loads per bus 64 bits addressing with single address cycle Peak Bandwidth: 533MB/sec Load Count: Devices = 1; Slot/Add-in Cards = 2 Freescale Technology Forum, Beijing - November

5 Evolution of PCI to PCI Express PCI-X has improvements over PCI Introduced in 1999 Specification for higher bus speeds Increased efficiency of bus transfers with protocol enhancements Split Transactions allowing the bus to be utilized by another device while the slave (completer) device is gathering the read data PCI bus transfer efficiency: 50-60% PCI-X bus transfer efficiency: 85% Freescale Technology Forum, Beijing - November

6 Evolution of PCI to PCI Express PCI-X MHz Limited to two-three loads per bus Peak Bandwidth: 800MB/sec PCI-X MHz Point to Point Bus limited to one-two loads per bus* Peak Bandwidth: 1066MB/sec PCI-X based systems can run at lower bus speed to increase the number of loads and take advantage of PCI-X split transaction feature Load Count: Devices = 1; Slot/Add-in Cards = 2 Freescale Technology Forum, Beijing - November

7 Evolution of PCI to PCI Express PCI Express Introduced in 2002 Packet based high-speed serial lines Point-to-Point Differential signaling PCIe is switched versus a multi-drop bus found in PCI Higher Throughput; Higher Bandwidth/pin; and Scalable Interconnect Full Duplex Transmit and Receive Simultaneously Freescale Technology Forum, Beijing - November

8 Evolution of PCI to PCI Express Each SerDes (serial) line runs at: PCIe 1.0 Gen1: 2.5 Gb/sec Aggregate Bandwidth: x1=0.5; x4=2; x8=4; x16=8 GB/sec PCIe 2.0 Gen2: 5.0 Gb/sec (2X throughput of Gen1) Aggregate Bandwidth: x1=1; x4=4; x8=8; x16=16 GB/sec PCIe 3.0 Gen3: 8.0 Gb/sec (2X throughput of Gen2) Aggregate Bandwidth: x1=2; x4=8; x8=16; x16=32 GB/sec Freescale Technology Forum, Beijing - November

9 Networking Bandwidth and PCI/PCIe 40 Gbps 100 Gbps Dual 10 Gbps 10 Gbps PCIe 3.0 (Gen3) Quad 1 Gbps PCIe 2.0 (Gen2) 100 Mbps 1 Gbps PCIe 1.0 (Gen1) PCI-X 100/133MHz PCI 66MHz 10 Mbps PCI 33MHz ISA/EISA Freescale Technology Forum, Beijing - November

10 Storage Bandwidth and PCI/PCIe SCSI 1 Gbps FC 40 Gbps FCOE 16 Gbps FC Dual 8 Gbps FC Dual 4 Gbps PCIe 3.0 (Gen3) FC Dual 2 Gbps FC/ PCIe 2.0 (Gen2) 4 Gbps FC 2 Gbps FC PCIe 1.0 (Gen1) PCI 33MHz PCI-X 100/133MHz PCI 66MHz ISA/EISA Freescale Technology Forum, Beijing - November

11 Graphics and PCI/PCIe Very High Performance Graphics PCIe 3.0 (Gen3) Graphics Cards High Performance Graphics High Performance Graphics PCI 66MHz PCI 33MHz AGP PCIe 1.0 (Gen1) PCIe 2.0 (Gen2) ISA/EISA Freescale Technology Forum, Beijing - November

12 Agenda Interconnect Evolution PCI to PCI Express PCI Based Systems Usage models PCI Express Systems Usage models Design considerations of PCIe systems Freescale Processors Market Trends Q & A Freescale Technology Forum, Beijing - November

13 PCI Based Embedded Systems 10/100/1000 Ethernet Serial Embedded Processor Mem Flash ASIC PCI To Backplane ASIC Controller Card Freescale Technology Forum, Beijing - November

14 PCI Based Embedded Systems 10/100/1000 Ethernet Serial Embedded Processor Mem Flash Addition of PCI-PCI bridge to increase number of PCI loads ASIC PCI ASIC PCI 2 PCI Bridge To Backplane Controller Card Freescale Technology Forum, Beijing - November

PCI-X Based Embedded Systems 10/100/1000 Ethernet Serial Embedded Processor Mem Flash Limit of two-three loads on PCI-X bus @ 100MHz PCI-X Bus @ 100 MHz ASIC Limit of one-two

15 PCI-X Based Embedded Systems 10/100/1000 Ethernet Serial Embedded Processor Mem Flash Limit of two-three loads on PCI-X 100MHz PCI-X 100 MHz ASIC Limit of one-two loads on PCI-X 133MHz PCI-X2PCI Bridge Load Count: Devices = 1 Slot/Add-in Cards = 2 To Backplane Controller Card Freescale Technology Forum, Beijing - November

16 PCI Based Embedded Systems 10/100/1000 Ethernet (Management) Serial Embedded Processor Mem Flash ASIC PCI ASIC Ethernet To Backplane Controller Card Freescale Technology Forum, Beijing - November

17 Latency Comparison PCI MHz: Read Access Time = 510ns PCI MHz: Read Access Time = 150ns PCI-X: Read Access Time = 80ns or 60ns 8 clocks of 10ns (100MHz) or 7.5ns (133MHz) Freescale Technology Forum, Beijing - November

18 Agenda Interconnect Evolution PCI to PCI Express PCI Based Systems Usage models PCI Express Systems Usage models Design considerations of PCIe systems Freescale Processors Market Trends Q & A Freescale Technology Forum, Beijing - November

19 Advantages of PCIe based systems Scalability Number of Ports and Lanes per Port Higher Throughput (Less Transport Delay) Less number of wires per Gbps Higher bandwidth per pin System implementations require fewer lines Hence, overall reduced system cost per unit bandwidth Freescale Technology Forum, Beijing - November

20 PCIe Based Embedded Systems 10/100/1000 Ethernet Serial Embedded Processor Mem Flash PCIe PCI/PCI-X PCIe ASIC Switch ASIC To Backplane Controller Card Freescale Technology Forum, Beijing - November

21 PCIe Based Embedded Systems 10/100/1000 Ethernet Serial Embedded Processor Mem Flash PCIe PCIe ASIC Switch ASIC To Backplane Controller Card Freescale Technology Forum, Beijing - November

22 PCIe Based Embedded Systems Backplanes Line Card ASIC PCIe Switch Controller Card ASIC PCIe Embedded Switch Processor Controller Card Line Card ASIC PCIe PCIe Switch Embedded Processor Switch ASIC Freescale Technology Forum, Beijing - November

23 PCIe Based Embedded System CPU Freescale Memory x4 ASIC Image Processing - 1 x4 PEX 8525 x4 ASIC Engine Control 2 x4 x4 ASIC Image Processing 2 ASIC Engine Control 1 Freescale Technology Forum, Beijing - November

24 Agenda Interconnect Evolution PCI to PCI Express PCI Based Systems Usage models PCI Express Systems Usage models Design considerations of PCIe systems Freescale Processors Market Trends Q & A Freescale Technology Forum, Beijing - November

25 Gen 1 Layout of the System Gen 1 (2.5 Gbps) layout is fairly simple with standard FR-4 material General rules Keep number of discontinuities minimal Keep higher trace width (smaller resistance, minimal 5mils, 6 mils desirable) and ½ oz copper on the trace Chip-to-Chip Two Break out of the chip Backplane (up to 40 of trace) Four Vias Two on the break out of the chip Two on the backplane connectors Freescale Technology Forum, Beijing - November

26 Gen 1 Layout of the System Cable (Up to 7-10 meters of cable) can be driven by PCIe Switches and Bridges Optical (EMCORE modules) another option for Gen 1 that can scale to Gen 3 and beyond Freescale Technology Forum, Beijing - November

27 Gen 2 Layout of the System Gen 2 (5 Gbps) layout needs scrutiny with standard FR- 4 material General rules Keep number of discontinuities minimal Keep higher trace width (smaller resistance, minimal 5mils, 6 mils desirable) and ½ oz copper on the trace Chip-to-Chip Two Break out of the chip Backplane (up to 40 of trace) Four Vias Two on the break out of the chip Two on the backplane connectors Freescale Technology Forum, Beijing - November

28 Gen 2 Layout of the System Cable (Up to 3-5 meters of cable) can be driven by PCIe switches and Bridges Optical (EMCORE modules) another option for Gen 1 that can scale to Gen 3 and beyond At Gen 2 rate, simulation is highly suggested Other options for less lossy material Nelco 4000-SI-13, Nelco 6000, Rogers,. With standard Tx and Rx with pre-emphasis and deemphasis should work for 40 of trace length Shown in PLX Freescale Technology Forum, Beijing - November

29 Dual Cast Feature Relieves CPU Source Port Switch Exclusive feature from PLX Allows forwarding of one ingress packet to two egress ports Posted transactions only (Memory Writes) Forward ingress packet to any 2 user selectable ports ACKs have to be received for both copies 8 Dual Cast Windows available Select 8 address ranges to copy from Used to segment traffic Destination Port Dual Cast Port Useful for different applications Storage Systems (Redundancy) Dual Host (High Availability) Systems Traffic monitoring Increases CPU performance! Relieves CPU from dual writes of same data Ask about the Dual Cast training video with audio Freescale Technology Forum, Beijing - November

30 Eight Dual Cast Windows Source Port One Source Port One Dual Cast Port ( copy to port) Up to 8 Destination Ports ( copy from ports) Destination Port Switch Dual Cast Port 8 Dual Cast Windows 8 address windows to be copied from Can all be within one egress port Can be distributed amongst up to 8 egress ports All 8 windows get copied to same Dual Cast port Freescale Technology Forum, Beijing - November

Eight Dual Cast Windows Example In this example, all 8 BARs are located in 8 different Destination Ports Source Port Any data written to BAR 0 in Destination Port will be copied to corresponding

31 Eight Dual Cast Windows Example In this example, all 8 BARs are located in 8 different Destination Ports Source Port Any data written to BAR 0 in Destination Port will be copied to corresponding address window (BAR 0) in Dual Cast port PEX 8648 BAR 0 BAR 1 BAR 2 BAR 3 BAR 4 BAR 5 BAR 6 BAR 7 BAR 0 BAR 1 BAR 2 BAR 3 BAR 4 BAR 5 BAR 6 BAR 7 Destination Port 1 Destination Port 2 Destination Port 3 Destination Port 4 Destination Port 5 Destination Port 6 Destination Port 7 Destination Port 8 Dual Cast Port Freescale Technology Forum, Beijing - November

Fail-Over System (NT and Dual Cast) Applications Servers SAN/NAS System A L7 Switches Routing System B Dual Cast Data going to each downstream port on switch being copied to other system via NT Port

32 Fail-Over System (NT and Dual Cast) Applications Servers SAN/NAS System A L7 Switches Routing System B Dual Cast Data going to each downstream port on switch being copied to other system via NT Port Processor (Primary) Root Complex Processor (Backup) Root Complex Non-Transparent Port Failover Processor Isolation Address Translation PEX 8632 NT x4 & x8 x4 & x8 NT PEX 8632 Hot-Plug Controllers Allows for live board or blade replacement & servicing Freescale Technology Forum, Beijing - November

33 Dual Clock Domain Support Support of two clock domains: Spread Spectrum Clock Domain Modulated clock input 100MHz +/-30kHz (300ppm) Constant Frequency Clock Domain Constant clock input 100MHz Host 1 SSC Domain 1 Host 2 SSC Domain 2 Applications of Dual Clock Domain Architectures: Removes requirement for single source clock Important for modular systems Connection of two different Host systems using their own Spread Spectrum clock. PCIe over cable/fiber over long distances Freescale Technology Forum, Beijing - November

34 Dual Clock Domain Architecture T Host 1 SSC Domain 1 OSC SSC Clock Buffer CPU Bridge Constant Clock Domain (Non-SSC) CPU Bridge Host 2 SSC Domain 2 OSC SSC Clock Buffer I/O I/O I/O Switch NT T NT Switch I/O I/O OSC OSC I/O Constant Clock Input Freescale Technology Forum, Beijing - November

35 PCIe Switch with DMA PCIe Switch is a Multi-Function device Function 0 P-to-P bridge Transparent Switch model No Driver Required Function 1 DMA endpoint Type 0 Configuration Header Memory mapped registers Requires DMA Driver Provided by PLX Availability December 2008 PEX8619: 16-lane/16-Port PEX8615: 12-lane/12-Port PEX8609: 8-lane/8-Port P-P Bridge DMA F1 Upstream Port P-P Bridge P-P Bridge Downstream Ports Virtual Bus P-P Bridge P-P Bridge Freescale Technology Forum, Beijing - November

36 DMA Benefits Independent Data Mover Can transfer small and large blocks of data No CPU involvement Can transfer data between all switch ports Centralized DMA Engine Processor/chipset no longer needs to support DMA More selection lower cost Software consolidation through multiple platforms Software code for one DMA engine Improves system performance Low latency transfers while sustaining Gen 2 speeds Freescale Technology Forum, Beijing - November

37 Packet-Ahead Feature Allows the NT port to modify the original Traffic Class (TC) of a PCIe packet From TC0 to TCx where TCx is TC1 TC7 Benefits Provides two separate data paths for memory traffic Low priority, High priority Enhanced QoS regardless of CPU single VC limitation Differentiation of traffic in single VC systems Available in PEX8618, PEX8614 and PEX8608 Freescale Technology Forum, Beijing - November

38 Example with Packet-Ahead Same CPU Limitations VC0 and TC0 only Same Endpoint and Switch capabilities VC0 VC1; TC0 TC1 CPU Two paths to CPU Via Upstream Port and NT Port NT PEX 8618 For packets received on NT Port TC is changed from TC0 to TC1 Are mapped to High Priority VC1 ASIC ASIC ASIC Packets received on upstream port are unaffected Freescale Technology Forum, Beijing - November

39 PLX PCIe Debug Features SerDes Link Training and Status State Machine state changes saved Monitor any port on the device On-chip collection & extraction of SerDes receiver Eye width Scope reference clock jitter most critical for Gen2 Loopback modes: internal, external, recovered clock, recovered data Error Injection Confirm how your software handles errors found in packets. Freescale Technology Forum, Beijing - November

40 PLX PCIe Debug Features (cont d) Datapath Bad DLLP and TLP error counters Probe Mode Access to internal data paths & state machines Trigger on user specified state change Storage of states in on-chip memory Performance Monitor Obtain detailed visibility/analysis of what kind of PCIe traffic is coming in and going out of each port (TLP; DLLP; Posted; Non- Posted; Completion; Data Throughput) PCIe Gen2 packet generator Functional testing at line rate Any TLP can be programmed Sequence and Looping Freescale Technology Forum, Beijing - November

41 PLX PEX 8600 Buffer Allocation Shared memory pool per 16 lanes PLX Buffer Allocation x4 User assigns buffers as per port-width Set minimum buffers per ports Also creates a common pool Ports dynamically grab buffers as needed Grab when utilization of assigned buffers exceeds user-assigned thresholds (25% by default) Return empty buffers to the pool x4 x2 x2 Assigned Buffers Common Buffer Pool Assigned Buffers Freescale Technology Forum, Beijing - November

42 Dynamic Allocation Appropriate Buffers Static Buffers/port Unused buffers Can not assign based on traffic load Can not move buffers between ports LOWER PERFORMANCE Static Buffers/port x8 Unused buffers Fixed 5 packet buffers for each ports for all port widths PLX Shared Memory Pool All buffers usable Assign based on traffic load Move buffers around between ports HIGHER PERFORMANCE x1 x4 x8 Shared Memory Pool x8 Buffers assign as needed x1 x4 x8 Freescale Technology Forum, Beijing - November

43 Read Pacing Problem Reduced endpoint performance caused by: Unbalanced upstream/downstream link-widths Uneven number of Read Requests made by endpoints Leads to one endpoint dominating Root Complex queue Other endpoints get starved Solution PLX Read Pacing Read Pacing Queues manage incoming Read Requests Prevents one endpoint from dominating Root Complex queue Ensures no endpoint is starved Allows for optimized performance of endpoints * Patents pending Freescale Technology Forum, Beijing - November

44 Without Read Pacing Performance bottleneck due to mixing of slow and fast I/Os 1. FC HBA makes multiple 2KB Read Requests 2. Root Complex queues FC HBA requests 3. Ethernet NIC makes one 1KB Read Requests 4. Root Complex queues Ethernet NIC request 5. Ethernet NIC must wait for RC to service FC HBA requests before serving Ethernet NIC request Root Complex IN 2KB RR 2KB RR 2KB RR 2KB RR 1KB RR x8 Switch 1KB Data 2KB Data 2KB Data 2KB Data 2KB Data OUT Ethernet NIC packets at the end of the line 6. Ethernet NIC is starved Reduced Ethernet NIC Performance! Sends 2KB Read Requests FC HBA x4 2KB RR x4 1KB RR Sends 1KB Read Requests Ethernet NIC Freescale Technology Forum, Beijing - November

45 With PLX s Read Pacing Increased performance due to fair allocation of bandwidth to downstream ports 1. FC HBA makes multiple 2KB Read Requests 2. Switch allows one FC HBA request at a time to pass through based on programmable thresholds 3. Ethernet NIC makes one 1KB Read Requests 4. Switch allows one requests to pass through the switch based on programmable thresholds 5. Switch continues to allow Ethernet NIC requests to pass through in front of large FC HBA requests based on programmable settings 6. Ethernet NIC gets serviced more often with no impact to FC HBA performance 7. Neither endpoint is starved Optimized Performance! FC HBA Root Complex IN 2KB RR 2KB RR 2KB RR 1KB RR 1KB RR x8 Read Pacing Queue Sends 2KB x4 Read Requests 2KB RR PEX 86xx 2KB Data 1KB Data 2KB Data 1KB Data 2KB Data OUT Ethernet NIC packets fairly queued Read Pacing Queue Sends 1KB x4 Read Requests 1KB RR Ethernet 1KB NIC RR Freescale Technology Forum, Beijing - November

46 Agenda Interconnect Evolution PCI to PCI Express PCI Based Systems Usage models PCI Express Systems Usage models Design considerations of PCIe systems Freescale Processors Market Trends Q & A Freescale Technology Forum, Beijing - November

47 Freescale, PCIe Gen 1 Device Gen 1 PCIe Comments Relevant PLX Switch MPC8314E MPC8315E MPC8377E MPC8378E 2 x1 PCIe 2 x1 PCIe 2 x1 PCIe or 1 x2 PCIe 2 x1 or 1 x2 PCIe Targeted at WLAN AP, Residential Gateways, Printers Targeted at NAS, Digital Media Server, WLAN AP, Residential Gateways Targeted at SMB, WAP, NAS, Printers, SMB routers Targeted at SMB, WAP, NAS, Printers, SMB routers 8608/8606/ /8606/ /8606/ /8606/8604 MPC8533E 2 x4 PCIe + 1 x1 PCIe High-performance Processor 8618/8614/8608 MPC8536E 1 x8 PCIe or 2 x4 PCIe or 1 x4 + 2 x2 PCIe Routers, switches, wireless base stations 8632/8624/8618/8614/8608/ 8606/8604 MPC8543E 1 x4 PCIe General Purpose Control Processor 8618/8614/8608 MPC8544E 2 x4 PCIe + 1 x1 PCIe Communications Processor 8618/8614/8608 MPC8545E 1 x4 PCIe Imaging Processor 8618/8614/8608 Freescale Technology Forum, Beijing - November

48 Freescale, PCIe Gen 1 (continued) Device Gen 1 PCIe Comments Relevant PLX Switch MPC8547E 1 x4 PCIe Storage Processor 8618/8614/8608 MPC8548E 1 x8 PCIe Networking/Telecom Processor 8632/8624/8618/8614/8608 MPC8567E MPC8568E MPC8572E 1 x4 PCIe 1 x8 PCIe 1 x8 PCIe or 2 x4 PCIe Broadband Access Equipment Processor Broadband Access Equipment Processor Targeted at networking, telecommunications and wireless infrastructure applications 8618/8614/ /8624/8618/8614/ /8624/8618/8614/8608 MPC x8 PCIe + 1 x4 PCIe MFP, SBC, Scanners 8632/8624/8618/8614/8608 MPC x8 PCIe High-performance Single-Core Processor 8632/8624/8618/8614/8608 MPC8641D P1010, P1011, P1020 P2010, P x8 PCIe P1010 = 2 x1 PCIe; P1011/1020 = 2 x2 PCIe 3 x1 PCIe High-performance Dual-Core Processor P Single-Core 667 MHz, P Single-Core 800 MHz, P Dual-Core 800 MHz P Single-Core 1.2 GHz, P Dual-Core 1.2 GHz 8632/8624/8618/8614/ /8606/ /8606/8604 Freescale Technology Forum, Beijing - November

49 Freescale, PCIe Gen 2 Device Gen 2 PCIe Comments Relevant PLX Switch P x8 Gen 2 PCIe Targeted at networking, telecommunications and wireless infrastructure applications 8632/8624/8618/8614/8608 Freescale Technology Forum, Beijing - November

50 PLX Features Complement Freescale Up to 16 ports Provides fan-out connectivity to multiple PCIe end-points 2 Virtual Channels Provide QoS 4-channel DMA Complementary to Freescale s DMA Enhances system performance Dual Cast Writes same packet to 2 different ports Saves CPU cycles and improves system performance Integrated Non-Transparency Port Provides redundancy in the system PLX provides single-chip solution with integrated NT Freescale Technology Forum, Beijing - November

51 PLX PCIe Gen 2 Switches, Available Now Feature PEX 8648 PEX 8647 PEX 8632 PEX 8624 PEX 8619 PEX 8618 PEX 8616 PEX 8615 PEX 8614 PEX 8612 PEX 8609 PEX 8608 PEX 8606 PEX 8604 Lanes Ports Latency 140ns (x16) 140ns (x16) 160ns (x8) 160ns (x8) 140ns (x4) 140ns (x4) 170ns (x4) 140ns (x4) 140ns (x4) 170ns (x4) 140ns (x4) 140ns (x4) 190ns (x4) 190ns (x4) Non- Transparency Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Read Pacing Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Dual Cast Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DMA Yes Yes Yes SSC Isolation Yes Yes -- Yes Yes -- Yes Yes Yes Yes Hot-Plug Ports 3 SHPC & 9 Serial 3 SHPC & 9 Serial 3 SHPC & 3 Serial 16 Serial 16 Serial 2 SHPC & 2 Serial 12 Serial 12 Serial 2 SHPC & 1 Serial 8 Serial 8 Serial 6 Serial 4 Serial Maximum Payload 2 KB 2 KB 2 KB 2 KB 2 KB 2 KB 2 KB 2 KB 2 KB 2 KB 2 KB 2 KB 2 KB 2 KB Package (mm 2 ) 27x27 27x27 27x27 19x19 19x19 19x19 19x19 19x19 19x19 19x19 15x15 15x15 15x15 15x15 Power (Typ.) 4.0W 3.8W 2.8W 3.0W 2.0W 1.9W 2.2W 1.6W 1.5W 2.0W 1.2W 1.2W 1.0W 0.8W Samples Now Now Now Now Jan 09 Now Now Jan 09 Now Now Jan 09 Now Now Now Production Dec 08 Dec 08 Dec 08 Dec 08 Apr 09 Q1-09 Dec 08 Apr 09 Q1-09 Dec 08 Apr 09 Q1-09 Q1-09 Q1-09 More Gen 2 devices are in development PLX encourages new designs to use Gen 2 parts even if only Gen 1 needed Freescale Technology Forum, Beijing - November

52 Q & A Questions? Freescale Technology Forum, Beijing - November

53 Thank you More Information: Nick Ma 马明辉 Field Applications Engineer, PLX Technical Sales excelpoint.com.cn Freescale Technology Forum, Beijing - November

PEX 8636, PCI Express Gen 2 Switch, 36 Lanes, 24 Ports

PEX 8636, PCI Express Gen 2 Switch, 36 Lanes, 24 Ports Highlights PEX 8636 General Features o 36-lane, 24-port PCIe Gen2 switch - Integrated 5.0 GT/s SerDes o 35 x 35mm 2, 1156-ball FCBGA package o Typical Power: 8.8 Watts PEX 8636 Key Features o Standards