PCI Express Base Specification Revision 3.0. November 10, 2010

Transcription

1 PCI Express Base Specification Revision 3.0 November 10, 2010

2 Revision Revision History DATE 1.0 Initial release. 07/22/ a Incorporated Errata C1-C66 and E1-E /15/ Incorporated approved Errata and ECNs. 03/28/ Added 5.0 GT/s data rate and incorporated approved Errata and ECNs. 12/20/ Incorporated Errata for the PCI Express Base Specification, Rev. 2.0 (February 27, 2009), and added the following ECNs: Internal Error Reporting ECN (April 24, 2008) Multicast ECN (December 14, 2007, approved by PWG May 8, 2008) Atomic Operations ECN (January 15, 2008, approved by PWG April 17, 2008) Resizable BAR Capability ECN (January 22, 2008, updated and approved by PWG April 24, 2008) Dynamic Power Allocation ECN (May 24, 2008) ID-Based Ordering ECN (January 16, 2008, updated 29 May 2008) Latency Tolerance Reporting ECN (22 January 2008, updated 14 August 2008) Alternative Routing-ID Interpretation (ARI) ECN (August 7, 2006, last updated June 4, 2007) Extended Tag Enable Default ECN (September 5, 2008) TLP Processing Hints ECN (September 11, 2008) TLP Prefix ECN (December 15, 2008) 3.0 Added 8.0 GT/s data rate, latest approved Errata, and the following ECNs: Optimized Buffer Flush/Fill ECN (8 February 2008, updated 30 April 2009) ASPM Optionality ECN (June 19, 2009, approved by the PWG August 20, 2009) Incorporated End-End TLP Changes for RCs ECN (26 May 2010) and Protocol Multiplexing ECN (17 June 2010) 03/04/ /10/2010 PCI-SIG disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does PCI-SIG make a commitment to update the information contained herein. Contact the PCI-SIG office to obtain the latest revision of this specification. Questions regarding the PCI Express Base Specification or membership in PCI-SIG may be forwarded to: Membership Services administration@pcisig.com Phone: Fax: Technical Support techsupp@pcisig.com DISCLAIMER This PCI Express Base Specification is provided as is with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. PCI-SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. PCI, PCI Express, PCIe, and PCI-SIG are trademarks or registered trademarks of PCI-SIG. All other product names are trademarks, registered trademarks, or servicemarks of their respective owners. Copyright PCI-SIG 2

3 Contents OBJECTIVE OF THE SPECIFICATION DOCUMENT ORGANIZATION DOCUMENTATION CONVENTIONS TERMS AND ACRONYMS REFERENCE DOCUMENTS INTRODUCTION A THIRD GENERATION I/O INTERCONNECT PCI EXPRESS LINK PCI EXPRESS FABRIC TOPOLOGY Root Complex Endpoints Switch Root Complex Event Collector PCI Express to PCI/PCI-X Bridge PCI EXPRESS FABRIC TOPOLOGY CONFIGURATION PCI EXPRESS LAYERING OVERVIEW Transaction Layer Data Link Layer Physical Layer Layer Functions and Services TRANSACTION LAYER SPECIFICATION TRANSACTION LAYER OVERVIEW Address Spaces, Transaction Types, and Usage Packet Format Overview TRANSACTION LAYER PROTOCOL - PACKET DEFINITION Common Packet Header Fields TLPs with Data Payloads - Rules TLP Digest Rules Routing and Addressing Rules First/Last DW Byte Enables Rules Transaction Descriptor Memory, I/O, and Configuration Request Rules Message Request Rules Completion Rules TLP Prefix Rules HANDLING OF RECEIVED TLPS

4 Request Handling Rules Completion Handling Rules TRANSACTION ORDERING Transaction Ordering Rules Update Ordering and Granularity Observed by a Read Transaction Update Ordering and Granularity Provided by a Write Transaction VIRTUAL CHANNEL (VC) MECHANISM Virtual Channel Identification (VC ID) TC to VC Mapping VC and TC Rules ORDERING AND RECEIVE BUFFER FLOW CONTROL Flow Control Rules DATA INTEGRITY ECRC Rules Error Forwarding COMPLETION TIMEOUT MECHANISM LINK STATUS DEPENDENCIES Transaction Layer Behavior in DL_Down Status Transaction Layer Behavior in DL_Up Status DATA LINK LAYER SPECIFICATION DATA LINK LAYER OVERVIEW DATA LINK CONTROL AND MANAGEMENT STATE MACHINE Data Link Control and Management State Machine Rules FLOW CONTROL INITIALIZATION PROTOCOL Flow Control Initialization State Machine Rules DATA LINK LAYER PACKETS (DLLPS) Data Link Layer Packet Rules DATA INTEGRITY Introduction LCRC, Sequence Number, and Retry Management (TLP Transmitter) LCRC and Sequence Number (TLP Receiver) PHYSICAL LAYER SPECIFICATION INTRODUCTION LOGICAL SUB-BLOCK Encoding for 2.5 GT/s and 5.0 GT/s Data Rates Encoding for 8.0 GT/s and Higher Data Rates Link Equalization Procedure for 8.0 GT/s Data Rate Link Initialization and Training Link Training and Status State Machine (LTSSM) Descriptions Link Training and Status State Rules Clock Tolerance Compensation Compliance Pattern in 8b/10b Encoding Modified Compliance Pattern in 8b/10b Encoding Compliance Pattern in 128b/130b Encoding Modified Compliance Pattern in 128b/130b Encoding

5 4.3. ELECTRICAL SUB-BLOCK Electrical Specification Organization Interoperability Criteria for 2.5, 5.0, and 8.0 GT/s Devices Transmitter Specification Receiver Specifications Low Frequency and Miscellaneous Signaling Requirements Channel Specification Refclk Specifications Refclk Specifications for 8.0 GT/s POWER MANAGEMENT OVERVIEW Statement of Requirements LINK STATE POWER MANAGEMENT PCI-PM SOFTWARE COMPATIBLE MECHANISMS Device Power Management States (D-States) of a Function PM Software Control of the Link Power Management State Power Management Event Mechanisms NATIVE PCI EXPRESS POWER MANAGEMENT MECHANISMS Active State Power Management (ASPM) AUXILIARY POWER SUPPORT Auxiliary Power Enabling POWER MANAGEMENT SYSTEM MESSAGES AND DLLPS SYSTEM ARCHITECTURE INTERRUPT AND PME SUPPORT Rationale for PCI Express Interrupt Model PCI Compatible INTx Emulation INTx Emulation Software Model Message Signaled Interrupt (MSI/MSI-X) Support PME Support Native PME Software Model Legacy PME Software Model Operating System Power Management Notification PME Routing Between PCI Express and PCI Hierarchies ERROR SIGNALING AND LOGGING Scope Error Classification Error Signaling Error Logging Sequence of Device Error Signaling and Logging Operations Error Message Controls Error Listing and Rules Virtual PCI Bridge Error Handling Internal Errors VIRTUAL CHANNEL SUPPORT Introduction and Scope

6 TC/VC Mapping and Example Usage VC Arbitration Isochronous Support DEVICE SYNCHRONIZATION LOCKED TRANSACTIONS Introduction Initiation and Propagation of Locked Transactions - Rules Switches and Lock - Rules PCI Express/PCI Bridges and Lock - Rules Root Complex and Lock - Rules Legacy Endpoints PCI Express Endpoints PCI EXPRESS RESET - RULES Conventional Reset Function-Level Reset (FLR) PCI EXPRESS HOT-PLUG SUPPORT Elements of Hot-Plug Registers Grouped by Hot-Plug Element Association PCI Express Hot-Plug Events Firmware Support for Hot-Plug POWER BUDGETING CAPABILITY System Power Budgeting Process Recommendations SLOT POWER LIMIT CONTROL ROOT COMPLEX TOPOLOGY DISCOVERY LINK SPEED MANAGEMENT ACCESS CONTROL SERVICES (ACS) ACS Component Capability Requirements Interoperability ACS Peer-to-Peer Control Interactions ACS Violation Error Handling ACS Redirection Impacts on Ordering Rules ALTERNATIVE ROUTING-ID INTERPRETATION (ARI) MULTICAST OPERATIONS Multicast TLP Processing Multicast Ordering Multicast Capability Structure Field Updates MC Blocked TLP Processing MC_Overlay Mechanism ATOMIC OPERATIONS (ATOMICOPS) AtomicOp Use Models and Benefits AtomicOp Transaction Protocol Summary Root Complex Support for AtomicOps Switch Support for AtomicOps DYNAMIC POWER ALLOCATION (DPA) CAPABILITY DPA Capability with Multi-Function Devices TLP PROCESSING HINTS (TPH)

7 Processing Hints Steering Tags ST Modes of Operation TPH Capability LATENCY TOLERANCE REPORTING (LTR) MECHANISM OPTIMIZED BUFFER FLUSH/FILL (OBFF) MECHANISM SOFTWARE INITIALIZATION AND CONFIGURATION CONFIGURATION TOPOLOGY PCI EXPRESS CONFIGURATION MECHANISMS PCI 3.0 Compatible Configuration Mechanism PCI Express Enhanced Configuration Access Mechanism (ECAM) Root Complex Register Block CONFIGURATION TRANSACTION RULES Device Number Configuration Transaction Addressing Configuration Request Routing Rules PCI Special Cycles CONFIGURATION REGISTER TYPES PCI-COMPATIBLE CONFIGURATION REGISTERS Type 0/1 Common Configuration Space Type 0 Configuration Space Header Type 1 Configuration Space Header PCI POWER MANAGEMENT CAPABILITY STRUCTURE MSI AND MSI-X CAPABILITY STRUCTURES Vector Control for MSI-X Table Entries PCI EXPRESS CAPABILITY STRUCTURE PCI Express Capability List Register (Offset 00h) PCI Express Capabilities Register (Offset 02h) Device Capabilities Register (Offset 04h) Device Control Register (Offset 08h) Device Status Register (Offset 0Ah) Link Capabilities Register (Offset 0Ch) Link Control Register (Offset 10h) Link Status Register (Offset 12h) Slot Capabilities Register (Offset 14h) Slot Control Register (Offset 18h) Slot Status Register (Offset 1Ah) Root Control Register (Offset 1Ch) Root Capabilities Register (Offset 1Eh) Root Status Register (Offset 20h) Device Capabilities 2 Register (Offset 24h) Device Control 2 Register (Offset 28h) Device Status 2 Register (Offset 2Ah) Link Capabilities 2 Register (Offset 2Ch) Link Control 2 Register (Offset 30h) Link Status 2 Register (Offset 32h)

8 Slot Capabilities 2 Register (Offset 34h) Slot Control 2 Register (Offset 38h) Slot Status 2 Register (Offset 3Ah) PCI EXPRESS EXTENDED CAPABILITIES Extended Capabilities in Configuration Space Extended Capabilities in the Root Complex Register Block PCI Express Extended Capability Header ADVANCED ERROR REPORTING CAPABILITY Advanced Error Reporting Extended Capability Header (Offset 00h) Uncorrectable Error Status Register (Offset 04h) Uncorrectable Error Mask Register (Offset 08h) Uncorrectable Error Severity Register (Offset 0Ch) Correctable Error Status Register (Offset 10h) Correctable Error Mask Register (Offset 14h) Advanced Error Capabilities and Control Register (Offset 18h) Header Log Register (Offset 1Ch) Root Error Command Register (Offset 2Ch) Root Error Status Register (Offset 30h) Error Source Identification Register (Offset 34h) TLP Prefix Log Register (Offset 38h) VIRTUAL CHANNEL CAPABILITY Virtual Channel Extended Capability Header (Offset 00h) Port VC Capability Register 1 (Offset 04h) Port VC Capability Register 2 (Offset 08h) Port VC Control Register (Offset 0Ch) Port VC Status Register (Offset 0Eh) VC Resource Capability Register VC Resource Control Register VC Resource Status Register VC Arbitration Table Port Arbitration Table DEVICE SERIAL NUMBER CAPABILITY Device Serial Number Extended Capability Header (Offset 00h) Serial Number Register (Offset 04h) PCI EXPRESS ROOT COMPLEX LINK DECLARATION CAPABILITY Root Complex Link Declaration Extended Capability Header (Offset 00h) Element Self Description (Offset 04h) Link Entries PCI EXPRESS ROOT COMPLEX INTERNAL LINK CONTROL CAPABILITY Root Complex Internal Link Control Extended Capability Header (Offset 00h) Root Complex Link Capabilities Register (Offset 04h) Root Complex Link Control Register (Offset 08h) Root Complex Link Status Register (Offset 0Ah) POWER BUDGETING CAPABILITY Power Budgeting Extended Capability Header (Offset 00h) Data Select Register (Offset 04h)

9 Data Register (Offset 08h) Power Budget Capability Register (Offset 0Ch) ACS EXTENDED CAPABILITY ACS Extended Capability Header (Offset 00h) ACS Capability Register (Offset 04h) ACS Control Register (Offset 06h) Egress Control Vector (Offset 08h) PCI EXPRESS ROOT COMPLEX EVENT COLLECTOR ENDPOINT ASSOCIATION CAPABILITY Root Complex Event Collector Endpoint Association Extended Capability Header (Offset 00h) Association Bitmap for Root Complex Integrated Endpoints (Offset 04h) MULTI-FUNCTION VIRTUAL CHANNEL CAPABILITY MFVC Extended Capability Header (Offset 00h) Port VC Capability Register 1 (Offset 04h) Port VC Capability Register 2 (Offset 08h) Port VC Control Register (Offset 0Ch) Port VC Status Register (Offset 0Eh) VC Resource Capability Register VC Resource Control Register VC Resource Status Register VC Arbitration Table Function Arbitration Table VENDOR-SPECIFIC CAPABILITY Vendor-Specific Extended Capability Header (Offset 00h) Vendor-Specific Header (Offset 04h) RCRB HEADER CAPABILITY RCRB Header Extended Capability Header (Offset 00h) Vendor ID (Offset 04h) and Device ID (Offset 06h) RCRB Capabilities (Offset 08h) RCRB Control (Offset 0Ch) MULTICAST CAPABILITY Multicast Extended Capability Header (Offset 00h) Multicast Capability Register (Offset 04h) Multicast Control Register (Offset 06h) MC_Base_Address Register (Offset 08h) MC_Receive Register (Offset 10h) MC_Block_All Register (Offset 18h) MC_Block_Untranslated Register (Offset 20h) MC_Overlay_BAR (Offset 28h) RESIZABLE BAR CAPABILITY Resizable BAR Extended Capability Header (Offset 00h) Resizable BAR Capability Register Resizable BAR Control Register ARI CAPABILITY ARI Capability Header (Offset 00h)

10 ARI Capability Register (Offset 04h) ARI Control Register (Offset 06h) DYNAMIC POWER ALLOCATION (DPA) CAPABILITY DPA Extended Capability Header (Offset 00h) DPA Capability Register (Offset 04h) DPA Latency Indicator Register (Offset 08h) DPA Status Register (Offset 0Ch) DPA Control Register (Offset 0Eh) DPA Power Allocation Array LATENCY TOLERANCE REPORTING (LTR) CAPABILITY LTR Extended Capability Header (Offset 00h) Max Snoop Latency Register (Offset 04h) Max No-Snoop Latency Register (Offset 06h) TPH REQUESTER CAPABILITY TPH Requester Extended Capability Header (Offset 00h) TPH Requester Capability Register (Offset 04h) TPH Requester Control Register (Offset 08h) TPH ST Table (Starting from Offset 0Ch) SECONDARY PCI EXPRESS EXTENDED CAPABILITY Secondary PCI Express Extended Capability Header (Offset 00h) Link Control 3 Register (Offset 04h) Lane Error Status Register (Offset 08h) Lane Equalization Control Register (Offset 0Ch) A. ISOCHRONOUS APPLICATIONS A.1. INTRODUCTION A.2. ISOCHRONOUS CONTRACT AND CONTRACT PARAMETERS A.2.1. Isochronous Time Period and Isochronous Virtual Timeslot A.2.2. Isochronous Payload Size A.2.3. Isochronous Bandwidth Allocation A.2.4. Isochronous Transaction Latency A.2.5. An Example Illustrating Isochronous Parameters A.3. ISOCHRONOUS TRANSACTION RULES A.4. TRANSACTION ORDERING A.5. ISOCHRONOUS DATA COHERENCY A.6. FLOW CONTROL A.7. CONSIDERATIONS FOR BANDWIDTH ALLOCATION A.7.1. Isochronous Bandwidth of PCI Express Links A.7.2. Isochronous Bandwidth of Endpoints A.7.3. Isochronous Bandwidth of Switches A.7.4. Isochronous Bandwidth of Root Complex A.8. CONSIDERATIONS FOR PCI EXPRESS COMPONENTS A.8.1. An Endpoint as a Requester A.8.2. An Endpoint as a Completer A.8.3. Switches A.8.4. Root Complex

11 B. SYMBOL ENCODING C. PHYSICAL LAYER APPENDIX C.1. 8B/10B DATA SCRAMBLING EXAMPLE C B/130B DATA SCRAMBLING EXAMPLE D. REQUEST DEPENDENCIES E. ID-BASED ORDERING USAGE E.1. INTRODUCTION E.2. POTENTIAL BENEFITS WITH IDO USE E.2.1. Benefits for MFD/RP Direct Connect E.2.2. Benefits for Switched Environments E.2.3. Benefits for Integrated Endpoints E.2.4. IDO Use in Conjunction with RO E.3. WHEN TO USE IDO E.4. WHEN NOT TO USE IDO E.4.1. When Not to Use IDO with Endpoints E.4.2. When Not to Use IDO with Root Ports E.5. SOFTWARE CONTROL OF IDO USE E.5.1. Software Control of Endpoint IDO Use E.5.2. Software Control of Root Port IDO Use F. MESSAGE CODE USAGE G. PROTOCOL MULTIPLEXING G.1. PROTOCOL MULTIPLEXING INTERACTIONS WITH PCI EXPRESS G.2. PMUX PACKETS G.3. PMUX PACKET LAYOUT G.3.1. PMUX Packet Layout for 8b10b Encoding G.3.2. PMUX Packet Layout at 128b/130b Encoding G.4. PMUX CONTROL G.5. PMUX EXTENDED CAPABILITY G.5.1. PCI Express Extended Header (Offset 00h) G.5.2. PMUX Capability Register (Offset 04h) G.5.3. PMUX Control Register (Offset 08h) G.5.4. PMUX Status Register (Offset 0Ch) G.5.5. PMUX Protocol Array (Offsets 10h Through 48h) ACKNOWLEDGEMENTS

12 Figures FIGURE 1-1: PCI EXPRESS LINK FIGURE 1-2: EXAMPLE TOPOLOGY FIGURE 1-3: LOGICAL BLOCK DIAGRAM OF A SWITCH FIGURE 1-4: HIGH-LEVEL LAYERING DIAGRAM FIGURE 1-5: PACKET FLOW THROUGH THE LAYERS FIGURE 2-1: LAYERING DIAGRAM HIGHLIGHTING THE TRANSACTION LAYER FIGURE 2-2: SERIAL VIEW OF A TLP FIGURE 2-3: GENERIC TLP FORMAT FIGURE 2-4: FIELDS PRESENT IN ALL TLPS FIGURE 2-5: FIELDS PRESENT IN ALL TLP HEADERS FIGURE 2-6: EXAMPLES OF COMPLETER TARGET MEMORY ACCESS FOR FETCHADD FIGURE 2-7: 64-BIT ADDRESS ROUTING FIGURE 2-8: 32-BIT ADDRESS ROUTING FIGURE 2-9: ID ROUTING WITH 4 DW HEADER FIGURE 2-10: ID ROUTING WITH 3 DW HEADER FIGURE 2-11: LOCATION OF BYTE ENABLES IN TLP HEADER FIGURE 2-12: TRANSACTION DESCRIPTOR FIGURE 2-13: TRANSACTION ID FIGURE 2-14: ATTRIBUTES FIELD OF TRANSACTION DESCRIPTOR FIGURE 2-15: REQUEST HEADER FORMAT FOR 64-BIT ADDRESSING OF MEMORY FIGURE 2-16: REQUEST HEADER FORMAT FOR 32-BIT ADDRESSING OF MEMORY FIGURE 2-17: REQUEST HEADER FORMAT FOR I/O TRANSACTIONS FIGURE 2-18: REQUEST HEADER FORMAT FOR CONFIGURATION TRANSACTIONS FIGURE 2-19: TPH TLP PREFIX FIGURE 2-20: LOCATION OF PH[1:0] IN A 4 DW REQUEST HEADER FIGURE 2-21: LOCATION OF PH[1:0] IN A 3 DW REQUEST HEADER FIGURE 2-22: LOCATION OF ST[7:0] IN THE MEMORY WRITE REQUEST HEADER FIGURE 2-23: LOCATION OF ST[7:0] IN MEMORY READ AND ATOMICOP REQUEST HEADERS FIGURE 2-24: MESSAGE REQUEST HEADER FIGURE 2-25: HEADER FOR VENDOR-DEFINED MESSAGES FIGURE 2-26: LTR MESSAGE FIGURE 2-27: OBFF MESSAGE FIGURE 2-28: COMPLETION HEADER FORMAT FIGURE 2-29: (NON-ARI) COMPLETER ID FIGURE 2-30: ARI COMPLETER ID FIGURE 2-31: FLOWCHART FOR HANDLING OF RECEIVED TLPS FIGURE 2-32: FLOWCHART FOR SWITCH HANDLING OF TLPS FIGURE 2-33: FLOWCHART FOR HANDLING OF RECEIVED REQUEST FIGURE 2-34: VIRTUAL CHANNEL CONCEPT AN ILLUSTRATION FIGURE 2-35: VIRTUAL CHANNEL CONCEPT SWITCH INTERNALS (UPSTREAM FLOW) FIGURE 2-36: AN EXAMPLE OF TC/VC CONFIGURATIONS FIGURE 2-37: RELATIONSHIP BETWEEN REQUESTER AND ULTIMATE COMPLETER

13 FIGURE 2-38: CALCULATION OF 32-BIT ECRC FOR TLP END TO END DATA INTEGRITY PROTECTION FIGURE 3-1: LAYERING DIAGRAM HIGHLIGHTING THE DATA LINK LAYER FIGURE 3-2: DATA LINK CONTROL AND MANAGEMENT STATE MACHINE FIGURE 3-3: VC0 FLOW CONTROL INITIALIZATION EXAMPLE WITH 8B/10B ENCODING-BASED FRAMING FIGURE 3-4: DLLP TYPE AND CRC FIELDS FIGURE 3-5: DATA LINK LAYER PACKET FORMAT FOR ACK AND NAK FIGURE 3-6: DATA LINK LAYER PACKET FORMAT FOR INITFC FIGURE 3-7: DATA LINK LAYER PACKET FORMAT FOR INITFC FIGURE 3-8: DATA LINK LAYER PACKET FORMAT FOR UPDATEFC FIGURE 3-9: PM DATA LINK LAYER PACKET FORMAT FIGURE 3-10: VENDOR SPECIFIC DATA LINK LAYER PACKET FORMAT FIGURE 3-11: DIAGRAM OF CRC CALCULATION FOR DLLPS FIGURE 3-12: TLP WITH LCRC AND TLP SEQUENCE NUMBER APPLIED FIGURE 3-13: TLP FOLLOWING APPLICATION OF TLP SEQUENCE NUMBER AND RESERVED BITS FIGURE 3-14: CALCULATION OF LCRC FIGURE 3-15: RECEIVED DLLP ERROR CHECK FLOWCHART FIGURE 3-16: ACK/NAK DLLP PROCESSING FLOWCHART FIGURE 3-17: RECEIVE DATA LINK LAYER HANDLING OF TLPS FIGURE 4-1: LAYERING DIAGRAM HIGHLIGHTING PHYSICAL LAYER FIGURE 4-2: CHARACTER TO SYMBOL MAPPING FIGURE 4-3: BIT TRANSMISSION ORDER ON PHYSICAL LANES - X1 EXAMPLE FIGURE 4-4: BIT TRANSMISSION ORDER ON PHYSICAL LANES - X4 EXAMPLE FIGURE 4-5: TLP WITH FRAMING SYMBOLS APPLIED FIGURE 4-6: DLLP WITH FRAMING SYMBOLS APPLIED FIGURE 4-7: FRAMED TLP ON A X1 LINK FIGURE 4-8: FRAMED TLP ON A X2 LINK FIGURE 4-9: FRAMED TLP ON A X4 LINK FIGURE 4-10: LFSR WITH SCRAMBLING POLYNOMIAL FIGURE 4-11: EXAMPLE OF BIT TRANSMISSION ORDER IN A X1 LINK SHOWING 130 BITS OF A BLOCK FIGURE 4-12: EXAMPLE OF BIT PLACEMENT IN A X4 LINK WITH ONE BLOCK PER LANE FIGURE 4-13: LAYOUT OF FRAMING TOKENS FIGURE 4-14: TLP AND DLLP LAYOUT FIGURE 4-15: PACKET TRANSMISSION IN A X8 LINK FIGURE 4-16: NULLIFIED TLP LAYOUT IN A X8 LINK WITH OTHER PACKETS FIGURE 4-17: SKP ORDERED SET OF LENGTH 66-BIT IN A X8 LINK FIGURE 4-18: LFSR WITH SCRAMBLING POLYNOMIAL IN 8.0 GT/S AND ABOVE DATA RATE FIGURE 4-19: ALTERNATE IMPLEMENTATION OF THE LFSR FOR DESCRAMBLING FIGURE 4-20: EQUALIZATION FLOW FIGURE 4-21: ELECTRICAL IDLE EXIT ORDERED SET FIGURE 4-22: MAIN STATE DIAGRAM FOR LINK TRAINING AND STATUS STATE MACHINE FIGURE 4-23: DETECT SUBSTATE MACHINE FIGURE 4-24: POLLING SUBSTATE MACHINE

14 FIGURE 4-25: CONFIGURATION SUBSTATE MACHINE FIGURE 4-26: RECOVERY SUBSTATE MACHINE FIGURE 4-27: L0S SUBSTATE MACHINE FIGURE 4-28: L1 SUBSTATE MACHINE FIGURE 4-29: L2 SUBSTATE MACHINE FIGURE 4-30: LOOPBACK SUBSTATE MACHINE FIGURE 4-31: TRANSMITTER, CHANNEL, AND RECEIVER BOUNDARIES FIGURE 4-32: REQUIRED SETUP FOR CHARACTERIZING A 5.0 GT/S TRANSMITTER FIGURE 4-33: ALLOWABLE SETUP FOR CHARACTERIZING A 2.5 GT/S TRANSMITTER FIGURE 4-34: TX TEST BOARD EXAMPLE FIGURE 4-35: SINGLE-ENDED AND DIFFERENTIAL LEVELS FIGURE 4-36: FULL SWING SIGNALING VOLTAGE PARAMETERS SHOWING -6 DB DE-EMPHASIS 330 FIGURE 4-37: REDUCED SWING TX PARAMETERS FIGURE 4-38: MINIMUM PULSE WIDTH DEFINITION FIGURE 4-39: FULL SWING TX PARAMETERS SHOWING DE-EMPHASIS FIGURE 4-40: MEASURING FULL SWING/DE-EMPHASIZED VOLTAGES FROM EYE DIAGRAM FIGURE 4-41: TX EQUALIZATION FIR REPRESENTATION FIGURE 4-42: DEFINITION OF TX VOLTAGE LEVELS AND EQUALIZATION RATIOS FIGURE 4-43: WAVEFORM MEASUREMENT POINTS FOR PRE-SHOOT AND DE-EMPHASIS FIGURE 4-44: V TX-FS-NO-EQ MEASUREMENT FIGURE 4-45: TXEQ COEFFICIENT SPACE TRIANGULAR MATRIX EXAMPLE FIGURE 4-46: MEASURING V TX-EIEOS-FS AND V TX-EIEOS-RS FIGURE 4-47: COMPLIANCE PATTERN AND RESULTING PACKAGE LOSS TEST WAVEFORM FIGURE 4-48: TRANSMITTER MARGINING VOLTAGE LEVELS AND CODES FIGURE 4-49: PLOT OF TRANSMITTER HPF FILTER FUNCTIONS FIGURE 4-50: ALGORITHM TO REMOVE DE-EMPHASIS INDUCED JITTER FIGURE 4-51: EXAMPLE OF DE-EMPHASIS JITTER REMOVAL FIGURE 4-52: RELATION BETWEEN DATA EDGE PDFS AND RECOVERED DATA CLOCK FIGURE 4-53: DERIVATION OF T TX-UTJ AND T TX-UDJDD FIGURE 4-54: PWJ RELATIVE TO CONSECUTIVE EDGES 1 UI APART FIGURE 4-55: DEFINITION OF T TX-UPW-DJDD AND T TX-UPW-TJ FIGURE 4-56: TX, RX DIFFERENTIAL RETURN LOSS MASK FIGURE 4-57: TX, RX COMMON MODE RETURN LOSS MASK FIGURE 4-58: CALIBRATION CHANNEL VALIDATION FIGURE 4-59: CALIBRATION CHANNEL SHOWING T MIN-PULSE FIGURE 4-60: CALIBRATION CHANNEL S 11 PLOT WITH TOLERANCE LIMITS FIGURE 4-61: SETUP FOR CALIBRATING RECEIVER TEST CIRCUIT INTO A REFERENCE LOAD FIGURE 4-62: SETUP FOR TESTING RECEIVER FIGURE 4-63: RECEIVER EYE MARGINS FIGURE 4-64: SIGNAL AT RECEIVER REFERENCE LOAD SHOWING MIN/MAX SWING FIGURE 4-65: RX TESTBOARD TOPOLOGY FIGURE 4-66: INSERTION LOSS GUIDELINES FOR CALIBRATION/BREAKOUT CHANNELS FIGURE 4-67: BEHAVIORAL CDR MODEL FOR RX MEASUREMENT FIGURE 4-68: TRANSFER FUNCTION FOR BEHAVIORAL CTLE FIGURE 4-69: LOSS CURVES FOR BEHAVIORAL CTLE FIGURE 4-70: EQUATION AND FLOW DIAGRAM FOR 1-TAP DFE

15 FIGURE 4-71: SETUP FOR CALIBRATING THE STRESSED VOLTAGE EYE FIGURE 4-72: LAYOUT FOR STRESSED VOLTAGE TESTING OF RECEIVER FIGURE 4-73: LAYOUT FOR CALIBRATING THE STRESSED JITTER EYE FIGURE 4-74: SWEPT SJ MASK FIGURE 4-75: LAYOUT FOR JITTER TESTING COMMON REFCLK RX FIGURE 4-76: LAYOUT FOR JITTER TESTING DATA CLOCKED REFCLK RX FIGURE 4-77: EXIT FROM IDLE VOLTAGE AND TIME MARGINS FIGURE 4-78: A 30 KHZ BEACON SIGNALING THROUGH A 75 NF CAPACITOR FIGURE 4-79: BEACON, WHICH INCLUDES A 2-NS PULSE THROUGH A 75 NF CAPACITOR FIGURE 4-80: SIMULATION ENVIRONMENT FOR CHARACTERIZING CHANNEL FIGURE 4-81: EXTRACTING EYE MARGINS FROM CHANNEL SIMULATION RESULTS FIGURE 4-82: MULTI-SEGMENT CHANNEL EXAMPLE FIGURE 4-83: FLOW DIAGRAM FOR CHANNEL TOLERANCING FIGURE 4-84: TX/RX BEHAVIORAL PACKAGE MODELS FIGURE 4-85: BEHAVIORAL TX AND RX S-PARAMETER FILE DETAILS FIGURE 4-86: DERIVATION OF JITTER PARAMETERS IN TABLE FIGURE 4-87: EH, EW MASK FIGURE 4-88: REFCLK TEST SETUP FIGURE 4-89: COMMON REFCLK RX ARCHITECTURE FIGURE 4-90: REFCLK TRANSPORT DELAY PATHS FOR A COMMON REFCLK RX ARCHITECTURE 403 FIGURE 4-91: DATA CLOCKED RX ARCHITECTURE FIGURE 4-92: SEPARATE REFCLK ARCHITECTURE FIGURE 4-93: 8.0 GT/S COMMON REFCLK RX ARCHITECTURE WITH ω N, ζ LIMITS FIGURE 4-94: 8.0 GT/S DATA CLOCKED RX ARCHITECTURE WITH ω N, ζ LIMITS FIGURE 5-1: LINK POWER MANAGEMENT STATE FLOW DIAGRAM FIGURE 5-2: ENTRY INTO THE L1 LINK STATE FIGURE 5-3: EXIT FROM L1 LINK STATE INITIATED BY UPSTREAM COMPONENT FIGURE 5-4: CONCEPTUAL DIAGRAMS SHOWING TWO EXAMPLE CASES OF WAKE# ROUTING. 431 FIGURE 5-5: A CONCEPTUAL PME CONTROL STATE MACHINE FIGURE 5-6: L1 TRANSITION SEQUENCE ENDING WITH A REJECTION (L0S ENABLED) FIGURE 5-7: L1 SUCCESSFUL TRANSITION SEQUENCE FIGURE 5-8: EXAMPLE OF L1 EXIT LATENCY COMPUTATION FIGURE 6-1: ERROR CLASSIFICATION FIGURE 6-2: FLOWCHART SHOWING SEQUENCE OF DEVICE ERROR SIGNALING AND LOGGING OPERATIONS FIGURE 6-3: PSEUDO LOGIC DIAGRAM FOR ERROR MESSAGE CONTROLS FIGURE 6-4: TC FILTERING EXAMPLE FIGURE 6-5: TC TO VC MAPPING EXAMPLE FIGURE 6-6: AN EXAMPLE OF TRAFFIC FLOW ILLUSTRATING INGRESS AND EGRESS FIGURE 6-7: AN EXAMPLE OF DIFFERENTIATED TRAFFIC FLOW THROUGH A SWITCH FIGURE 6-8: SWITCH ARBITRATION STRUCTURE FIGURE 6-9: VC ID AND PRIORITY ORDER AN EXAMPLE FIGURE 6-10: MULTI-FUNCTION ARBITRATION MODEL FIGURE 6-11: ROOT COMPLEX REPRESENTED AS A SINGLE COMPONENT FIGURE 6-12: ROOT COMPLEX REPRESENTED AS MULTIPLE COMPONENTS FIGURE 6-13: EXAMPLE SYSTEM TOPOLOGY WITH ARI DEVICES

16 FIGURE 6-14: SEGMENTATION OF THE MULTICAST ADDRESS RANGE FIGURE 6-15: LATENCY FIELDS FORMAT FOR LTR MESSAGES FIGURE 6-16: CLKREQ# AND CLOCK POWER MANAGEMENT FIGURE 6-17: USE OF LTR AND CLOCK POWER MANAGEMENT FIGURE 6-18: CODES AND EQUIVALENT WAKE# PATTERNS FIGURE 6-19: EXAMPLE PLATFORM TOPOLOGY SHOWING A LINK WHERE OBFF IS CARRIED BY MESSAGES FIGURE 7-1: PCI EXPRESS ROOT COMPLEX DEVICE MAPPING FIGURE 7-2: PCI EXPRESS SWITCH DEVICE MAPPING FIGURE 7-3: PCI EXPRESS CONFIGURATION SPACE LAYOUT FIGURE 7-4: COMMON CONFIGURATION SPACE HEADER FIGURE 7-5: TYPE 0 CONFIGURATION SPACE HEADER FIGURE 7-6: TYPE 1 CONFIGURATION SPACE HEADER FIGURE 7-7: POWER MANAGEMENT CAPABILITIES REGISTER FIGURE 7-8: POWER MANAGEMENT STATUS/CONTROL REGISTER FIGURE 7-9: VECTOR CONTROL FOR MSI-X TABLE ENTRIES FIGURE 7-10: PCI EXPRESS CAPABILITY STRUCTURE FIGURE 7-11: PCI EXPRESS CAPABILITY LIST REGISTER FIGURE 7-12: PCI EXPRESS CAPABILITIES REGISTER FIGURE 7-13: DEVICE CAPABILITIES REGISTER FIGURE 7-14: DEVICE CONTROL REGISTER FIGURE 7-15: DEVICE STATUS REGISTER FIGURE 7-16: LINK CAPABILITIES REGISTER FIGURE 7-17: LINK CONTROL REGISTER FIGURE 7-18: LINK STATUS REGISTER FIGURE 7-19: SLOT CAPABILITIES REGISTER FIGURE 7-20: SLOT CONTROL REGISTER FIGURE 7-21: SLOT STATUS REGISTER FIGURE 7-22: ROOT CONTROL REGISTER FIGURE 7-23: ROOT CAPABILITIES REGISTER FIGURE 7-24: ROOT STATUS REGISTER FIGURE 7-25: DEVICE CAPABILITIES 2 REGISTER FIGURE 7-26: DEVICE CONTROL 2 REGISTER FIGURE 7-27: LINK CAPABILITIES 2 REGISTER FIGURE 7-28: LINK CONTROL 2 REGISTER FIGURE 7-29: LINK STATUS 2 REGISTER FIGURE 7-30: PCI EXPRESS EXTENDED CONFIGURATION SPACE LAYOUT FIGURE 7-31: PCI EXPRESS EXTENDED CAPABILITY HEADER FIGURE 7-32: PCI EXPRESS ADVANCED ERROR REPORTING EXTENDED CAPABILITY STRUCTURE FIGURE 7-33: ADVANCED ERROR REPORTING EXTENDED CAPABILITY HEADER FIGURE 7-34: UNCORRECTABLE ERROR STATUS REGISTER FIGURE 7-35: UNCORRECTABLE ERROR MASK REGISTER FIGURE 7-36: UNCORRECTABLE ERROR SEVERITY REGISTER FIGURE 7-37: CORRECTABLE ERROR STATUS REGISTER FIGURE 7-38: CORRECTABLE ERROR MASK REGISTER

17 FIGURE 7-39: ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER FIGURE 7-40: HEADER LOG REGISTER FIGURE 7-41: ROOT ERROR COMMAND REGISTER FIGURE 7-42: ROOT ERROR STATUS REGISTER FIGURE 7-43: ERROR SOURCE IDENTIFICATION REGISTER FIGURE 7-44: TLP PREFIX LOG REGISTER FIGURE 7-45: PCI EXPRESS VIRTUAL CHANNEL CAPABILITY STRUCTURE FIGURE 7-46: VIRTUAL CHANNEL EXTENDED CAPABILITY HEADER FIGURE 7-47: PORT VC CAPABILITY REGISTER FIGURE 7-48: PORT VC CAPABILITY REGISTER FIGURE 7-49: PORT VC CONTROL REGISTER FIGURE 7-50: PORT VC STATUS REGISTER FIGURE 7-51: VC RESOURCE CAPABILITY REGISTER FIGURE 7-52: VC RESOURCE CONTROL REGISTER FIGURE 7-53: VC RESOURCE STATUS REGISTER FIGURE 7-54: EXAMPLE VC ARBITRATION TABLE WITH 32 PHASES FIGURE 7-55: EXAMPLE PORT ARBITRATION TABLE WITH 128 PHASES AND 2-BIT TABLE ENTRIES FIGURE 7-56: PCI EXPRESS DEVICE SERIAL NUMBER CAPABILITY STRUCTURE FIGURE 7-57: DEVICE SERIAL NUMBER EXTENDED CAPABILITY HEADER FIGURE 7-58: SERIAL NUMBER REGISTER FIGURE 7-59: PCI EXPRESS ROOT COMPLEX LINK DECLARATION CAPABILITY FIGURE 7-60: ROOT COMPLEX LINK DECLARATION EXTENDED CAPABILITY HEADER FIGURE 7-61: ELEMENT SELF DESCRIPTION REGISTER FIGURE 7-62: LINK ENTRY FIGURE 7-63: LINK DESCRIPTION REGISTER FIGURE 7-64: LINK ADDRESS FOR LINK TYPE FIGURE 7-65: LINK ADDRESS FOR LINK TYPE FIGURE 7-66: ROOT COMPLEX INTERNAL LINK CONTROL CAPABILITY FIGURE 7-67: ROOT INTERNAL LINK CONTROL EXTENDED CAPABILITY HEADER FIGURE 7-68: ROOT COMPLEX LINK CAPABILITIES REGISTER FIGURE 7-69: ROOT COMPLEX LINK CONTROL REGISTER FIGURE 7-70: ROOT COMPLEX LINK STATUS REGISTER FIGURE 7-71: PCI EXPRESS POWER BUDGETING CAPABILITY STRUCTURE FIGURE 7-72: POWER BUDGETING EXTENDED CAPABILITY HEADER FIGURE 7-73: POWER BUDGETING DATA REGISTER FIGURE 7-74: POWER BUDGET CAPABILITY REGISTER FIGURE 7-75: ACS EXTENDED CAPABILITY FIGURE 7-76: ACS EXTENDED CAPABILITY HEADER FIGURE 7-77: ACS CAPABILITY REGISTER FIGURE 7-78: ACS CONTROL REGISTER FIGURE 7-79: EGRESS CONTROL VECTOR REGISTER FIGURE 7-80: ROOT COMPLEX EVENT COLLECTOR ENDPOINT ASSOCIATION CAPABILITY FIGURE 7-81: ROOT COMPLEX EVENT COLLECTOR ENDPOINT ASSOCIATION EXTENDED CAPABILITY HEADER FIGURE 7-82: PCI EXPRESS MFVC CAPABILITY STRUCTURE

18 FIGURE 7-83: MFVC EXTENDED CAPABILITY HEADER FIGURE 7-84: PORT VC CAPABILITY REGISTER FIGURE 7-85: PORT VC CAPABILITY REGISTER FIGURE 7-86: PORT VC CONTROL REGISTER FIGURE 7-87: PORT VC STATUS REGISTER FIGURE 7-88: VC RESOURCE CAPABILITY REGISTER FIGURE 7-89: VC RESOURCE CONTROL REGISTER FIGURE 7-90: VC RESOURCE STATUS REGISTER FIGURE 7-91: PCI EXPRESS VSEC STRUCTURE FIGURE 7-92: VENDOR-SPECIFIC EXTENDED CAPABILITY HEADER FIGURE 7-93: VENDOR-SPECIFIC HEADER FIGURE 7-94: ROOT COMPLEX FEATURES CAPABILITY STRUCTURE FIGURE 7-95: RCRB HEADER EXTENDED CAPABILITY HEADER FIGURE 7-96: VENDOR ID AND DEVICE ID FIGURE 7-97: RCRB CAPABILITIES FIGURE 7-98: RCRB CONTROL FIGURE 7-99: MULTICAST EXTENDED CAPABILITY STRUCTURE FIGURE 7-100: MULTICAST EXTENDED CAPABILITY HEADER FIGURE 7-101: MULTICAST CAPABILITY REGISTER FIGURE 7-102: MULTICAST CONTROL REGISTER FIGURE 7-103: MC_BASE_ADDRESS REGISTER FIGURE 7-104: MC_RECEIVE REGISTER FIGURE 7-105: MC_BLOCK_ALL REGISTER FIGURE 7-106: MC_BLOCK_UNTRANSLATED REGISTER FIGURE 7-107: MC_OVERLAY_BAR FIGURE 7-108: RESIZABLE BAR CAPABILITY FIGURE 7-109: RESIZABLE BAR EXTENDED CAPABILITY HEADER FIGURE 7-110: RESIZABLE BAR CAPABILITY REGISTER FIGURE 7-111: RESIZABLE BAR CONTROL REGISTER FIGURE 7-112: ARI CAPABILITY FIGURE 7-113: ARI CAPABILITY HEADER FIGURE 7-114: ARI CAPABILITY REGISTER FIGURE 7-115: ARI CONTROL REGISTER FIGURE 7-116: DYNAMIC POWER ALLOCATION CAPABILITY STRUCTURE FIGURE 7-117: DPA EXTENDED CAPABILITY HEADER FIGURE 7-118: DPA CAPABILITY REGISTER FIGURE 7-119: DPA LATENCY INDICATOR REGISTER FIGURE 7-120: DPA STATUS REGISTER FIGURE 7-121: DPA CONTROL REGISTER FIGURE 7-122: DPA POWER ALLOCATION ARRAY FIGURE 7-123: LTR EXTENDED CAPABILITY STRUCTURE FIGURE 7-124: LTR EXTENDED CAPABILITY HEADER FIGURE 7-125: MAX SNOOP LATENCY REGISTER FIGURE 7-126: MAX NO-SNOOP LATENCY REGISTER FIGURE 7-127: TPH EXTENDED CAPABILITY STRUCTURE FIGURE 7-128: TPH REQUESTER EXTENDED CAPABILITY HEADER

19 FIGURE 7-129: TPH REQUESTER CAPABILITY REGISTER FIGURE 7-130: TPH REQUESTER CONTROL REGISTER FIGURE 7-131: TPH ST TABLE FIGURE 7-132: SECONDARY PCI EXPRESS EXTENDED CAPABILITY STRUCTURE FIGURE 7-133: SECONDARY PCI EXPRESS EXTENDED CAPABILITY HEADER FIGURE 7-134: LINK CONTROL 3 REGISTER FIGURE 7-135: LANE ERROR STATUS REGISTER FIGURE 7-136: LANE EQUALIZATION CONTROL REGISTER FIGURE 7-137: LANE ((MAXIMUM LINK WIDTH 1):0) EQUALIZATION CONTROL REGISTER FIGURE A-1: AN EXAMPLE SHOWING ENDPOINT-TO-ROOT-COMPLEX AND PEER-TO-PEER COMMUNICATION MODELS FIGURE A-2: TWO BASIC BANDWIDTH RESOURCING PROBLEMS: OVER-SUBSCRIPTION AND CONGESTION FIGURE A-3: A SIMPLIFIED EXAMPLE ILLUSTRATING PCI EXPRESS ISOCHRONOUS PARAMETERS FIGURE C-1: SCRAMBLING SPECTRUM AT 2.5 GT/S FOR DATA VALUE OF FIGURE E-1: REFERENCE TOPOLOGY FOR IDO USE FIGURE G-1: DEVICE AND PROCESSOR CONNECTED USING A PMUX LINK FIGURE G-2: PMUX LINK FIGURE G-3: PMUX PACKET FLOW THROUGH THE LAYERS FIGURE G-4: PMUX PACKET FIGURE G-5: TLP AND PMUX PACKET FRAMING (8B10B ENCODING) FIGURE G-6: TLP AND PMUX PACKET FRAMING (128B/130B ENCODING) FIGURE G-7: PMUX EXTENDED CAPABILITY FIGURE G-8: PMUX EXTENDED CAPABILITY HEADER FIGURE G-9: PMUX CAPABILITY REGISTER FIGURE G-10: PMUX CONTROL REGISTER FIGURE G-11: PMUX STATUS REGISTER FIGURE G-12: PMUX PROTOCOL ARRAY ENTRY

20 Tables TABLE 2-1: TRANSACTION TYPES FOR DIFFERENT ADDRESS SPACES TABLE 2-2: FMT[2:0] FIELD VALUES TABLE 2-3: FMT[2:0] AND TYPE[4:0] FIELD ENCODINGS TABLE 2-4: LENGTH[9:0] FIELD ENCODING TABLE 2-5: ADDRESS TYPE (AT) FIELD ENCODINGS TABLE 2-6: ADDRESS FIELD MAPPING TABLE 2-7: HEADER FIELD LOCATIONS FOR NON-ARI ID ROUTING TABLE 2-8: HEADER FIELD LOCATIONS FOR ARI ID ROUTING TABLE 2-9: BYTE ENABLES LOCATION AND CORRESPONDENCE TABLE 2-10: ORDERING ATTRIBUTES TABLE 2-11: CACHE COHERENCY MANAGEMENT ATTRIBUTE TABLE 2-12: DEFINITION OF TC FIELD ENCODINGS TABLE 2-13: LENGTH FIELD VALUES FOR ATOMICOP REQUESTS TABLE 2-14: TPH TLP PREFIX BIT MAPPING TABLE 2-15: LOCATION OF PH[1:0] IN TLP HEADER TABLE 2-16: PROCESSING HINT ENCODING TABLE 2-17: LOCATION OF ST[7:0] IN TLP HEADERS TABLE 2-18: MESSAGE ROUTING TABLE 2-19: INTX MECHANISM MESSAGES TABLE 2-20: BRIDGE MAPPING FOR INTX VIRTUAL WIRES TABLE 2-21: POWER MANAGEMENT MESSAGES TABLE 2-22: ERROR SIGNALING MESSAGES TABLE 2-23: UNLOCK MESSAGE TABLE 2-24: SET_SLOT_POWER_LIMIT MESSAGE TABLE 2-25: VENDOR_DEFINED MESSAGES TABLE 2-26: IGNORED MESSAGES TABLE 2-27: LTR MESSAGE TABLE 2-28: OBFF MESSAGE TABLE 2-29: COMPLETION STATUS FIELD VALUES TABLE 2-30: LOCAL TLP PREFIX TYPES TABLE 2-31: END-END TLP PREFIX TYPES TABLE 2-32: CALCULATING BYTE COUNT FROM LENGTH AND BYTE ENABLES TABLE 2-33: CALCULATING LOWER ADDRESS FROM 1 ST DW BE TABLE 2-34: ORDERING RULES SUMMARY TABLE 2-35: TC TO VC MAPPING EXAMPLE TABLE 2-36: FLOW CONTROL CREDIT TYPES TABLE 2-37: TLP FLOW CONTROL CREDIT CONSUMPTION TABLE 2-38: MINIMUM INITIAL FLOW CONTROL ADVERTISEMENTS TABLE 2-39: UPDATEFC TRANSMISSION LATENCY GUIDELINES FOR 2.5 GT/S MODE OPERATION BY LINK WIDTH AND MAX PAYLOAD (SYMBOL TIMES) TABLE 2-40: UPDATEFC TRANSMISSION LATENCY GUIDELINES FOR 5.0 GT/S MODE OPERATION BY LINK WIDTH AND MAX PAYLOAD (SYMBOL TIMES)

21 TABLE 2-41: UPDATEFC TRANSMISSION LATENCY GUIDELINES FOR 8.0 GT/S OPERATION BY LINK WIDTH AND MAX PAYLOAD (SYMBOL TIMES) TABLE 2-42: MAPPING OF BITS INTO ECRC FIELD TABLE 3-1: DLLP TYPE ENCODINGS TABLE 3-2: MAPPING OF BITS INTO CRC FIELD TABLE 3-3: MAPPING OF BITS INTO LCRC FIELD TABLE 3-4: UNADJUSTED REPLAY_TIMER LIMITS FOR 2.5 GT/S MODE OPERATION BY LINK WIDTH AND MAX_PAYLOAD_SIZE (SYMBOL TIMES) TOLERANCE: -0%/+100% TABLE 3-5: UNADJUSTED REPLAY_TIMER LIMITS FOR 5.0 GT/S MODE OPERATION BY LINK WIDTH AND MAX_PAYLOAD_SIZE (SYMBOL TIMES) TOLERANCE: -0%/+100% TABLE 3-6: UNADJUSTED REPLAY_TIMER LIMITS FOR 8.0 GT/S OPERATION BY LINK WIDTH AND MAX_PAYLOAD_SIZE (SYMBOL TIMES) TOLERANCE: -0%/+100% TABLE 3-7: ACK TRANSMISSION LATENCY LIMIT AND ACKFACTOR FOR 2.5 GT/S MODE OPERATION BY LINK WIDTH AND MAX PAYLOAD (SYMBOL TIMES) TABLE 3-8: ACK TRANSMISSION LATENCY LIMIT AND ACKFACTOR FOR 5.0 GT/S MODE OPERATION BY LINK WIDTH AND MAX PAYLOAD (SYMBOL TIMES) TABLE 3-9: ACK TRANSMISSION LATENCY LIMIT AND ACKFACTOR FOR 8.0 GT/S MODE OPERATION BY LINK WIDTH AND MAX PAYLOAD (SYMBOL TIMES) TABLE 4-1: SPECIAL SYMBOLS TABLE 4-2: FRAMING TOKEN ENCODING TABLE 4-3: TRANSMITTER PRESET ENCODING TABLE 4-4: RECEIVER PRESET HINT ENCODING TABLE 4-5: TS1 ORDERED SET TABLE 4-6: TS2 ORDERED SET TABLE 4-7: ELECTRICAL IDLE ORDERED SET (EIOS) FOR 2.5 GT/S AND 5.0 GT/S DATA RATES 233 TABLE 4-8: ELECTRICAL IDLE ORDERED SET (EIOS) FOR 8.0 GT/S AND ABOVE DATA RATES TABLE 4-9: ELECTRICAL IDLE EXIT ORDERED SET (EIEOS) FOR 5.0 GT/S DATA RATE TABLE 4-10: ELECTRICAL IDLE EXIT ORDERED SET (EIEOS) FOR 8.0 GT/S AND ABOVE DATA RATES TABLE 4-11: ELECTRICAL IDLE INFERENCE CONDITIONS TABLE 4-12: FTS FOR 8.0 GT/S AND ABOVE DATA RATES TABLE 4-13: SDS ORDERED SET (FOR 8.0 GT/S AND ABOVE DATA RATE) TABLE 4-14: LINK STATUS MAPPED TO THE LTSSM TABLE 4-15: SKP ORDERED SET WITH 128B/130B ENCODING TABLE 4-16: TX PRESET RATIOS AND CORRESPONDING COEFFICIENT VALUES TABLE 4-17: PRESET MEASUREMENT CROSS REFERENCE TABLE TABLE 4-18: TRANSMITTER SPECIFICATIONS TABLE 4-19: 8.0 GT/S SPECIFIC TX VOLTAGE AND JITTER PARAMETERS TABLE 4-20: 5.0 GT/S TOLERANCING LIMITS FOR COMMON REFCLK RX ARCHITECTURE TABLE 4-21: 5.0 GT/S TOLERANCING LIMITS FOR DATA CLOCKED RX ARCHITECTURE TABLE 4-22: STRESSED VOLTAGE EYE PARAMETERS TABLE 4-23: STRESSED JITTER EYE PARAMETERS TABLE 4-24: RECEIVER SPECIFICATIONS TABLE 4-25: WORST CASE TX CORNERS FOR 5.0 GT/S CHANNEL SIMULATION TABLE 4-26: JITTER/VOLTAGE PARAMETERS FOR CHANNEL TOLERANCING TABLE 4-27: CHANNEL TOLERANCING EYE MASK VALUES

22 TABLE 4-28: EIEOS SIGNALING PARAMETERS TABLE 4-29: FILTERING FUNCTIONS APPLIED TO REFCLK MEASUREMENTS TABLE 4-30: DIFFERENCE FUNCTION PARAMETERS APPLIED TO REFCLK MEASUREMENT TABLE 4-31: REFCLK PARAMETERS FOR COMMON REFCLK RX ARCHITECTURE AT 5.0 GT/S TABLE 4-32: PLL PARAMETERS FOR DATA CLOCKED RX ARCHITECTURE TABLE 4-33: REFCLK PARAMETERS FOR DATA CLOCKED RX ARCHITECTURE TABLE 4-34: PARAMETERS FOR COMMON REFCLK RX ARCHITECTURE AT 8.0 GT/S TABLE 4-35: PARAMETERS FOR DATA CLOCKED RX ARCHITECTURE AT 8.0 GT/S TABLE 5-1: SUMMARY OF PCI EXPRESS LINK POWER MANAGEMENT STATES TABLE 5-2: RELATION BETWEEN POWER MANAGEMENT STATES OF LINK AND COMPONENTS TABLE 5-3: ENCODING OF THE ASPM SUPPORT FIELD TABLE 5-4: DESCRIPTION OF THE SLOT CLOCK CONFIGURATION BIT TABLE 5-5: DESCRIPTION OF THE COMMON CLOCK CONFIGURATION BIT TABLE 5-6: ENCODING OF THE L0S EXIT LATENCY FIELD TABLE 5-7: ENCODING OF THE L1 EXIT LATENCY FIELD TABLE 5-8: ENCODING OF THE ENDPOINT L0S ACCEPTABLE LATENCY FIELD TABLE 5-9: ENCODING OF THE ENDPOINT L1 ACCEPTABLE LATENCY FIELD TABLE 5-10: ENCODING OF THE ASPM CONTROL FIELD TABLE 5-11: POWER MANAGEMENT SYSTEM MESSAGES AND DLLPS TABLE 6-1: ERROR MESSAGES TABLE 6-2: GENERAL PCI EXPRESS ERROR LIST TABLE 6-3: PHYSICAL LAYER ERROR LIST TABLE 6-4: DATA LINK LAYER ERROR LIST TABLE 6-5: TRANSACTION LAYER ERROR LIST TABLE 6-6: ELEMENTS OF HOT-PLUG TABLE 6-7: ATTENTION INDICATOR STATES TABLE 6-8: POWER INDICATOR STATES TABLE 6-9: ACS P2P REQUEST REDIRECT AND ACS P2P EGRESS CONTROL INTERACTIONS TABLE 6-10: ECRC RULES FOR MC_OVERLAY TABLE 6-11: PROCESSING HINT MAPPING TABLE 6-12: ST MODES OF OPERATION TABLE 7-1: ENHANCED CONFIGURATION ADDRESS MAPPING TABLE 7-2: REGISTER AND REGISTER BIT-FIELD TYPES TABLE 7-3: COMMAND REGISTER TABLE 7-4: STATUS REGISTER TABLE 7-5: SECONDARY STATUS REGISTER TABLE 7-6: BRIDGE CONTROL REGISTER TABLE 7-7: POWER MANAGEMENT CAPABILITIES REGISTER ADDED REQUIREMENTS TABLE 7-8: POWER MANAGEMENT STATUS/CONTROL REGISTER ADDED REQUIREMENTS TABLE 7-9: VECTOR CONTROL FOR MSI-X TABLE ENTRIES TABLE 7-10: PCI EXPRESS CAPABILITY LIST REGISTER TABLE 7-11: PCI EXPRESS CAPABILITIES REGISTER TABLE 7-12: DEVICE CAPABILITIES REGISTER TABLE 7-13: DEVICE CONTROL REGISTER TABLE 7-14: DEVICE STATUS REGISTER TABLE 7-15: LINK CAPABILITIES REGISTER

23 TABLE 7-16: LINK CONTROL REGISTER TABLE 7-17: LINK STATUS REGISTER TABLE 7-18: SLOT CAPABILITIES REGISTER TABLE 7-19: SLOT CONTROL REGISTER TABLE 7-20: SLOT STATUS REGISTER TABLE 7-21: ROOT CONTROL REGISTER TABLE 7-22: ROOT CAPABILITIES REGISTER TABLE 7-23: ROOT STATUS REGISTER TABLE 7-24: DEVICE CAPABILITIES 2 REGISTER TABLE 7-25: DEVICE CONTROL 2 REGISTER TABLE 7-26: LINK CAPABILITIES 2 REGISTER TABLE 7-27: LINK CONTROL 2 REGISTER TABLE 7-28: LINK STATUS 2 REGISTER TABLE 7-29: PCI EXPRESS EXTENDED CAPABILITY HEADER TABLE 7-30: ADVANCED ERROR REPORTING EXTENDED CAPABILITY HEADER TABLE 7-31: UNCORRECTABLE ERROR STATUS REGISTER TABLE 7-32: UNCORRECTABLE ERROR MASK REGISTER TABLE 7-33: UNCORRECTABLE ERROR SEVERITY REGISTER TABLE 7-34: CORRECTABLE ERROR STATUS REGISTER TABLE 7-35: CORRECTABLE ERROR MASK REGISTER TABLE 7-36: ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER TABLE 7-37: HEADER LOG REGISTER TABLE 7-38: ROOT ERROR COMMAND REGISTER TABLE 7-39: ROOT ERROR STATUS REGISTER TABLE 7-40: ERROR SOURCE IDENTIFICATION REGISTER TABLE 7-41: TLP PREFIX LOG REGISTER TABLE 7-42: VIRTUAL CHANNEL EXTENDED CAPABILITY HEADER TABLE 7-43: PORT VC CAPABILITY REGISTER TABLE 7-44: PORT VC CAPABILITY REGISTER TABLE 7-45: PORT VC CONTROL REGISTER TABLE 7-46: PORT VC STATUS REGISTER TABLE 7-47: VC RESOURCE CAPABILITY REGISTER TABLE 7-48: VC RESOURCE CONTROL REGISTER TABLE 7-49: VC RESOURCE STATUS REGISTER TABLE 7-50: DEFINITION OF THE 4-BIT ENTRIES IN THE VC ARBITRATION TABLE TABLE 7-51: LENGTH OF THE VC ARBITRATION TABLE TABLE 7-52: LENGTH OF PORT ARBITRATION TABLE TABLE 7-53: DEVICE SERIAL NUMBER EXTENDED CAPABILITY HEADER TABLE 7-54: SERIAL NUMBER REGISTER TABLE 7-55: ROOT COMPLEX LINK DECLARATION EXTENDED CAPABILITY HEADER TABLE 7-56: ELEMENT SELF DESCRIPTION REGISTER TABLE 7-57: LINK DESCRIPTION REGISTER TABLE 7-58: LINK ADDRESS FOR LINK TYPE TABLE 7-59: ROOT COMPLEX INTERNAL LINK CONTROL EXTENDED CAPABILITY HEADER TABLE 7-60: ROOT COMPLEX LINK CAPABILITIES REGISTER TABLE 7-61: ROOT COMPLEX LINK CONTROL REGISTER