Product Specifications

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1 PART NO: VL47B5263ZR9S/R8S/R7SHS REV: 1.0 General Information 4GB 512MX64 DDR3 UNBUFFERED 204 PIN SODIMM HEAT SPREADER AND CONFORMAL COATING Description: The VL47B5263Z is a 512M X 64 DDR3 SDRAM high density SODIMM. This memory module consists of sixteen CMOS 256Mx8 bit with 8 banks DDR3 Synchronous DRAMs in BGA packages and a 2K EEPROM with Thermal Sensor in an 8pin MLF package. This module is a 204pin smalloutline dual inline memory module and is intended for mounting into a connector socket. Decoupling capacitors are mounted on the printed circuit board for each DDR3 SDRAM. Features: Pin Name Function. 204pin, smalloutline dual inline memory module (SODIMM). Fast data transfer rates: PC310600, PC38500, or PC VDD = VD = 1.5V +/ 0.075V. VDDSPD = 3V to 3.6V. JEDEC standard 1.5V +/ 0.075V I/O (SSTL_15 compatible). 8 Banks. 8bit prefetch architecture. Bidirectional Differential DataStrobe. Programmable CAS# Latency: 6, 7, 9. Programmable burst; length (8). Ondie termination (ODT). Average refresh period 7.8 us. Asynchronous Reset. Flyby topology. Terminated command, address, and control bus. Gold edge PCB contacts. Leadfree, RoHS compliant. Serial presence detect (SPD) with EEPROM with Thermal Sensor,. Thermal sensor range: 20 0 C to C (+/ 1 0 C Accuracy). JEDEC pin out. PCB: Height 30mm (1.181 ), double sided components. Conformal coating MILI46058C. Operating temperature (TOPER): 40 0 C to C Order Information: VL47B5263ZR9 S XHS HS: Heat Sink DRAM DIE (option) DRAM MANUFACTURER S SAMSUNG MODULE SPEED R9: CL9 R8: CL7 R7: CL6 (R: Screening grade) Z: Conformal coating VL: Leadfree/RoHS A0~A14 A10/AP BA0~BA2 0~63 S0~S7 S0#~S7# ODT0, ODT1 CK0,CK0# ~ CK1,CK1# CKE0, CKE1 CS0#, CS1# RAS# CAS# WE# Address Inputs Address Input/Autoprecharge Bank Address Inputs Data Input/Output Data Strobes Data Strobes Complement Ondie Termination Control Clock Input Clock Enables Chip Selects Row Address Strobes Column Address Strobes Write Enable VDD Voltage Supply 1.5V +/ 0.075V VSS SA0~SA1 SDA SCL DM0~DM7 VREFCA VREF Ground SPD Address SPD Data Input/Output SPD Clock Input Data Masks Reference Voltage for CA Reference Voltage for VDDSPD SPD Voltage Supply 3V to 3.6V VTT RESET# EVENT# NC Termination Voltage Register and SDRAM Control Reserved for Temp Sensing No Connect Tel: Fax: PAGE 1 OF 12

2 PART NO: VL47B5263ZR9S/R8S/R7SHS REV: 1.0 Pin Configuration 204PIN DDR3 SODIMM FRONT 204PIN DDR3 SODIMM BACK Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name 1 VREF VDD VSS 54 VSS 106 VDD VSS 55 VSS 107 A BA BA0 161 VSS RAS# 162 VSS VDD VSS 60 VSS 112 VDD VSS 61 VSS 113 WE# S0# 62 S3# 114 CS0# DM0 63 DM3 115 CAS# 167 VSS 12 S0 64 S3 116 ODT0 168 VSS 13 VSS 65 VSS 117 VDD 169 S6# 14 VSS 66 VSS 118 VDD 170 DM A S ODT1 172 VSS CS1# 173 VSS NC VSS 71 VSS 123 VDD VSS 72 VSS 124 VDD CKE0 125 NC CKE1 126 VREFCA 178 VSS VDD 127 VSS 179 VSS VDD 128 VSS VSS 77 NC VSS 78 NC S1# 79 BA DM1 80 A VSS 29 S1 81 VDD 133 VSS 185 VSS 30 RESET# 82 VDD 134 VSS 186 S7# 31 VSS 83 A S4# 187 DM7 32 VSS 84 A DM4 188 S A9 137 S4 189 VSS A7 138 VSS 190 VSS VDD 139 VSS VDD VSS 89 A VSS 90 A A VSS A4 144 VSS 196 VSS VDD 145 VSS 197 SA VDD EVENT# 43 VSS 95 A VDDSPD 44 VSS 96 A SDA 45 S2# 97 A SA1 46 DM2 98 A0 150 VSS 202 SCL 47 S2 99 VDD 151 VSS 203 VTT 48 VSS 100 VDD 152 S5# 204 VTT 49 VSS 101 CK0 153 DM CK1 154 S CK0# 155 VSS CK1# 156 VSS Notes: 1. Pin 80 is NC for 1GB and A14 for 2GB component. Tel: Fax: PAGE 2 OF 12

3 PART NO: VL47B5263ZR9S/R8S/R7SHS REV: 1.0 Functional Block Diagram CS1# CS0# S0# S0 DM S1# S1 DM S2# S2 DM S3# S3 DM DM CS# S D0 DM CS# S D1 DM CS# S D2 DM CS# S D3 S# S# S# S# DM CS# S D8 DM CS# S D9 DM CS# S D10 DM CS# S D11 S# S# S# S# S4# S4 DM S5# S5 DM S6# S6 DM S7# S7 DM DM CS# S D4 DM CS# S D5 DM CS# S D6 DM CS# S D7 S# S# S# S# DM CS# S D12 DM CS# S D13 DM CS# S D14 DM CS# S D15 S# S# S# S# A0A14 BA0BA2 RAS# CAS# WE# CKE0 CKE1 ODT0 ODT1 RESET# A0A14: D0D15 BA0BA2: D0D15 RAS#: D0D15 CAS#: D0D15 WE#: D0D15 CKE0: D0D7 CKE1: D8D15 ODT0: D0D7 ODT1: D8D15 RESET#: D0D15 Integrated Thermal Sensor in SPD SCL EVENT# EVENT# A0 A1 A2 SA0 SA1 SDA Serial PD with Integrated thermal sensor CK0 CK0# CK1 CK1# 3.3pF 3.3pF D0D7 D8D15 VDDSPD Serial PD Command, address, control, and clock line terminations A0A14, BA0BA2 RAS#, CAS#, WE#, CS0#, CS1#, CKE0, CKE1, ODT0, ODT1 CK0, CK1 CK0#, CK1# DDR3 SDRAM DDR3 SDRAM 36 ohms +/ 5% VTT 30 ohms +/ 5% VDD 0.1uF VDD VTT VREFCA VREF VSS D0D15 D0D15 D0D15 D0D15 D0D15 Notes: 1. Unless otherwise noted, resistor values are 15 Ohms +/ 5% 2. resistors are 240 Ohms +/ 1% Tel: Fax: PAGE 3 OF 12

4 PART NO: VL47B5263ZR9S/R8S/R7SHS REV: 1.0 Absolute Maximum Ratings Symbol Parameter MIN MAX Unit VDD Voltage on VDD pin relative to VSS V VD Voltage on VD pin relative to VSS V VIN, VOUT Voltage on any pin relative to VSS V TSTG Storage temperature Command/Address, RAS#, CAS#, WE#, BA ua Input leakage current; Any input IL 0V<VIN<VDD; VREF input 0V<VIN<0.95V; CS#, CKE, ODT ua Other pins not under test = 0V CK, CK# ua DM 4 4 ua 0 C IOZ Output leakage current; 0V<VOUT<VD; s and ODT are disabled, S, S# ua IVREF VREF leakage current; VREF = Valid VREF level ua DC Operating Conditions Parameter Symbol Min Typical Max Unit Notes Supply Voltage VDD V 1,2 Supply Voltage for Output VD V 1,2 I/O Reference voltage () VREF (DC) 0.49 x VD 0.5 x VDD 0.51 x VD V 3,4 I/O Reference voltage (CMD/ADD) VREFCA (DC) 0.49 x VD 0.5 x VDD 0.51 x VD V 3,4 Termination Reference Voltage VTT x VDD 0.5 x VDD x VDD V 5 Notes: 1. Under all conditions VD must be less than or equal to VDD. 2. VD tracks with VDD. AC parameters are measured with VDD and VD tied together. 3. The ac peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than +/ 1% VDD. 4. For reference: approximate VDD/2 +/ 15mV. 5. VTT termination voltage in excess of stated limit will adversely affect the command and address signals' voltage margin and will reduce timing margins. Operating Temperature Condition Parameter Symbol Rating Units Notes Operating temperature TOPER 40 to + 85 Notes: 0 C 1 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD52 Tel: Fax: PAGE 4 OF 12

5 PART NO: VL47B5263ZR9S/R8S/R7SHS REV: 1.0 Input DC Logic Level All voltages referenced to VSS Parameter Symbol Min Max Unit Command and Address Input High (Logic 1) Voltage DDR3800/1066/1333 VIHCA(DC) VREF VDD V Input Low (Logic 0) Voltage DDR3800/1066/1333 VILCA(DC) VSS VREF V and DM Input High (Logic 1) Voltage DDR3800/1066/1333 VIHCA(DC) VREF VDD V Input Low (Logic 0) Voltage DDR3800/1066/1333 VILCA(DC) VSS VREF V Input AC Logic Level All voltages referenced to VSS Parameter Symbol Min Max Unit Command and Address AC Input High (Logic 1) Voltage DDR3800/1066/1333 VIHCA(AC) VREF V AC Input Low (Logic 0) Voltage DDR3800/1066/1333 VILCA(AC) VREF V and DM AC Input High (Logic 1) Voltage DDR3800/1066 VIHCA(AC) VREF V AC Input Low (Logic 0) Voltage DDR3800/1066 VILCA(AC) VREF V AC Input High (Logic 1) Voltage DDR31333 VIHCA(AC) VREF V AC Input Low (Logic 0) Voltage DDR31333 VILCA(AC) VREF V Parameter Input/Output Capacitance TA=25 0 C, f=100mhz Symbol DDR3800/1066 DDR31333 Min Max Min Max Unit Input capacitance (A0~A14, BA0~BA2, RAS#, CAS#, WE#) CIN pf Input capacitance (CKE0, CKE1), (ODT0, ODT1), (CS0#, CS1#) CIN pf Input capacitance (CK0, CK0# ~ CK1, CK1#) CIN pf Input/Output capacitance (DM0~DM7), (0~63), (S0~S7) CIO 7 10/ pf Input/Output capacitance of pin C pf Tel: Fax: PAGE 5 OF 12

6 PART NO: VL47B5263ZR9S/R8S/R7SHS REV: 1.0 Condition IDD Specification Operating one bank activeprecharge current; tck= tck(idd); trc= trc(idd); tras= tras MIN(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating one bank activereadprecharge current; IOUT = 0mA; BL = 8; CL = CL(IDD); AL = 0; tck= tck(idd); trc= trc(idd); tras= tras MIN(IDD); trcd= trcd(idd); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W. Precharge powerdown current; Symbol DDR31333 DDR31066 DDR3800 R9 R8 R7 Unit IDD0* ma IDD1* ma IDD2PF** ma All banks idle; tck= tck(idd); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING IDD2PS** ma Precharge standby current; All banks idle; tck= tck(idd); CKE is HIGH; CS# is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Precharge quiet standby current; All banks idle; tck= tck(idd); CKE is HIGH; CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Active powerdown current; All banks open; tck= tck(idd); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. Active standby current; All banks open; tck= tck(idd); trp= trp(idd); tras= tras MAX(IDD)); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Operating burst read current; All banks open; Continuous burst reads; IOUT = 0mA; BL = 8; CL = CL(IDD); AL = 0; tck= tck(idd); tras= tras MAX(IDD); trp= trp(idd); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W. Operating burst write current; All banks open; Continuous burst writes; BL = 8; CL = CL(IDD); AL = 0; tck= tck(idd); tras= tras MAX(IDD); trp= trp(idd); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Burst refresh current; tck=tck(idd); Refresh command at every trfc(idd) interval; CKE is HIGH; CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Self refresh current; CK and CK# at 0V; CKE < 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING. Operating bank interleave read current; All bank interleaving reads; IOUT = 0mA; BL = 8; CL = CL(IDD); AL = trcd(idd) 1*tCK(IDD); tck= tck(idd); trc= trc(idd); trrd = trrd(idd); trcd = 1*tCK(IDD) ; CKE is HIGH; CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R. IDD2N** ma IDD2Q** ma IDD3P** ma IDD3N** ma IDD4R* ma IDD4W* ma IDD5** ma IDD6** ma IDD7* ma Note: The IDD specification is based on Samsung Bdie components. * : Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P ( CKE LOW) mode. **: Value calculated reflects all module ranks in this operating condition. Tel: Fax: PAGE 6 OF 12

7 PART NO: VL47B5263ZR9S/R8S/R7SHS REV: 1.0 Parameter Clock Timing Minimum Clock Cycle Time (DLL off mode) AC TIMING PARAMETERS & SPECIFICATIONS Symbol tck (DLL_OFF) DDR31333 (R9) DDR31066 (R8) DDR3800 (R7) MIN MAX MIN MAX MIN MAX ns Average Clock Period tck(avg) See Speed Bins Table ps Clock Period tck(abs) tck(avg)min + tjit(per)min tck(avg)min + tjit(per)min tck(avg)min + tjit(per)min tck(avg) + tjit(per) tck(avg)min + tjit(per)min tck(avg) + tjit(per) Average high pulse width tch(avg) tck (avg) Average low pulse width tcl(avg) tck (avg) Clock Period Jitter (Period) tjit(per) ps Clock Period Jitter during DLL locking period tjit(per, lck) ps Cycle to Cycle Period Jitter tjit(cc) ps Cycle to Cycle Period Jitter during DLL locking period tjit(cc, lck) ps Cumulative error across 2 cycles terr(2per) ps Cumulative error across 3 cycles terr(3per) ps Cumulative error across 4 cycles terr(4per) ps Cumulative error across 5 cycles terr(5per) ps Cumulative error across 6 cycles terr(6per) ps Cumulative error across 7 cycles terr(7per) ps Cumulative error across 8 cycles terr(8per) ps Cumulative error across 9 cycles terr(9per) ps Cumulative error across 10 cycles terr(10per) ps Cumulative error across 11 cycles terr(11per) ps Cumulative error across 12 cycles terr(12per) ps Unit ps Cumulative error across n = 13, , 50 cycles terr(nper) terr(nper)min = ( ln(n))*tJIT(per)min terr(nper) = (1 = 0.68ln(n))*tJIT(per) Absolute clock HIGH pulse width tch(abs) Absolute clock Low pulse width tcl(abs) Data Timing S,S to skew, per group, per access tsq ps output hold time from S, S tqh tck (avg) lowimpedance time from CK, CK tlz() ps highimpedance time from CK, CK thz() ps Data setup time to S, S referenced to Vih(ac)Vil(ac) levels tds(base) ps Data hold time to S, S referenced to Vih(ac)Vil(ac) levels tdh(base) ps tck (avg) tck (avg) Tel: Fax: PAGE 7 OF 12

8 PART NO: VL47B5263ZR9S/R8S/R7SHS REV: 1.0 Parameter Data Strobe Timing AC TIMING PARAMETERS & SPECIFICATIONS Symbol DDR31333 (R9) DDR31066 (R8) Tel: Fax: PAGE 8 OF 12 DDR3800 (R7) MIN MAX MIN MAX MIN MAX S, S READ Preamble trpre tck S, S differential READ Postamble trpst tck S, S output high time tqsh tck(avg) S, S output low time tqsl tck(avg) S, S WRITE Preamble twpre tck S, S WRITE Postamble twpst tck S, S rising edge output access time from rising CK, CK tsck ps S, S lowimpedance time (Referenced from RL1) tlz(s) ps S, S highimpedance time (Referenced from RL+BL/ 2) thz(s) ps S, S differential input low pulse width tsl tck S, S differential input high pulse width tsh tck S, S rising edge to CK, CK rising edge tss tck(avg) S,S failing edge setup time to CK, CK rising edge tdss tck(avg) S,S failing edge hold time to CK, CK rising edge tdsh tck(avg) Command and Address Timing DLL locking time tdllk nck Internal READ Command to PRECHARGE Command delay Delay from start of internal write transaction to internal read command trtp twtr WRITE recovery time twr ns Mode Register Set command cycle time Mode Register Set command update delay Unit tmrd tck(avg) tmod (12tCK,15ns) (12tCK,15ns) (12tCK,15ns) CAS# to CAS# command delay tccd nck Auto precharge write recovery + precharge time MultiPurpose Register Recovery Time ACTIVE to PRECHARGE command period ACTIVE to ACTIVE command period for 1KB page size ACTIVE to ACTIVE command period for 2KB page size Four activate window for 1KB page size Four activate window for 2KB page size Command and Address setup time to CK, CK referenced to Vih(ac) / Vil(ac) levels Command and Address hold time from CK, CK referenced to Vih(ac) / Vil(ac) levels tdal(min) WR + roundup (trp / tck(avg)) nck tmprr nck tras 36 70, , ,000 ns trrd trrd (4tCK,6ns) (4tCK, (4tCK, (4tCK, tfaw ns tfaw ns tis(base) ps tih(base) ps

9 PART NO: VL47B5263ZR9S/R8S/R7SHS REV: 1.0 AC TIMING PARAMETERS & SPECIFICATIONS Parameter Refresh Timing 512Mb REFRESH to REFRESH OR REFRESH to ACTIVE command interval 1Gb REFRESH to REFRESH OR REFRESH to ACTIVE command interval 2Gb REFRESH to REFRESH OR REFRESH to ACTIVE command interval 4Gb REFRESH to REFRESH OR REFRESH to ACTIVE command interval Symbol DDR31333 (R9) DDR31066 (R8) DDR3800 (R7) MIN MAX MIN MAX MIN MAX trfc ns trfc ns trfc ns trfc ns Unit 8Gb REFRESH to REFRESH OR REFRESH to ACTIVE command interval Average periodic refresh interval(0 C<= TCASE <= 85 C) Average periodic refresh interval (85 C<= TCASE <= 95 C) Calibration Timing trfc ns trefi us trefi us Powerup and RESET calibration time tiniti tck Normal operation Full calibration time toper tck Normal operation Short calibration time tcs tck Reset Timing Exit Reset from CKE HIGH to a valid command Self Refresh Timing Exit Self Refresh to commands not requiring a locked DLL Exit Self Refresh to commands requiring a locked DLL Minimum CKE low width for Self refresh entry to exit timing txpr txs (5tCK, trfc + (5tCK, trfc + (5tCK, trfc + (5tCK, trfc + (5tCK, trfc + (5tCK, trfc + txsdll tdllk(min) tdllk(min) tdllk(min) tck tckesr tcke(min) + 1tCK tcke(min) + 1tCK tcke(min) + 1tCK Valid Clock Requirement after Self Refresh Entry (SRE) tcksre (5tCK, (5tCK,1 0ns) (5tCK,1 0ns) Valid Clock Requirement before Self Refresh Exit (SRX) Power Down Timing Exit Power Down with DLL to any valid command; Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL CKE minimum pulse width tcksrx txp txpdll tcke (5tCK, (3tCK,6ns) (10tCK,24n s) (3tCK,5.62 5ns) (5tCK,1 0ns) (3tCK,7.5ns ) (10tCK,24n s) (3tCK,5.625 ns) (5tCK,1 0ns) (3tCK,7.5ns ) (10tCK,24n s) (3tCK,7.5ns ) Command pass disable delay tcpded nck Tel: Fax: PAGE 9 OF 12

10 PART NO: VL47B5263ZR9S/R8S/R7SHS REV: 1.0 Parameter AC TIMING PARAMETERS & SPECIFICATIONS Symbol DDR31333 (R9) DDR31066 (R8) DDR3800 (R7) MIN MAX MIN MAX MIN MAX Unit Power Down Entry to Exit Timing tpd tcke(min) 9*tREFI tcke(min) 9*tREFI tcke(min) 9*tREFI tck Timing of ACT command to Power Down entry tactpden nck Timing of PRE command to Power Down entry tprpden nck Timing of RD/RDA command to Power Down entry trdpden RL RL RL WL + 4 WL + 4 WL + 4 Timing of WR command to Power Down entry twrpden +(twr/ +(twr/ +(twr/ (BL8OTF, BL8MRS, BL4OTF) tck) tck) tck) nck Timing of WRA command to Power Down entry (BL8OTF, BL8MRS, BL4OTF) Timing of WR command to Power Down entry (BL4MRS) Timing of WRA command to Power Down entry (BL4MRS) twrapden twrpden twrapden WL + 4 +WR +1 WL + 2 +(twr/ tck) WL +2 +WR +1 WL + 4 +WR +1 WL + 2 +(twr/ tck) WL +2 +WR +1 WL + 4 +WR +1 WL + 2 +(twr/ tck) WL +2 +WR +1 Timing of REF command to Power Down entry trefpden nck nck nck Timing of MRS command to Power Down entry tmrspden tmod(min) tmod(min) tmod(min) tck ODT Timing ODT high time without write command or with write command and BC4 ODTH nck ODT high time with Write command and BL8 ODTH nck Asynchronous RTT turnon delay (PowerDown with DLL frozen) Asynchronous RTT turnoff delay (PowerDown with DLL frozen) taonpd ns taofpd ns ODT turnon taon ps RTT_NOM and RTT_WR turnoff time from ODTL off reference taof tck(avg) RTT dynamic change skew tadc tck(avg) Write Leveling Timing First S pulse rising edge after tss margining mode is programmed S/S delay after ts margining mode is programmed twlmrd tck twlsen tck Setup time for tss latch twls ps Hold time for tss latch twlh ps Write leveling output delay twlo ns Write leveling output error twloe ns Tel: Fax: PAGE 10 OF 12

11 PART NO: VL47B5263ZR9S/R8S/R7SHS REV: 1.0 Package Dimensions FRONT VIEW MAX / 0.10 (2X) 1.80 (2X) TYP TYP TYP 2.15 TYP PIN TYP 0.45 TYP 0.60 TYP / TYP PIN 203 BACK VIEW 2.55 TYP 4.00 TYP PIN TYP PIN TYP TYP 24.8 TYP Notes: All dimensions are in millimeters with tolerance +/ 0.13mm unless otherwise specified. Tel: Fax: PAGE 11 OF 12

12 PART NO: VL47B5263ZR9S/R8S/R7SHS REV: 1.0 Revision History: Date Rev. Page Changes 03/31/ All Release spec Tel: Fax: PAGE 12 OF 12