Product Specifications. General Information. Order Information: VL41B5263A-K0/K9/F8/E7S REV: 1.0. Pin Description PART NO.:

Transcription

1 PART NO.: VL41B5263AK0/K9/F8/E7S REV: 1.0 General Information 4GB 512Mx72 DDR3 SDRAM ECC UNBUFFERED SOUDIMM 204PIN Description The VL41B5263A is a 512Mx72 DDR3 SDRAM high density SOUDIMM. This memory module is dual rank, consists of eighteen CMOS 256Mx8 bits with 8 banks DDR3 synchronous DRAMs in BGA packages and a 2K EEPROM in an 8pin MLF package. This module is a 204pin smalloutline dual inline memory module and is intended for mounting into an edge connector socket. Decoupling capacitors are mounted on the printed circuit board for each DDR3 SDRAM. Features 204pin, unbuffered smalloutline dual inline memory module (SOUDIMM) Supports ECC error detection and correction Fast data transfer rates: PC312800, PC310600, PC38500, PC36400 VDD = VDDQ = 1.5V /0.075V JEDEC standard 1.5V /0.075V I/O (SSTL_15 compatible) VDDSPD = 3.0V to 3.6V Eight internal component banks for concurrent operation 8bit prefetch architecture Bidirectional differential datastrobe Nominal and dynamic ondie termination (ODT) calibration support Programmable CAS# latency: 11 (DDR31600), 9 (DDR31333), 7 (DDR31066), 6 (DDR3800) Programmable burst; length (8) Average refresh period 7.8 us Asynchronous reset Flyby topology On board terminated command, address, and control bus Serial presence detect (SPD) with EEPROM Leadfree, RoHS compliant Gold edge contacts PCB: Height 30.00mm (1.181 ), double sided component Operating temperature (TOPER): Commercial (0 o C <= Tc <= 95 o C) Industrial (40 o C <= Tc <= 95 o C) Notes: Double refresh rate is required when 85 o C < TOPER <= 95 o C. TOPER is DRAM case temperature (Tc). Order Information: VL41B5263A K0 S X X OPERATING TEMPERATURE None: Commercial S1: Industrial screening DRAM DIE (Option) DRAM MANUFACTURER S SAMSUNG Pin Description Pin Name A0~A14 A10/AP A12/BC# BA0~BA2 ~3 DQS0~DQS8 DQS0#~DQS8# DM0~DM8 CB0~CB7 CK0,CK0#, CK1,CK1# ODT0, ODT1 CKE0, CKE1 CS0#, CS1# RAS# CAS# WE# VDD VSS SA0~SA1 SDA SCL VREFCA VREFDQ VDDSPD VTT RESET# NC Function Address Inputs Address Input/ Autoprecharge Address Input/ Burst Chop Bank Address Inputs Data Input/Output Data Strobes Data Strobes Complement Data Masks Data Check Bits I/O Clock Input Ondie Termination Control Clock Enables Chip Selects Row Address Strobes Column Address Strobes Write Enable Voltage Supply Ground SPD Address SPD Data Input/Output SPD Clock Input Reference Voltage for CA Reference Voltage for DQ SPD Voltage Supply Termination Voltage Register and SDRAM Control No Connect MODULE SPEED K0: CL11 K9: CL9 F8: CL7 E7: CL6 VL: Leadfree/RoHS DRAM component: Samsung K4B2G0846DHCK0 (Leadfree/RoHS) Tel Tomas, Rancho Santa Margarita, CA USA 1

2 VL41B5263AK0/K9/F8/E7S REV: 1.0 Pin Configuration 204PIN DDR3 SOUDIMM FRONT 204PIN DDR3 SOUDIMM BACK Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name 1 VREFDQ 53 VSS 105 A1 157 DM5 2 VSS A2 158 VSS 3 VSS A0 159 DQ42 4 DQ BA1 160 DQ VDD 161 DQ VSS 110 VDD 162 DQ DM3 111 CK0 163 VSS 8 VSS 60 DQS3# 112 CK1 164 VSS 9 VSS 61 VSS 113 CK0# 165 DQ48 10 DQS0# 62 DQS3 114 CK1# DM VDD 167 DQ49 12 DQS0 64 VSS 116 VDD A10/AP 169 VSS 14 VSS CS3# * 170 VSS VSS 119 BA0 171 DQS6# CS2# * 172 DM6 17 VSS 69 CB0 121 WE# 173 DQS VSS 122 RAS# DQ8 71 CB1 123 VDD 175 VSS 20 VSS 72 CB4 124 VDD DQ9 73 VSS 125 CAS# CB5 126 ODT0 178 VSS 23 VSS 75 DQS8# 127 CS0# DM8 128 ODT DQS1# 77 DQS8 129 CS1# 181 VSS 26 VSS 78 VSS 130 A DQS1 79 VSS 131 VDD DM1 80 CB6 132 VDD 184 VSS 29 VSS 81 CB RESET# 82 CB DQS7# CB VSS 32 VSS 84 VREFCA DQS VDD 137 VSS 189 DM VDD 138 VSS 190 VSS 35 VSS 87 CKE0 139 DQS4# A15 * 140 DM CKE1 141 DQS VSS 90 A BA2 143 VSS 195 VSS A VSS 41 VSS 93 VDD SA VDD 146 VSS 198 EVENT# * 43 DQS2# 95 A12/BC# VDDSPD 44 DM2 96 A DQ SDA 45 DQS2 97 A8 149 VSS 201 SA1 46 VSS 98 A7 150 DQ SCL 47 VSS 99 A5 151 DQ VTT A6 152 VSS 204 VTT VDD 153 DQ VDD 154 DQS5# A3 155 VSS 52 VSS 104 A4 156 DQS5 *: These pins are not used in this module. Tel Tomas, Rancho Santa Margarita, CA USA 2

3 VL41B5263AK0/K9/F8/E7S REV: 1.0 Function Block Diagram CS1# CS0# DQS0 DQS0# DM0 DQS4 DQS4# DM4 DQ4 DQ4 D0 DQ4 D DQ4 D4 DQ4 D13 DQS1 DQS1# DM1 DQS5 DQS5# DM5 DQ8 DQ DQ4 D1 DQ4 D10 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ4 D5 DQ4 D14 DQS2 DQS2# DM2 DQS6 DQS6# DM DQ4 D2 DQ4 D11 DQ48 DQ DQ4 D6 DQ4 D15 DQS3 DQS3# DM3 DQS7 DQS7# DM DQ4 D3 DQ4 D DQ4 D7 DQ4 D16 DQS8 DQS8# DM8 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQ4 D8 DQ4 D17 A0A14, BA0BA2 RAS#, CAS#, WE#, CS0#, CKE0, ODT0 CS1#, CKE1, ODT1 CK0, CK1 CK0#, CK1# DDR3 SDRAM DDR3 SDRAM Command, address, control, and clock line terminations 36 ohm /5% VTT 30 ohm /5% VDD 0.1uF A0A14 BA0BA2 RAS# CAS# WE# CKE0 ODT0 CKE1 ODT1 RESET# A0A14: SDRAMs D0D17 BA0BA2: SDRAMs D0D17 RAS#: SDRAMs D0D17 CAS#: SDRAMs D0D17 WE#: SDRAMs D0D17 CKE0: SDRAMs D0D8 ODT0: SDRAMs D0D8 CKE1: SDRAMs D9D17 ODT1: SDRAMs D9D17 RESET#: SDRAMs D0D17 SCL Serial PD WP A0 A1 A2 SA0 SA1 SDA VDDSPD VDD VTT VREFCA VREFDQ VSS Serial PD D0D17 D0D17 D0D17 D0D17 D0D17 CK0 CK0# D0D8 CK1 CK1# D9D17 Notes: 1. Unless otherwise noted, resistor values are 15 ohms /5% 2. resistors are 240 ohms /1% 3.3pF 3.3pF Tel Tomas, Rancho Santa Margarita, CA USA 3

4 VL41B5263AK0/K9/F8/E7S REV: 1.0 Absolute Maximum Ratings Symbol Parameter MIN MAX Unit VDD Voltage on VDD pin relative to VSS V VDDQ Voltage on VDDQ pin relative to VSS V VIN, VOUT Voltage on any pin relative to VSS V TSTG Storage temperature C IL IOZ Input leakage current; Any input 0V<VIN<VDD; VREF input 0V<VIN<0.95V; Other pins not under test = 0V Output leakage current; 0V<VOUT<VDDQ; DQs and ODT are disabled Address, RAS#, CAS#, WE#, BA CS#, CKE, ODT, CK, CK# ua ua DM 4 4 ua DQ, DQS, DQS# ua IVREF VREF supply leakage current; VREF = Valid VREF level ua DC Operating Conditions Symbol Parameter Min Typical Max Unit Notes VDD Supply Voltage V 1,2 VDDQ I/O Supply Voltage V 1,2 VREFDQ (DC) I/O reference voltage DQ bus 0.49 x VDD 0.5 x VDD 0.51 x VDD V 3,4 VREFCA (DC) Input reference voltage CMD/ADD bus 0.49 x VDD 0.5 x VDD 0.51 x VDD V 3,4 VTT Termination Reference Voltage x VDDQ 0.5 x VDDQ x VDDQ V 5 Notes: 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. 3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than /1% VDD 4. For reference: approximate VDD/2 /15mV. 5. VTT termination voltage in excess of stated limit will adversely affect the command and address signals voltage margin and will reduce timing margins. Operating Temperature Condition Symbol Parameter Rating Units Notes TOPER Operating temperature Commercial 0 to 95 0 C 1,2 Industrial 40 to 95 Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD At 40 to 85 o C, operation temperature range, all DRAM specifications will be supported. The refresh rate is required to double when 85 o C < TOPER <= 95 o C. Tel Tomas, Rancho Santa Margarita, CA USA 4

5 VL41B5263AK0/K9/F8/E7S REV: 1.0 Input DC Logic Level All voltages referenced to VSS Symbol Parameter Min Max Unit Command and Address VIHCA(DC) Input High (Logic 1) Voltage (DDR3800/1066/1333/1600) VREF VDD V VILCA(DC) Input Low (Logic 0) Voltage (DDR3800/1066/1333/1600) VSS VREF V DQ and DM VIHDQ(DC) Input High (Logic 1) Voltage (DDR3800/1066/1333/1600) VREF VDD V VILDQ(DC) Input Low (Logic 0) Voltage (DDR3800/1066/1333/1600) VSS VREF V Input AC Logic Level All voltages referenced to VSS Symbol Parameter Min Max Unit Command and Address VIHCA(AC) Input High (Logic 1) Voltage (DDR3800/1066/1333/1600) VREF V VILCA(AC) Input Low (Logic 0) Voltage (DDR3800/1066/1333/1600) VREF V DQ and DM VIHDQ(AC) Input High (Logic 1) Voltage (DDR3800/1066) VREF V VILDQ(AC) Input Low (Logic 0) Voltage (DDR3800/1066) VREF V VIHDQ(AC) Input High (Logic 1) Voltage (DDR31333/1600) VREF V VILDQ(AC) Input Low (Logic 0) Voltage (DDR31333/1600) VREF V Parameter Input capacitance (A0~A14, BA0~BA2, RAS#, CAS#, WE#) Input capacitance (CKE0, CKE1), (ODT0, ODT1), (CS0#, CS1#) Input/Output Capacitance TA=25 0 C, f=100mhz Symbol K0 (DDR31600) K9 (DDR31333) F8 (DDR31066) E7 (DDR3800) Min Max Min Max Min Max Min Max CIN pf CIN pf Input capacitance (CK0, CK0#), (CK1, CK1#) CIN pf Input/Output capacitance (DQ, DQS, DQS#, CB, DM) CIO pf Unit Tel Tomas, Rancho Santa Margarita, CA USA 5

6 VL41B5263AK0/K9/F8/E7S REV: 1.0 Condition IDD Specification Symbol K0 (DDR31600) K9 (DDR31333) F8 (DDR31066) E7 (DDR3800) Operating one bank activeprecharge current; tck= tck(idd); trc= trc(idd); tras= tras MIN(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Operating one bank activereadprecharge current; IDD0* ma IOUT = 0mA; BL = 8; CL = CL(IDD); AL = 0; tck= tck(idd); trc= trc(idd); tras= tras MIN(IDD); trcd= trcd(idd); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W. Precharge powerdown current; All device banks idle; tck= tck(idd); CKE is LOW; Other IDD1* IDD2PF** ma ma control and address bus inputs are STABLE; Data bus inputs are FLOATING. IDD2PS** ma Precharge standby current; All device banks idle; tck= tck(idd); CKE is HIGH; CS# is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Precharge quiet standby current; IDD2N** ma All device banks idle; tck= tck(idd); CKE is HIGH; CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. Active powerdown current; IDD2Q** ma All device banks open; tck= tck(idd); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. Active standby current; IDD3P** ma All device banks open; tck= tck(idd); trp= trp(idd); tras= tras MAX(IDD)); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Operating burst read current; IDD3N** ma All device banks open; Continuous burst reads; IOUT = 0mA; BL = 8; CL = CL(IDD); AL = 0; tck= tck(idd); tras= tras MAX(IDD); trp= trp(idd); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W. Operating burst write current; IDD4R* ma All device banks open; Continuous burst writes; BL = 8; CL = CL(IDD); AL = 0; tck= tck(idd); tras= tras MAX(IDD); trp= trp(idd); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Burst refresh current; IDD4W* ma tck=tck(idd); Refresh command at every trfc(idd) interval; CKE is HIGH; CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Self refresh current; IDD5** ma CK and CK# at 0V; CKE < 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING. Operating bank interleave read current; IDD6** ma All bank interleaving reads; IOUT = 0mA; BL = 8; CL = CL(IDD); AL = trcd(idd) 1*tCK(IDD); tck= tck(idd); trc= trc(idd); trrd = trrd(idd); trcd = 1*tCK(IDD) ; CKE is HIGH; CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R. IDD7* ma Notes: IDD specification is based on Samsung Ddie components. *: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode. **: Value calculated reflects all module ranks in this operating condition. Unit Tel Tomas, Rancho Santa Margarita, CA USA 6

7 PART NO.: VL41B5263AK0/K9/F8/E7S REV: 1.0 AC TIMING PARAMETERS & SPECIFICATIONS Parameter Symbol K0 (DDR31600) K9 (DDR31333) F8 (DDR31066) E7 (DDR3800) MIN MAX MIN MAX MIN MAX MIN MAX Unit Clock Timing Minimum Clock Cycle Time (DLL off mode) tck(dll_off) ns Average Clock Period tck(avg) 1.25 < < < ns Clock Period tck(abs) tck(avg)min tjit(per)min tck(avg) tjit(per) tck(avg)min tjit(per)min tck(avg) tjit(per) tck(avg)min tjit(per)min tck(avg) tjit(per) tck(avg)min tjit(per)min tck(avg) tjit(per) ns Average high pulse width tch(avg) tck(avg) Average low pulse width tcl(avg) tck(avg) Clock Period Jitter tjit(per) ps Clock Period Jitter during DLL locking period tjit(per, lck) ps Cycle to Cycle Period Jitter tjit(cc) ps Cycle to Cycle Period Jitter during DLL locking period tjit(cc, lck) ps Cumulative error across 2 cycles terr(2per) ps Cumulative error across 3 cycles terr(3per) ps Cumulative error across 4 cycles terr(4per) ps Cumulative error across 5 cycles terr(5per) ps Cumulative error across 6 cycles terr(6per) ps Cumulative error across 7 cycles terr(7per) ps Cumulative error across 8 cycles terr(8per) ps Cumulative error across 9 cycles terr(9per) ps Cumulative error across 10 cycles terr(10per) ps Cumulative error across 11 cycles terr(11per) ps Cumulative error across 12 cycles terr(12per) ps Cumulative error across n = 13, , 50 cycles terr(nper) terr(nper)min =(1 0.68ln(n))*tJIT(per)min terr(nper)=(1 0.68ln(n))*tJIT(per) ps Absolute clock HIGH pulse width tch(abs) tck(avg) Absolute clock Low pulse width tcl(abs) tck(avg) Data Timing DQS,DQS# to DQ skew, per group, per access tdqsq ps DQ output hold time from DQS, DQS# tqh tck(avg) DQ lowimpedance time from CK, CK# tlz(dq) ps DQ highimpedance time from CK, CK# thz(dq) ps Data setup time to DQS, DQS# referenced to Vih(ac)Vil(ac) levels Data hold time to DQS, DQS# referenced to Vih(ac)Vil(ac) levels tds(base) ps tdh(base) ps DQ and DM Input pulse width for each input tdipw ps Tel Tomas, Rancho Santa Margarita, CA USA 7

8 VL41B5263AK0/K9/F8/E7S REV: 1.0 Parameter Data Strobe Timing AC TIMING PARAMETERS & SPECIFICATIONS Symbol K0 (DDR31600) K9 (DDR31333) F8 (DDR31066) E7 (DDR3800) MIN MAX MIN MAX MIN MAX MIN MAX Unit DQS, DQS# READ Preamble trpre tck DQS, DQS# differential READ Postamble trpst tck DQS, DQS# output high time tqsh tck(avg) DQS, DQS# output low time tqsl tck(avg) DQS, DQS# WRITE Preamble twpre tck DQS, DQS# WRITE Postamble twpst tck DQS, DQS# rising edge output access time from rising CK, CK# DQS, DQS# lowimpedance time (Referenced from DQS, DQS# highimpedance time (Referenced from RLBL/ 2) tdqsck ps tlz(dqs) ps thz(dqs) ps DQS, DQS# differential input low pulse width tdqsl tck DQS, DQS# differential input high pulse width DQS, DQS# rising edge to CK, CK# rising edge DQS,DQS# failing edge setup time to CK, CK# rising edge DQS,DQS# failing edge hold time to CK, CK# rising edge Command and Address Timing tdqsh tck tdqss tck(avg) tdss tck(avg) tdsh tck(avg) DLL locking time tdllk nck Internal READ Command to PRECHARGE Command delay Delay from start of internal write transaction to internal read command trtp twtr WRITE recovery time twr ns Mode Register Set command cycle time tmrd nck Mode Register Set command update delay tmod (12tCK,15ns) (12tCK,15ns) (12tCK,15ns) (12tCK,15ns) CAS# to CAS# command delay tccd nck Auto precharge write recovery precharge time tdal(min) WR roundup (trp / tck(avg)) nck MultiPurpose Register Recovery Time tmprr nck ACTIVE to PRECHARGE command period tras 35 9*tREFI 36 9*tREFI *tREFI *tREFI ns ACTIVE to ACTIVE command period for 1KB page size ACTIVE to ACTIVE command period for 2KB page size trrd trrd (4tCK,6ns) (4tCK,6ns) (4tCK, (4tCK, (4tCK, Four activate window for 1KB page size tfaw ns Four activate window for 2KB page size tfaw ns Command and Address setup time to CK, CK# referenced to Vih(ac) / Vil(ac) levels Command and Address hold time from CK, CK# referenced to Vih(ac) / Vil(ac) levels Control & Address Input pulse width for each input tis(base) ps tih(base) ps tipw ps Tel Tomas, Rancho Santa Margarita, CA USA 8

9 PART NO.: VL41B5263AK0/K9/F8/E7S REV: 1.0 AC TIMING PARAMETERS & SPECIFICATIONS Parameter Symbol K0 (DDR31600) K9 (DDR31333) F8 (DDR31066) E7 (DDR3800) MIN MAX MIN MAX MIN MAX MIN MAX Unit Refresh Timing 2Gb REFRESH to REFRESH or REFRESH to ACTIVE command interval Average periodic refresh interval (0 C<= TCASE <= 85 C) Average periodic refresh interval (85 C<= TCASE <= 95 C) trfc ns trefi us trefi us Calibration Timing Powerup and RESET calibration time tiniti tck Normal operation Full calibration time toper tck Normal operation Short calibration time tcs tck Reset Timing Exit Reset from CKE HIGH to a valid command txpr (5tCK, trfc (5tCK, trfc (5tCK, trfc (5tCK, trfc Self Refresh Timing Exit Self Refresh to commands not requiring a locked DLL txs (5tC, trfc (5tC, trfc (5tC, trfc (5tC, trfc Exit Self Refresh to commands requiring a locked DLL txsdll tdllk(min) tdllk(min) tdllk(min) tdllk(min) nck Minimum CKE low width for Self refresh entry to exit timing tckesr tcke(min) 1tCK tcke(min) 1tCK tcke(min) 1tCK tcke(min) 1tCK Valid Clock Requirement after Self Refresh Entry (SRE) tcksre (5tC, (5tCK, (5tCK, (5tCK, Valid Clock Requirement before Self Refresh Exit (SRX) tcksrx (5tC, (5tCK, (5tCK, (5tCK, Power Down Timing Exit Power Down with DLL to any valid command; Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL txp (3tCK,6ns) (3tCK,6ns) (3tCK,7.5ns) (3tCK,7.5ns) Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL txpdll (10tCK,24ns) (10tCK,24ns) (10tCK,24ns) (10tCK,24ns) CKE minimum pulse width tcke (3tCK, 5.625ns) (3tCK, 5.625ns) (3tCK, 5.625ns) (3tCK, 7.5ns) Command pass disable delay tcpded nck Power Down Entry to Exit Timing tpd tcke(min) 9*tREFI tcke(min) 9*tREFI tcke(min) 9*tREFI tcke(min) 9*tREFI tck Timing of ACT command to Power Down entry Timing of PRE command to Power Down entry Timing of RD/RDA command to Power Down entry Timing of WR command to Power Down entry BL8 (OTF, MRS), BL4OTF Timing of WRA command to Power Down entry BL8 (OTF, MRS), BL4OTF Timing of WR command to Power Down entry (BL4MRS) Timing of WRA command to Power Down entry (BL4MRS) Timing of REF command to Power Down entry Timing of MRS command to Power Down entry tactpden nck tprpden nck trdpden RL 4 1 RL 4 1 RL 4 1 RL 4 1 twrpden twrapden twrpden twrapden WL 4 (twr/ tck) WL4WR 1 WL 2 (twr/ tck) WL2WR 1 WL 4 (twr/ tck) WL 4 (twr/ tck) WL 4 (twr/ tck) nck WL4WR1 WL4WR1 WL4WR1 nck WL 2 (twr/ tck) WL 2 (twr/ tck) WL 2 (twr/ tck) nck WL2WR1 WL2WR1 WL2WR1 nck trefpden tmrspden tmod(min) tmod(min) tmod(min) tmod(min) Tel Tomas, Rancho Santa Margarita, CA USA 9

10 PART NO.: VL41B5263AK0/K9/F8/E7S REV: 1.0 AC TIMING PARAMETERS & SPECIFICATIONS Parameter ODT Timing ODT high time without write command or with write command and BC4 Symbol K0 (DDR31600) K9 (DDR31333) F8 (DDR31066) E7 (DDR3800) MIN MAX MIN MAX MIN MAX MIN MAX ODTH nck Unit ODT high time with Write command and BL8 ODTH nck Asynchronous RTT turnon delay (Power Down with DLL frozen) Asynchronous RTT turnoff delay (Power Down with DLL frozen) taonpd ns taofpd ns ODT turnon taon ps RTT_NOM and RTT_WR turnoff time from ODTL off reference taof tck(avg) RTT dynamic change skew tadc tck(avg) Write Leveling Timing First DQS pulse rising edge after tdqss margining mode is programmed DQS/DQS delay after tdqs margining mode is programmed twlmrd tck twldqsen tck Setup time for tdqss latch twls ps Hold time for tdqss latch twlh ps Write leveling output delay twlo ns Write leveling output error twloe ns Tel Tomas, Rancho Santa Margarita, CA USA 10

11 VL41B5263AK0/K9/F8/E7S REV: 1.0 Package Dimensions.. FRONT VIEW MAX 4.0 / 0.10 (2X) TYP 1.80 (2X) TYP TYP TYP 2.15 TYP 1.0 / 0.10 TYP PIN R 0.60 TYP 0.45 TYP PIN / TYP BACK VIEW 2.55 TYP 4.00 TYP PIN TYP 3.00 TYP TYP PIN TYP.. Note: 1. All dimensions are in millimeters with tolerance / 0.15mm unless otherwise specified. 2. The dimensional diagram is for reference only. Tel Tomas, Rancho Santa Margarita, CA USA 11

12 VL41B5263AK0/K9/F8/E7S REV: 1.0 Revision History: Date Rev. Page Changes 03/24/ All Spec released Tel Tomas, Rancho Santa Margarita, CA USA 12