SN74ALS533A, SN74AS533A OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SDAS270 DECEMBER 1994

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1 Eight Latches in a Single Package -State Bus-Driving Inverting Outputs Full Parallel Access for Loading Buffered Control Inputs pnp Inputs Reduce dc Loading on Data Lines Package Optio Include Plastic Small-Outline (DW) Packages and Standard Plastic (N) 00-mil DIPs description These 8-bit D-type traparent latches feature -state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. SN74ALSA, SN74ASA DW OR N PACKAGE (TOP VIEW) While latch-enable () input is high, the Q outputs follow the complements of the data (D) inputs. When is taken low, the Q outputs are latched at the inverses of the levels set up at the D inputs. The SN74ALSA and SN74ASA are functionally equivalent to the SN74ALS7A and SN74AS7, except for having inverted outputs. A buffered output-enable () input places the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. does not affect the internal operatio of the latches. Old data can be retained or new data can be entered while the outputs are off. The SN74ALSA and SN74ASA are characterized for operation from 0 C to 70 C. FUNCTION TAB (each latch) INPUTS OUTPUT D Q L H H L L H L H L L X Q0 H X X Z Q 2D 2Q Q D 4D 4Q GND V CC 8Q 8D 7D 7Q 6Q 6D D Q PRODUCTION DATA information is current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 994, Texas Itruments Incorporated POST OFFICE BOX 60 DALLAS, TEXAS 726

2 logic symbol logic diagram (positive logic) EN 2D D 4D D 6D 7D 8D Q 2Q Q 4Q Q 6Q 7Q 8Q 2D D Q 2Q Q This symbol is in accordance with ANSI/IEEE Std and IEC Publication D 8 9 4Q D 2 Q 6D 4 6Q 7D 7 6 7Q 8D 8 9 8Q absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC V Input voltage, V I V Voltage applied to a disabled -state output V Operating free-air temperature range, T A : SN74ALSA C to 70 C Storage temperature range C to 0 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. 2 POST OFFICE BOX 60 DALLAS, TEXAS 726

3 recommended operating conditio SN74ALSA MIN NOM MAX VCC Supply voltage 4.. V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V IOH High-level output current 2.6 ma IOL Low-level output current 24 ma tw Pulse duration, high tsu Setup time, data before th Hold time, data after 7 TA Operating free-air temperature 0 70 C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS SN74ALSA MIN TYP MAX VIK VCC = 4. V, II = 8 ma. V VCC =4V 4. VCC = 4. V to. V, IOH = 0.4 ma VCC 2 VCC = 4. V, IOH = 2.6 ma IOL = 2 ma IOL = 24 ma IOZH VCC =. V, VO = 2.7 V 20 µa IOZL VCC =. V, VO = 0.4 V 20 µa II VCC =. V, VI = 7 V 0. ma IIH VCC =. V, VI = 2.7 V 20 µa IIL VCC =. V, VI = 0.4 V 0. ma IO VCC =. V, VO = 2.2 V 0 2 ma Outputs high 0 7 ICC VCC =. V Outputs low 7 26 ma Outputs disabled All typical values are at VCC = V, TA = 2 C. The output conditio have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. V V POST OFFICE BOX 60 DALLAS, TEXAS 726

4 switching characteristics (see Figure ) FROM (INPUT) TO (OUTPUT) VCC = 4. V to. V, CL = 0 pf, R = 00 Ω, R2 = 00 Ω, TA = MIN to MAX SN74ALSA 4 9 D Q tpzh 7 tpzl 4 8 tphz 2 0 tplz 2 6 For conditio shown as MIN or MAX, use the appropriate value specified under recommended operating conditio. MIN MAX absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC V Input voltage, V I V Voltage applied to a disabled -state output V Operating free-air temperature range, T A : SN74ASA C to 70 C Storage temperature range C to 0 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. recommended operating conditio SN74ASA MIN NOM MAX VCC Supply voltage 4.. V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V IOH High-level output current ma IOL Low-level output current 48 ma tw Pulse duration, high 2 tsu Setup time, data before 2 th Hold time, data after TA Operating free-air temperature 0 70 C 4 POST OFFICE BOX 60 DALLAS, TEXAS 726

5 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS SN74ASA MIN TYP MAX VIK VCC = 4. V, II = 8 ma. V VCC = 4. V to. V, IOH = 2 ma VCC 2 VCC = 4. V, IOH = ma 2.4. VCC = 4. V, IOL = 48 ma V IOZH VCC =. V, VO = 2.7 V 0 µa IOZL VCC =. V, VO = 0.4 V 0 µa II VCC =. V, VI = 7 V 0. ma IIH VCC =. V, VI = 2.7 V 20 µa IIL VCC =. V, VI = 0.4 V ma IO VCC =. V, VO = 2.2 V 0 2 ma Outputs high ICC VCC =. V Outputs low ma Outputs disabled 7 0 All typical values are at VCC = V, TA = 2 C. The output conditio have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. switching characteristics (see Figure ) V FROM (INPUT) TO (OUTPUT) VCC = 4. V to. V, CL = 0 pf, R = 00 Ω, R2 = 00 Ω, TA = MIN to MAX SN74ASA 4 7. D Q tpzh 2 6. tpzl 4 9. tphz 2 6. tplz 7 For conditio shown as MIN or MAX, use the appropriate value specified under recommended operating conditio. MIN MAX POST OFFICE BOX 60 DALLAS, TEXAS 726

6 MEASUREMENT INFORMATION SERIES 4ALS/74ALS AND 4AS/74AS DEVICES VCC 7 V RL = R = R2 S RL From Output Under Test CL (see Note A) RL Test Point From Output Under Test CL (see Note A) Test Point From Output Under Test CL (see Note A) R R2 Test Point LOAD CIRCUIT FOR BI-STATE TOTEM-PO OUTPUTS LOAD CIRCUIT FOR OPEN-COLCTOR OUTPUTS LOAD CIRCUIT FOR -STATE OUTPUTS Timing Input High-Level Pulse Data Input tsu th Low-Level Pulse tw TAGE WAVEFORMS SETUP AND HOLD TIMES TAGE WAVEFORMS PULSE DURATIONS Output Control (low-level enabling) Waveform S Closed (see Note B) tpzl tphz tplz tpzh Waveform 2 S Open (see Note B) 0 V TAGE WAVEFORMS ENAB AND DISAB TIMES, -STATE OUTPUTS Input In-Phase Output Out-of-Phase Output (see Note C) TAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform is for an output with internal conditio such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditio such that the output is high except when disabled by the output control. C. When measuring propagation delay items of -state outputs, switch S is open. D. All input pulses have the following characteristics: PRR MHz, tr = tf = 2, duty cycle = 0%. E. The outputs are measured one at a time with one traition per measurement. Figure. Load Circuits and Voltage Waveforms 6 POST OFFICE BOX 60 DALLAS, TEXAS 726

7 IMPORTANT NOTICE Texas Itruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditio of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specificatio applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ( CRITICAL APPLICATIONS ). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITAB FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK. In order to minimize risks associated with the customer s applicatio, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applicatio assistance or customer product design. TI does not warrant or represent that any licee, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not cotitute TI s approval, warranty or endorsement thereof. Copyright 998, Texas Itruments Incorporated

SN54ALS573C, SN54AS573A, SN74ALS573C, SN74AS573A OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

SN54ALS573C, SN54AS573A, SN74ALS573C, SN74AS573A OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS -State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout True Logic Outputs Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), Standard Plastic (N)