PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces

Transcription

1 CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces Doc. No Rev. *H Cypress Semiconductor 198 Champion Court San Jose, CA

2 Copyrights Cypress Semiconductor Corporation, This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ( Cypress ). This document, including any software or firmware included or referenced in this document ( Software ), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress s patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ( Unintended Uses ). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ- USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 2

3 Contents 1. Introduction Overview PowerPSoC Firmware Design Guidelines Lighting Control Interface: DMX Lighting Control Interface: DALI PowerPSoC Firmware Design Guidelines Design Platform Overview Traditional Method PowerPSoC Method Design Procedure Component and Parameter Selection Device Configuration Accompanying Firmware Summary Lighting Control Interface: DMX DMX512: The Standard DMX512: The System PowerPSoC Solution for DMX Overview Firmware: High-Level Overview Implementation with PSoC Designer Generate Configuration Files and Update main.c Hardware Interface Lighting Control Interface: DALI DALI Receiver Using PowerPSoC PowerPSoC Platform Advantage DALI Receiver Design DALI Signal Decoding Multichannel DALI Receiver Using Cypress DALI Library Cypress DALI Library APIs Using Cypress DALI Library in PSoC Designer Code Example Using CY3267 PowerPSoC Lighting Evaluation Kit Hardware and Software Requirements Code Example Demonstration CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 3

4 Contents 4.5 Summary Appendix A DALI Interface Board Appendix B DALI Standard B.1 DALI System B.2 Addressing Schemes B.2.1 Individual Addressing B.2.2 Group Addressing B.2.3 Broadcast Addressing B.3 DALI Commands B.4 DALI Bus Setup B.4.1 Packet Structure B.4.2 Notes Appendix C DALI Control Gear Command Library Appendix D Steps to Create the Code Example CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 4

5 1. Introduction The Cypress Programmable System-on-Chip (PSoC ) family of devices is well established in programmable mixedsignal microcontroller based devices. The traditional method to implement power management systems involves the use of a similar system-on-chip to interface with high-power discrete devices such as constant current drivers and MOSFET switches. PowerPSoC devices combine the classic PSoC core with high-performance power electronics. The result is an integrated, intelligent, power electronics solution in a single QFN package. The intent of PowerPSoC is to significantly reduce the cost, part count, and board space to implement high-brightness light emitting diode (HB-LED) drivers while retaining performance. This family of devices (CY8CLED04D01) combines up to four independent channels of constant current drivers. These drivers feature hysteretic controllers with a PSoC core that contains an 8-bit microcontroller, configurable digital and analog peripherals, and embedded flash memory. PowerPSoC operates at voltages from 7 to 32 V and can drive up to 1 A of current using internal MOSFET switches. The current drive can be extended to over 1 A with external MOSFETs. For added flexibility, PowerPSoC supports the commonly used power management topologies such as buck, boost, and buck-boost to meet a variety of application requirements. The control loop formed by the internal current sense amplifiers (CSAs) and hysteretic controllers (with inbuilt DACs and high-speed comparators) allows a maximum switching frequency of 2 MHz. Hardware modulators (including the Cypress PrISM) interface with the constant current driver channels and enable the modulation of high-brightness LEDs. There are additional standalone DACs and high-speed comparators that, with the trip capability of the hysteretic controller, provide independent protection to the system and device in case of abnormal conditions, such as overcurrent, overtemperature, and overvoltage. PowerPSoC also features an internal auxiliary regulator that powers the PSoC core from the high-voltage input and can power other devices requiring a 5-V supply in the system. The PSoC core present in PowerPSoC is the same powerful and flexible device that exists in the PSoC family of devices. In addition to the 8-bit MCU and embedded flash, there are programmable analog blocks that can implement ADCs, DACs, amplifiers, and filters; and programmable digital blocks that can implement counters, timers, modulators, UARTs, SPI interfaces, and an I 2 C hardware module. These provide the capability to perform intelligent microcontroller functions and to interface with external sensors for temperature, ambient light, and more. The presence of communication blocks allows this device to provide standard lighting communication interfaces such as Digital Multiplex (DMX512) and Digital Addressable Lighting Interface (DALI). 1.1 Overview This guide is divided into two sections. The PowerPSoC firmware design guidelines section describes a step-by-step process to build an HB LED driver using PowerPSoC. It is followed by sections on lighting control interfaces that describe the implementation of the DMX512 and DALI protocols in PowerPSoC PowerPSoC Firmware Design Guidelines This section addresses the new standard of designing a power electronics solution to use PowerPSoC to drive highbrightness LEDs. It presents a brief comparison between the traditional method to implement a power controller with multiple integrated circuits and discrete components, and the new method, which uses software and firmware tools in a single integrated device. This section also describes the configuration of an intelligent power electronics solution for high-brightness LEDs. The simplicity of the design process is demonstrated using the PSoC Designer Integrated Design Environment (IDE). A code example of the implementation is included. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 5

6 Introduction Lighting Control Interface: DMX The impact of the digital revolution on the lighting industry is recent, yet increasing. Many lighting fixtures today have controllable parameters that require a more sophisticated control interface than toggle switches for ON and OFF. This has given rise to digital lighting control interfaces such as DMX512 and DALI. This section introduces the DMX512 communication standard. It describes the implementation of a DMX512 receiver in PowerPSoC. This section also includes an example project for PSoC Designer that implements a DMX receiver in PowerPSoC. The platform used to evaluate this implementation is the CY3267 PowerPSoC Lighting Evaluation Kit Lighting Control Interface: DALI While DMX512 evolved to become a lighting control standard in the entertainment industry (stage lighting), DALI focuses on building lighting applications. This section describes the use of PowerPSoC to implement a DALI receiver system for LED lighting. The platform used to evaluate this implementation is the CY3267 PowerPSoC Lighting Evaluation Kit. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 6

7 2. PowerPSoC Firmware Design Guidelines This section addresses a power electronics solution that uses PowerPSoC to drive high-brightness LEDs. A parallel is drawn between the traditional method to implement a power controller with multiple integrated circuits and discrete components, and the new method, which uses software and firmware tools in a single integrated device. This section also describes the configuration of an intelligent power electronics solution for high-brightness LEDs. 2.1 Design Platform Overview Traditional Method The traditional method to implement a constant current driver uses a microcontroller that generates PWM signals based on firmware control. The PWM signals drive external constant current drivers, which are configured for a target LED current. The power switches are either discrete or internal to the constant current drivers. With this method, you need to choose the different parts of the system carefully, ensuring that they can interact correctly with one another, and base the calculations for the choice of components on average current, ripple percentage, switching frequency, and sense voltage Every time a design criterion changes, the calculations result in the selection of different components. Figure 1 shows the practical implementation of such a design. Notice how the microcontroller section and the constant current drivers are separate with their own associated circuitry. Figure 1. Traditional Method MR16-Based LED Ballast CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 7

8 PowerPSoC Firmware Design Guidelines PowerPSoC Method PowerPSoC implements current control with its integrated hysteretic controllers. The CSA continuously monitors the current through the channel, during both ON and OFF time. To achieve this, there must be access to both sides of the load, so that the switch can be on one side (high side versus low side of the load) and the sensing element (the current sense resistor in this case) can be on the opposite side. A topology in which the load moves between the various elements of the circuit is called a floating load buck. LEDs are loads that lend themselves well to this kind of topology, since they are constant current loads rather than constant voltage loads. PowerPSoC implements the floating load buck topology with a high side sensing element and a low side switch, as shown in Figure 2. To get a better understanding of this implementation, refer to CY8CLED0xx0x: Topology and Design Guide for Circuits using PowerPSoC. Figure 2. Current Control Loop Based on PowerPSoC Hysteretic Controller PowerPSoC DC CSA R Sense Schottky Diode Hysteretic Controller DAC + - S Q Gate Driver HBLED DAC + - R MOSFET Figure 2 shows one channel in the section of PowerPSoC that performs the current control. This is called the hysteretic controller, and it performs the regulation by monitoring the current in real time and appropriately turning the switch on and off. An SR latch performs the gate drive control for the power MOSFET. A pair of high-speed comparators controls the latch. One of the inputs to both comparators is a representative signal of the actual load current. The load current passes through a sense resistor and a CSA inside the PowerPSoC. The CSA amplifies the low voltage across the sense resistor. The output of the CSA is the input to a pair of high-speed comparators. The output of these comparators drives an SR latch that performs gate drive control for the power MOSFET. A pair of DAC converters sets the references for both comparators. The DAC connected to the set (S) input of the latch is programmed with the lower limit. When the current goes below the lower limit, the latch is set. The DAC connected to the reset (R) input of the latch is programmed with the upper limit. When the current rises above the upper limit, the latch is reset. The DAC values can also be controlled by the firmware, which provides dynamic runtime control to the hysteretic controllers and hence the LED current. This type of control is not possible for most discrete constant current drivers. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 8

9 PowerPSoC Firmware Design Guidelines Figure 3 shows the waveforms of the schematic in Figure 2. The red waveform is the voltage across the sense resistor (V SENSE ) amplified by the CSA. When it crosses the limit set on the lower DAC (V UPPER ), it activates the Reset input of the latch. The latch then drives its output low, and it turns OFF the MOSFET, as shown by the blue waveform. The load current starts to decrease, causing V SENSE to decrease. The Set input of the latch is triggered when the load current drops below the limit set on the upper DAC (V LOWER ). This makes the latch output go high, which turns ON the MOSFET again. This process is repeated continuously to maintain the average value of the load current. Figure 3. Waveforms of Hysteretic Controller V UPPER SLOPE = (V i-v o)/l SLOPE = -V o/l V SENSE V LOWER RS FF OUTPUT TIME R INPUT S INPUT Figure 4 illustrates the architecture of the hysteretic controller module in more detail. The CSA, DACs (Ref_A and Ref_B), and latch are shown as previously, but with the addition of the ON/OFF timers. The timers ensure a bare minimum ON and OFF time and gate the Set and Reset signals to the latch. The output of the latch (Q) is gated by the Trip signal and the dimming signal. If the Trip signal asserts, it causes the output of the final gate to be low and keeps the power FET OFF. As shown in Figure 5, the dimming signal envelops the switching regulator signal. HYST_OUT shows the nature of the signal coming out of the gate (and driving the FET). TIME Figure 4. Hysteretic Controller Section of PowerPSoC Lower Limit Comparator Min ON Timer REF_A S Q CSA FN0.x I FB Upper Limit Comparator R REF_B Min Off Timer DIM Modulation Enable Hyst Out Trip Function CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 9

10 PowerPSoC Firmware Design Guidelines Figure 5. Signal Waveforms of Hysteretic Controller REF_B I LED REF_A ON DIM OFF Hyst Out Since the modulators, hysteretic controller, CSA, and power switch are all internal to the device, and configurable through software, the design methodology is different. Figure 6 shows the practical implementation of a four-channel LED ballast based on PowerPSoC. Note that the single device comprises the PSoC core and the constant current drivers. This effectively reduces the component count on the board and hence the overall cost of the system. Figure 6. PowerPSoC Method MR16-Based LED Ballast Figure 7 shows the entire PowerPSoC device as represented in the interconnect view of PSoC Designer. PSoC Designer is a development tool that enables you to configure, customize, and manage the programmable resources and power peripherals in the PowerPSoC device family. It is available as a free download from Along with PSoC Programmer, the development environment helps you to write related firmware, compile, and build projects that are then programmed into PowerPSoC. The interconnect view has two distinct sections: the PSoC core and the power peripherals. The PSoC core has two sections: digital (top) and analog (bottom right). The power peripherals section is in the bottom right. Figure 8 shows a magnified view of the power peripherals section. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 10

11 PowerPSoC Firmware Design Guidelines The interconnect view shows the various blocks inside the power core of PowerPSoC. They align from left to right in the order of progression of the system signals. Figure 7. Interconnect View of PowerPSoC in PSoC Designer PSoC Digital Section PSoC Analog Section Power Peripherals CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 11

12 PowerPSoC Firmware Design Guidelines Current Sense Amplifiers Figure 8. Power Peripherals Modulators Hysteretic Controllers DACs and Comparators Similar to the classic PSoC, the blocks in the PowerPSoC are configurable. There are preconfigured user modules available in PSoC Designer for each block, as well as associated parameters and APIs (similar to PSoC) that enable configuration, even dynamically during run time. The CSA blocks are designated as CSA, the modulators as MOD, and the hysteretic controllers as HYSTCTRL. The power FETs are also shown separately, although they are part of the Hysteretic Controller User Module. In addition, separate DACs and comparators are shown, which can be used for system monitoring and protection functions such as overcurrent and overtemperature shutoff. Note that these DACs are different from the reference DACs (not shown) that are part of the hysteretic controller. The reference DAC settings are part of the Hysteretic Controller User Module properties. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 12

13 PowerPSoC Firmware Design Guidelines 2.2 Design Procedure This application note assumes that you are familiar with developing applications using PSoC Designer. If you are new to PSoC, refer to AN75320 Getting Started with PSoC 1. If you are new to PSoC Designer, visit the PSoC Designer home page Component and Parameter Selection 1. Before you can configure the chip and write firmware, you must execute a design procedure that considers the circuit parameters and components, as depicted in Figure 9. Refer to CY8CLED0xx0x: Topology and Design Guide for Circuits using PowerPSoC for details and a design example of how to choose the components of a floating load buck circuit such as the inductor, Schottky diode, capacitor, and sense resistor. Figure 9. Firmware Design Flow Start Set up and configure feedback Set up and configure dimming modulator Set up and configure hysteretic controller Set up global configuration parameters Start feedback modules Start hysteretic controller and gate driver Stop CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 13

14 PowerPSoC Firmware Design Guidelines 2. Consider the following parameters and components with respect to the firmware design: a. Average current b. Ripple percentage c. Sense resistor value d. Selection of the sense resistor (R SENSE ) is a tradeoff between the desired sense voltage and power loss in the resistor. In addition, the sense resistor must be chosen so that the voltage across it is under 150 mv. For example, a 0.2-Ω resistor for a 1-A current exceeds the limit. In this case, you must use a smaller sense resistor (for example, 0.1 Ω). The large gain of 20 on the CSA enables a small sense resistor. For instance, at a current of 1 A with a resistor of 0.1 Ω, the voltage across the resistor is 100 mv. A gain of 20 brings this up to 2 V. Therefore, to reduce power loss, the sense resistor can be small. It is also preferable to keep the DAC references close to half the level of the full-scale voltage to give headroom on either side. 3. You also need to select the hysteretic controller s DAC references. Equation 1 represents the relationship of the DAC reference parameters. Equation 1 Where: R SENSE = Sense resistor value I LOW = I AVG (I AVG Ripple % / ) I HIGH = I AVG + (I AVG Ripple % / ) Gain CSA is the CSA gain. DAC Setting and DAC Full Scale Voltage are explained in step 4. For example, a 20 percent ripple and 1 A average current yields: I LOW = 1 (1 (20/100) 0.5) = 0.9 A I HIGH = 1 + (1 (20/100) 0.5) = 1.1 A 4. The DACs inside the hysteretic controller have a choice of two full-scale voltage levels: 1.3 V or 2.6 V. The 1.3-V mode has a smaller resolution step of 5 mv, while the 2.6-V mode has a resolution step of 10 mv. To calculate this value, rewrite Equation 1 to solve for the DAC Setting: Equation 2 If I AVG = 1 A, R SENSE = 0.1 Ω, and Gain CSA = 20 (recommended), the current swings between 1.1 and 0.9 A. The sense voltages are 2.2 V and 1.8 V. Therefore, you select the DAC Full Scale Voltage range of 2.6 V. DAC HIGH Setting = ( ) / 2.6 = 216, which in hex is 0xD7 DAC LOW Setting = ( ) / 2.6 = 176, which in hex is 0xB0 Note that the result obtained from Equation 2 is not a round number. You must round the result before configuring the DAC in the firmware. In practical implementations, the resolution of the DAC and tolerance of the resistor affect the actual load current level. Hex values are acceptable as parameters when using the APIs to modify the DAC references. When using the interconnect view to set the DAC references, use the decimal form. Perform dimming with one of the available digital modulators or by linear dimming, where the load current varies to vary intensity. PowerPSoC can perform linear dimming because the firmware can dynamically change DAC references. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 14

15 PowerPSoC Firmware Design Guidelines Device Configuration Create the Project 1. Open PSoC Designer. From the Windows desktop, choose Start > All Programs > Cypress > PSoC Designer version > PSoC Designer version. 2. From PSoC Designer, choose File > New Project. Type a name for your example project, and then click OK. 3. Click the Device Catalog button to open the Device Catalog. 4. Select Lighting under Device Type, and locate a device with a part number ending in D0X or G0X. The Device Type selection is in the top left corner of the dialog box. Figure 10 shows the Device Catalog with the CY8CLED04D01 device (four channels with 1 A per channel integrated FETs) selected. A description of each device appears in the device datasheet. Figure 10. Device Catalog 5. Click the checkbox next to the device to select the part. Click Create Project with CY8CLED04D01-56LTXI button to create the project. PSoC Designer creates the project and the associated workspace and opens the chip interconnect view. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 15

16 PowerPSoC Firmware Design Guidelines Place User Modules 1. In the User Modules panel, expand the Power folder, shown in Figure 11. This section contains the list of user modules that are unique to PowerPSoC. Figure 11. User Modules Power 2. Double-click the CURSENSEHW User Module (UM). You can also right-click the module name and select Place. The UM appears in the interconnect window as shown in Figure 12. PSoC Designer places the CSA UM in the first available empty slot in the window. In this case, it names the object CURSENSEHW_1. Figure 12. Placement of CURSENSEHW User Module 3. If it is not open already, choose View > Parameters Window. You can use the Parameters window to rename the object. The only parameter for the CSA UM is Bandwidth, as shown in Figure 13. There are multiple settings for the Bandwidth parameter. The selected setting depends on the switching frequency. At higher frequencies, a higher bandwidth is warranted. Set the parameter to Highest. At lower frequencies, setting the bandwidth lower can provide better noise immunity to the amplifier. You can also use API calls in the firmware to configure the Bandwidth setting during run time. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 16

17 PowerPSoC Firmware Design Guidelines Figure 13. Configuration of CURSENSEHW User Module 4. Select and place a modulator in the MOD block. There is a choice of PWM16HW, PrISM16HW, or DMM16HW based modulators. They are all signal density based digital modulators (up to 16 bit) but perform the modulation in different ways. Detailed information about each of the modulators is available in the user module datasheets: PrISM16HW, PWM16HW, and DMM16HW. Select and place the PrlSM16HW User Module, as shown in Figure 14. It occupies the first available MOD block. To open a datasheet, right-click the user module, and select Datasheet. Figure 14. Placement of PrISM User Module 5. The PrISM (Precision Illumination Signal Modulation) modulator uses a Cypress patented stochastic signal density modulation (SSDM) technique to achieve signal density modulation while spreading the frequency spectrum of the output. You can use PSoC Designer for one-time configuration of the modulator, or use the firmware to reconfigure it dynamically. The modulator block has several configuration options: a. ClockScaler: Configure in the user module Parameters window, shown in Figure 15. It represents the final input frequency of the MOD block. The output frequency of the PrISM block depends on the input frequency: F IN = MOD Clock / ClockScaler. The maximum output frequency is F IN /2, and the minimum is F IN /(2n 1), where n is the dimming resolution in bits. For this example, set the ClockScaler parameter to 30. As a result, F IN = 800 khz. This means F OUT(MIN) = 800 khz/255 = 3.14 khz, and F OUT(MAX) = 800 khz/2 = 400 khz. This setting avoids flicker and yet switches slower than the switching frequency (assumed at 1 MHz). Flicker refers to the perception of the eye. As long as the LED turns on and off faster than 120 Hz, the persistence of vision of the human eye makes it appear that the LED is continuously on. Figure 15. Configuration of PrISM User Module CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 17

18 PowerPSoC Firmware Design Guidelines b. DimmingResolution: Configure in the Parameters window. It represents the bit-width of modulation. For instance, for an 8-bit modulator, the value is 8. For this example, set the DimmingResolution parameter to 8. c. SignalDensity: Refers to the duty-cycle equivalent of the PWM output. The duty cycle percentage is (Signal Density + 1) / (2 Dimming Resolution). A value of 127 corresponds to an overall signal density of 50 percent (( ) / 28). You can change this parameter in the firmware or set to a particular value for startup of the LEDs. For this exercise, set the SignalDensity to 127. d. CompareType: For this exercise, set it to Less Than. 6. Select and place the HYSTCTRL User Module, as shown in Figure 16. The configuration of this module, shown in Figure 17, is very important. Figure 16. Placement of HYSTCTRL User Module Figure 17. Configuration of HYSTCTRL User Module 7. In the HYSTCTRL_1 Parameters window, configure as follows: a. GateDriverStrength: For this exercise, set to Default. The default gate drive strength is sufficient to drive a MOSFET with a gate capacitance of 4 nf with a rise/fall time specified in the datasheet. Therefore, the 50 percent option drives half the impedance with the same rise/fall time. b. RefHigh: Sets the high trip point of the hysteretic controller or the two DAC references. For this exercise, it is not necessary to configure this option immediately. You can use the firmware to configure it latert. If required for your application, enter the decimal DAC HIGH Setting calculated in step 3 of section In this example, the DACs are configured for 175 ma with a 30 percent ripple. c. RefLow: Sets the low trip point of the hysteretic controller or the two DAC references. For this exercise, it is not necessary to configure this option immediately. You can use the firmware to configure it later. If required for your application, enter the decimal DAC LOW Setting calculated in step 4 of section d. FeedbackInput: Denotes the current feedback to the hysteretic controller. For this exercise, set to CSA0, as shown in Figure 17. The parameter includes the option to use the corresponding CSA or a function pin. This allows the use of an external feedback mechanism. e. DACVoltageRange: Controls the voltage operating range of the DAC. Set to the values used to configure the DAC references. The options are 1.3 V with a 5-mV step, and 2.6 V with a 10-mV step. You can also use API calls in the firmware to configure these parameters dynamically. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 18

19 PowerPSoC Firmware Design Guidelines f. DimInput: Provides the option to modulate the channel with any of the internal modulator blocks, or from an external modulator through one of the function pins. Set the DimInput to MOD0. g. TripInput: Used when the detection of a certain condition needs to shut down the system loop. One of the auxiliary comparators or an external input through the Function IO pins provides a trip input to the hysteretic controller. These comparators can have one of their inputs fed from the auxiliary DACs as references. The other input should be from the fault detection circuit. For instance, a thermistor can sense an overtemperature condition and feed to one of the comparators. Trip function is not used in this example, and hence set it to VGND. Note that the configuration of the DimInput and TripInput parameters is represented by actual connections in the interconnect view, as shown in Figure 18. h. TimerDelay: Sets the monoshot timer delay for both the on and off timers. Possible choices are no delay, ns delay, ns delay, or ns for both on and off timers. For this example, set to NoDelay. When the current goes from the peak to the valley (or vice versa) faster than the loop can respond, these timers are necessary to ensure that the hysteretic controller does not keep the switch continuously on or off. i. GateDriver: Configures the operation of the gate drivers. Possible choices are disable, internal driver enabled, or external driver enabled. For this exercise, set to Internal to use the internal FETs. When gate drive pins (GDx) are used to drive the external FETs, set this option to External. 8. Configure the other three hysteretic control channels in the same way as for the first channel. The average currents can be varied for the other channels, if desired. The final interconnect view in Figure 18 shows how one channel must look at the end of placement and configuration of all modules. Figure 18. Final Interconnect View of Power Core for One Channel Figure 19. Placement of CMPHW User Module 9. There are standalone hardware comparators (Figure 19) in the power core. Current or dimming control does not require these comparators, which frees them for additional functionality such as over-current or over-temperature protection. The comparator can monitor inputs from the CSA or from one of the function pins to monitor external signals. Use function pins or the standalone DACs to obtain the other input (reference). The properties window of the CMPHW User Module shown in Figure 20 demonstrates a possible configuration of the user module. The Fast mode is useful when a very fast hardware response is necessary, such as for overcurrent monitoring. Use the Slow mode when a slower changing parameter, such as temperature, is monitored. The Slow mode uses less power. In addition, you can enable the 10-mV hysteresis in both Slow and Fast modes. For more information on the parameters, refer to the CMPHW User Module datasheet. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 19

20 PowerPSoC Firmware Design Guidelines Figure 20. Configuration of CMPHW User Module Add Standalone DualDAC8HW User Modules To work with these comparators, use the standalone DualDAC8HW User Modules. These DACs provide a reference to the comparators for protection functions. Using the same method as described previously, place a Dual DAC module, as shown in Figure 21. Figure 21. Placement of DualDAC8HW User Module The significant configurable parameter of the DualDAC User Modules is VoltageRange, as shown in Figure 22. For the 2.6V Mode, the steps are in 10-mV increments. For the 1.3V Mode, the steps are in 5-mV increments. The 8-bit data for each of the DACs is written through firmware API calls (for example, when data = 0x80, the voltage is 1.3 V with the 2.6V Mode setting and 0.65 V for the 1.3V Mode setting. For this example, set VoltageRange to 1.3V Mode. Figure 22. Configuration of DualDAC8HW User Module CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 20

21 PowerPSoC Firmware Design Guidelines Configure Global Resources Settings Figure 23 shows the Global Resources settings in the interconnect view. The last five parameters are significant to PowerPSoC in particular. Figure 23. Global Resources Parameters AINX Connection: Connects any of the four CSAs to the analog bus. This enables an ADC to monitor the load current. AINX Mode: Configures the amount of bias current used to bias the modules in the power core. MOD Clock: Provides the reference clock to all the modulator blocks. There is an option of 24 MHz or 48 MHz, denoted by SysClk or SysClk*2. For this example, set the Mod Clock parameter to SysClk. Bias Generator: Enables or disables the current bias generator. Set to Enable for the power peripherals to function. Switching Regulator: Enables or disables the 5-V regulator. Refer to the Technical Reference Manual for the correct use of the regulator and its relationship with software. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 21

22 PowerPSoC Firmware Design Guidelines Generate Configuration Files and Update main.c 1. From PSoC Designer, choose Build > Generate/Build. PSoC Designer builds the project and generates the configuration files. If there are any errors, the related messages will appear in the output panel. 2. From the Workspace Explorer, expand the PPSoC_Example [DeviceName] folder, as shown in Figure 24. Expand the PPSoC_Example folder. Expand the Source Files folder. If the Workspace Explorer is not visible, choose View > Workspace Explorer. Figure 24. Workspace Explorer View 3. Double-click main.c. The main source file opens in its own tab with two header files included and an empty main function defined. 4. Copy the following code into main.c. This code starts up all the modules. /* Include part specific constants and macros */ #include <m8c.h> /* PSoC API definitions for all User Modules */ #include "PSoCAPI.h" void main(void) { /* Enable global interrupts */ M8C_EnableGInt; CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 22

23 PowerPSoC Firmware Design Guidelines /* Start each of the current sense amplifiers */ CURSENSEHW_1_Start(); CURSENSEHW_2_Start(); CURSENSEHW_3_Start(); CURSENSEHW_4_Start(); /* Start each of the PRISM modulators */ PRISM16HW_1_Start(); PRISM16HW_2_Start(); PRISM16HW_3_Start(); PRISM16HW_4_Start(); /* Finally start the hysteretic controllers */ /* Note that these modules are to be started only after the CSA is turned ON */ HYSTCTRL_1_Start(); HYSTCTRL_2_Start(); HYSTCTRL_3_Start(); HYSTCTRL_4_Start(); /* Loop forever */ while(1); } Note the startup sequence of the user modules in these function calls. In the type of high-power system that PowerPSoC typically operates, it is important that the feedback and control systems are on before the current drivers turn on. This is called sequencing. In this case, the CSAs must start before the Hysteretic Controller User Modules. If only one channel is being started up, the hysteretic controller could start up before the CSA finishes starting up. To avoid this, insert a small delay in the firmware between CURSENSEHW_1_Start() and HystCtrl_Start(). 5. Choose Build > Build Project. PSoC Designer compiles and links all the files required by the project. A valid C compiler (ImageCraft) must be installed on the build computer; otherwise, a build error occurs. PSoC Designer comes with a free ImageCraft version. Once the project builds without any errors or warnings, then it is ready to be programmed onto the device. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 23

24 PowerPSoC Firmware Design Guidelines 2.3 Accompanying Firmware This application note includes a PSoC Designer project attached as a zip file that implements the configuration and firmware described in the previous section. The project drives all four RGBA LEDs on the PowerPSoC evaluation board with a current of 175 ma and 30 percent ripple. The dimming modulation is set to a duty cycle of 50 percent. The CY3267 PowerPSoC Lighting Evaluation Kit (Figure 25) is the ideal platform to evaluate the device. It has an ISSP header for programming, the PowerPSoC on-chip debugger (OCD) device CY8CLED04DOCD, a debug port to enable debugging, and four channels of LEDs. Additionally, it has CapSense buttons connected to PowerPSoC GPIO pins. Figure 25. CY3267 PowerPSoC Lighting Evaluation Kit You can open the project in PSoC Designer, and then build the project and program the board to quickly demonstrate the capabilities of the device and firmware. The project, when built with the ImageCraft compiler, occupies 2.5 KB (out of a total 16 KB) of flash memory and 26 bytes (out of 1 KB) of RAM. To program the device with the attached firmware, use a MiniProg1 programmer (part of the CY3210 kit) or MiniProg3 programmer (part of the CY8CKIT-002 kit). Follow these steps to program the device: 1. Use the USB cable to connect the MiniProg to the PC. 2. Connect the MiniProg to the ISSP header (5-pin header) on the board. 3. In PSoC Designer, choose Program > Program Part. 4. In the Program Part dialog box, verify that the Port Selection field shows the connection to a MiniProg1 or MiniProg3, as shown in Figure If the board is not powered yet, set the Acquire Mode option to Power Cycle. If the board is powered, set the Acquire Mode option to Reset. 6. Verification can be either setting. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 24

25 PowerPSoC Firmware Design Guidelines 7. Use the Power Settings drop-down list to select 5.0 V. 8. Click the Program button (bottom right corner of the dialog box). Wait until the progress bar is finished. On completion, the status displays the phrase Program Finished Figure 26. Program Part 9. If the board is not yet powered, then supply power to the board. When it is fully operational, all four LEDs are on. Note For a custom board, use an ISSP header and an OCD-enabled device to enable easy debugging and programming. For more information on OCD parts and debugging, refer to AN73212 Debugging with PSoC Summary PowerPSoC offers a powerful new method of designing high-power systems together with intelligence using software tools. The combination of the well-established PSoC core along with high-performance power electronics enables integrated, low-cost, small designs that differentiate products from others that use conventional methodologies. The firmware example project shows how simple it is to get an HB-LED driver circuit up and running. In addition, easy configuration of the circuit using the firmware allows quick and inexpensive design cycles. This results in quick time to market for end products. The flexibility of the device to be a part of different power management topologies means that a single platform can be used for a wide variety of applications. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 25

26 3. Lighting Control Interface: DMX 3.1 DMX512: The Standard DMX512 is a standard for digital communication networks that are used to control stage lighting. The DMX512 standard covers electrical characteristics, data format, data protocol, and connector type. The most important aspects pertaining to the implementation of the receiver/transmitter are the data protocol and format. The data is transmitted in discrete packets, with 513 slots of data in each packet. Figure 27 shows the format of a packet in the form of a timing diagram. The first slot or byte contains the start code, and the remaining 512 bytes contain dimming data for the interconnected devices. The standard specifies a maximum of 512 slots in each packet. The idle state of the bus is high, called mark. The packet starts with a period of low, called break, followed by a high (mark). The actual byte then starts with the LSB, followed by two stop bits. The slot ends with a mark (high) before the next slot starts. Figure 27. DMX512 Packet Breakdown * *Source E1.11-USITT DMX512-A Standard The bit rate is 250 Kbps, and the refresh rate for the packet (with 512 slots) is typically 44 Hz. From the receiver s perspective, the time allotted for a break before a packet is between 88 and 176 µs. The standard states that the electrical specification is followed according to the EIA-485 standard (differential signaling). The interface between the physical layer devices and the cables is specified to be 5-pin XLR connectors. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 26

27 Lighting Control Interface: DMX 3.2 DMX512: The System The typical DMX512 system is a DMX host that controls up to 512 receivers. The DMX512 standard specifies a unidirectional flow of data to the controlled element (the light fixture) to modulate its intensity. However, the latest version of the standard enables the optional implementation of enhanced function topologies using alternate start codes (non-null), which enables bidirectional data. The host has a DMX512 transmitter that assembles the packet and transmits it over the bus, as shown in the packet structure in Figure 27. The host also includes an EIA-485 (RS485) PHY that interfaces to the actual wires. Figure 28 represents a typical DMX512 system. The multiple receivers connect to the DMX host in a daisy-chain manner, and every packet goes through every receiver in entirety. At each receiver, a PHY receives the differential signal and then gives it to the receive side controller. Each receiver is programmed with a specific slot address so it knows which slot it has to extract from each packet. The receiver can also extract multiple slots from every packet and thereby control more than one light fixture or more than one attribute of a light fixture. Figure 28. Representation of a Typical DMX512 System Each receiver can control one or many light fixtures DMX512 Host (Transmitter) DMX512 Receiver 1 DMX512 Receiver 2 DMX512 Receiver N Each packet goes through every receiver in the 'daisy-chain' N < PowerPSoC Solution for DMX Overview The PowerPSoC solution for a DMX512 system involves implementation of the receiver that controls the light fixtures. The PowerPSoC device offers the following features: Dynamically sets the address during run time Extracts the required data (possibly multiple slots or bytes) from every received packet and stores it in a buffer Extracts the start code of every packet to enable slot data to be processed Dims the HB-LED based light fixtures using internal hysteretic-controlled constant current drivers according to the dimming data received If data is in the form of a color coordinate, processes the data using a color mixing algorithm (on the M8C) and drives three or four channels CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 27

28 Lighting Control Interface: DMX Therefore, the PowerPSoC device forms the receiver, controller, and driver in a DMX512-based lighting communication system. Figure 29 shows a representation of the system-level solution using PowerPSoC as the DMX512 receivers. The DMX512 host sends signals based on the RS485 signaling standard. Figure 29. PowerPSoC System Solution Each receiver can control upto 4 lighting fixtures of unique dimming values PowerPSoC Hysteretic controlled constant current drivers with internal FETs modulated by PrISM modules, and DMX512Rx module to receive dimming data from DMX bus (Stores dimming data from packet in RAM for user) RS485 PHY Interfaces to PowerPSoC device and loops DMX signals out to rest of daisy-chain DMX512 Host (Non-Cypress) PowerPSoC Hysteretic controlled constant current drivers with internal FETs modulated by PrISM modules, and DMX512Rx module to receive dimming data from DMX bus (Stores dimming data from packet in RAM for user) RS485 PHY Interfaces to PowerPSoC device and loops DMX signals out to rest of daisy-chain To remaining receivers of daisy-chain The RS485 Physical Layer device first receives the signals. The RS485 has two functions: Convert the RS485 voltage levels to TTL voltage levels compatible with PowerPSoC Retransmit the incoming signals to enable daisy-chaining more receivers The PowerPSoC device receives the packet (through the RS485 PHY) through a GPIO port pin and according to the address programmed. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 28

29 Lighting Control Interface: DMX The receiver then extracts the particular sequence of slots from each packet. These are stored in a buffer memory. The receiver also extracts the start code for every packet and stores it in a buffer. This can be used to determine processing decisions depending on the value of the start code, as required by the DMX512 standard. The dimming values stored in the buffer are passed to the modulator block in the power peripherals section to vary the signal densities of their outputs. Alternatively, if the data is in the form of a color coordinate, it is passed to a colormixing function in the firmware. The outputs of the modulator block are routed to the hysteretic controllers in the power peripherals. A PowerPSoC receiver can control multiple channels of LEDs simultaneously, because it can extract multiple slots of data from a packet Firmware: High-Level Overview Figure 30 shows an overview of the firmware at a higher level of abstraction. Refer to the DMX512 Rx User Module datasheet for more details on configuring the module. The flow chart in Figure 30 demonstrates the simplicity of the firmware required to use the PowerPSoC device as a DMX512 slave. Figure 30. Flow of Firmware Start Initialize: define memory space for extracted slot data Set address of receiver and number of slots to extract NO New packet received? YES Drive LEDs with new dimming values Stop Initialization refers to defining the memory space required by the user module to store the extracted slots of data and providing it the location of such memory space. The memory size also defines the number of slots the module extracts from every packet. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 29

30 Lighting Control Interface: DMX In a continuously running loop: The module changes its address dynamically if requested. The module waits until a packet is received. When it is received, the slots of interest to the receiver are extracted and stored in a previously defined memory space. These values are used to drive the modulators to dim the channels appropriately. This loop can also incorporate the function of checking the value of the start code, if functions other than dimming need to be performed based on non-zero start codes Implementation with PSoC Designer Following are the steps to implement a simple DMX512 receiver to dim the four LEDs on the CY3267 board. The project design uses the CY3267 board to test the receiver implementation. For a different development board or a custom-designed board with a PowerPSoC device, modify the pin connection settings appropriately. Create the Project and Add User Modules 1. Complete the Create the Project procedure as described in the Device Configuration section. 2. In the User Modules panel, expand the Digital Comm folder, as shown in Figure 31. Right-click the DMX512Rx module, and select Place. Figure 31. DMX512Rx User Module The DMX512Rx User Module occupies one basic block (DBBxx) and one communication block (DCBxx), as shown in Figure 32. The communication block is the receiver part of the module, while the basic block is responsible for detecting the start of a packet. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 30

31 Lighting Control Interface: DMX Figure 32. DMX512Rx User Module Occupies One DBB and One DCB 3. Choose View > Global Resources (Figure 33). Set VC1 to 12. Set VC2 to 14. This setting accommodates the frequency requirements for the two blocks of the user module. The communication block must have an input frequency of 2 MHz, and the basic block requires between 135 khz and 166 khz. Figure 33. Setting Clock Resources 4. If the application uses the switching regulator, set Switching Regulator to Enable. On the CY3267 board, the switching regulator is used; hence, set the option to Enable. 5. Right-click the user module and then select Properties to display the Parameters window for the DMX512Rx User Module. Configure the user module as shown in Figure 34. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 31

32 Lighting Control Interface: DMX Figure 34. DMX512Rx Properties Note The StartSlotID is set to 1. This can be reset to the desired address or dynamically changed in the firmware. 6. There are four channels of hysteretic-controlled constant current drivers with internal FETs that can be modulated by any of the three types of modulators. The signal density of these modulators changes dynamically, using the information received by the DMX512 User Module. The CY3267 board has four channels. The board supports an input voltage of 32 V, with one LED in each channel driven at 350 ma. For detailed instructions on configuring the channels, follow the steps in the Device Configuration section. 7. For the DMX512Rx User Module to function correctly, route the GPIO pin that is receiving the DMX signal to the user module s RX block. In this project, it is port pin P1[1]. Route it to the block as shown in Figure 35 using the bus GlobalInOdd_1. Figure 35. Route DMXRx GPIO Pin to DMX512Rx UM Using GlobalInOdd_1 Bus 8. This project uses the DMX512 interface board to daisy-chain more receivers. Therefore, set pin P1[0] to a High Z driver mode, as shown in Figure 36, so that connecting the RX and TX of the RS485 transceiver chip directly loops the input back to the output without influencing the signal. Figure 36. Set P1[0] to High Z to Loop Back Rx to Tx for Daisy Chaining CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 32

33 Lighting Control Interface: DMX Generate Configuration Files and Update main.c 1. From PSoC Designer, choose Build > Generate/Build. PSoC Designer builds the project and generates the configuration files. 2. Code 1 shows an example of the code that can be written in main.c to implement a receiver controlling a threechannel light fixture. Update the main.c file for the project to include the code similar to that in Code 1 as appropriate for your application. Code 1. Example Code for main.c /* Set the number of slots to be extracted from each packet */ #define DMX_RAM_BUF_SIZE 4 /* Define a memory space to hold the extracted slots */ BYTE DMX_RAM_BUF[DMX_RAM_BUF_SIZE]; BYTE DMX_START_CODE; void main(void) { /* (a) Enable global interrupts */ M8C_EnableGInt; /* (b) Inform the DMX512 user module of the location of the buffer to store the slots. */ DMX512Rx_1_SetRamBuffer(DMX_RAM_BUF_SIZE, &DMX_RAM_BUF[0]); /* (c) Configure the DACs of all the hysteretic controllers to set the current ripple. */ /* DACs configured for average current of 300mA with 25% ripple (peak-to-peak) */ HYSTCTRL_1_SetRefHigh(0x42); HYSTCTRL_1_SetRefLow(0x33); HYSTCTRL_2_SetRefHigh(0x42); HYSTCTRL_2_SetRefLow(0x33); HYSTCTRL_3_SetRefHigh(0x42); HYSTCTRL_3_SetRefLow(0x33); HYSTCTRL_4_SetRefHigh(0x42); HYSTCTRL_4_SetRefLow(0x33); /* (d) Start the current sense amplifiers */ CURSENSEHW_1_Start(); CURSENSEHW_2_Start(); CURSENSEHW_3_Start(); CURSENSEHW_4_Start(); /* (d) Start the PrISM modulators */ PRISM16HW_1_Start(); PRISM16HW_2_Start(); PRISM16HW_3_Start(); PRISM16HW_4_Start(); /* (d) Start the hysteretic controllers */ /* This must be the last module to be started in the power peripherals */ HYSTCTRL_1_Start(); HYSTCTRL_2_Start(); HYSTCTRL_3_Start(); HYSTCTRL_4_Start(); /* (e) Start the DMX512Rx user module */ DMX512Rx_1_Start(); /* (f) Enable interrupts for the DMX user module. */ DMX512Rx_1_EnableInt(); while(1) { CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 33

34 Lighting Control Interface: DMX /* (g) Wait for the slots of interest to come through */ while(!dmx512rx_1_bgetslotactivity()); /* (h) Read the start code of the packet */ DMX_START_CODE = DMX512Rx_1_bGetStartCode(); /* (i) If the start code is NULL (for dimming) */ if (DMX_START_CODE == 0x00) { /* Write the values in the buffer to the modulators */ PRISM16HW_1_SetSignalDensity(DMX_RAM_BUF[0]); PRISM16HW_2_SetSignalDensity(DMX_RAM_BUF[1]); PRISM16HW_3_SetSignalDensity(DMX_RAM_BUF[2]); PRISM16HW_4_SetSignalDensity(DMX_RAM_BUF[3]); } } } The first line of the example code determines the number of slots to be extracted, and the second line defines the buffer in memory that holds the slots. The third is a variable to hold the start code of the DMX packet. Inside the main function, the code: a. Enables global interrupts b. Informs the DMX User Module of the memory buffer s location c. Configures the four hysteretic controller DAC references to drive the LEDs with an average current of 300 ma with a 25 percent ripple. The CY3267 board has a sense resistor of 0.22 Ω, and the CSA gains are set to 20. For a detailed explanation of this calculation, refer to Component and Parameter Selection. d. Starts the CSAs, modulators, and hysteretic controllers. The CSAs must start before the hysteretic controllers. e. Starts the DMX512 User Module. f. Enables the DMX512 User Module s interrupts. If necessary, redefine the starting address of the receiver. After the initialization is complete, the remaining code periodically: a. Waits until the required slots arrive b. Reads the start code of the packet c. Only if the start code is NULL (zero), writes the dimming values stored in the memory buffer to the PrISM modules as their signal densities 3. Program the device per the steps in Accompanying Firmware Hardware Interface You can test this project with any off-the-shelf DMX512 controllers. This section highlights the important details of the test hardware developed and used for a DMX512 receiver with PowerPSoC. The controller transmits signals using the EIA-485 signaling protocol. Therefore, there must be an interface circuit between the controller and the PowerPSoC receiver comprising an EIA-485 PHY (see Figure 37 and Figure 38). It translates the EIA-485 differential signals to 5-V TTL signals. As shown in Figure 37 and Figure 38, U1 performs this role. The data out on the TTL side of the PHY (net labeled RO) connects to the DMX512 receiver s input through port pin P1[1] (or any other input pin). Connectors J3 and J4 denote the 5-pin or 3-pin XLR connectors that interface with a DMX bus. The differential signal coming in through connector J3 is the DMX input. The differential signal leaving through connector J4 is the DMX output. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 34

35 Lighting Control Interface: DMX The signal labeled RO is the 5-V DMX signal that goes into PowerPSoC. The signal labeled RE is an active low Receive Enable signal for the DMX receive section. The signal labeled DE is an active high Transmit Enable signal for the transmit section. Resistors R6 and R7 are 120-Ω termination resistors. The interface circuit is also required for ESD and overvoltage protection and must be present for a DMX512- compliant implementation. On the CY3267, P1[1] is accessed through pin 4 of the white programming header, J2. Figure 37. Schematic of a Basic Interface Circuit Between DMX Controller and PowerPSoC Device CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 35

36 Lighting Control Interface: DMX Figure 38. Isolated RS485 Transceiver Design for DMX512 Compliance The DMX512 standard specifies a preferred isolated receiver topology, where the RS485 signal side and the TTL signal side are electrically isolated, including the grounds. The schematic shown in Figure 38 is an example of the kind of interface circuit that is required in a final design compliant with the DMX512A standard. The electrical isolation in this device is taken care of inside the device. The ICs U2 and U3 are for transient voltage suppression, and the transformer is to isolate the power supply for the two signal sides. Power must be given to the LED driver circuits and the PowerPSoC device. On the CY3267 board, this is done by supplying 12 V DC through the power connector onboard. The system is now fully set up. Changing the dimming values of particular slots using the DMX controller causes the respective LEDs to change brightness. On the CY3267 board, this can be seen as changes in the brightness of the red, green, blue, and amber LEDs. Figure 39 and Figure 40 show the CY3267 board when controlled by the DMX512 master. The interface board, whose schematic is shown in Figure 37, is also shown in these pictures. There are XLR connectors to interface to standard DMX equipment. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 36

37 Lighting Control Interface: DMX Figure 39. CY3267 Board Controlled by USB-DMX Controller Figure 40. CY3267 Board with RS485 Interface Board CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 37

38 4. Lighting Control Interface: DALI This section describes the implementation of a DALI receiver system for LED lighting using PowerPSoC. The platform used to evaluate this implementation is the CY3267 PowerPSoC Lighting Evaluation Kit. Refer to Appendix B for an overview of the DALI protocol. Table 1 defines the terms used in this section. Table 1. Terms and Definitions Term DALI Control gear Control device IEC DALI power supply Manchester signaling Digital addressable lighting interface Definition This term is used in the protocol to describe DALI slaves. Examples are LED ballasts and other light fixtures. This term is used in the protocol to describe DALI masters. Examples are DALI dimmers, switches, and sliders. The standard specification that describes the DALI protocol This is a mandatory component in the DALI loop, which powers the DALI bus and maintains the idle high voltage. Biphase signaling used to represent bit 1 and 0 in DALI 4.1 DALI Receiver Using PowerPSoC PowerPSoC devices provide a powerful programmable platform that integrates the DALI receiver IP with hysteretic control and power peripherals for constant current regulation in intelligent LED lighting applications (Figure 41). Figure 41. PowerPSoC System Solution for DALI DALI Enabled Buttons/Slider for on/off and dimming (Control Device) DALI BUS PowerPSoC DALI Receiver DALI Interface Board USB to DALI Bridge USB DALI Power Supply LED Ballasts (Control Gear) The DALI receiver IP controls the DALI control gears on the bus by decoding and executing DALI commands for dimming control and lighting management. The key features of this solution are as follows: CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 38

39 Lighting Control Interface: DALI Decodes and executes DALI commands to support DALI control gears defined in IEC 62386: Part 102 and Part 207 (Optional LED Module Extension) Supports direct ARC power control (to set the dimming value of the ballast directly) and indirect control commands Supports storage of DALI control gear characteristic parameters such as minimum light output level and maximum light output level Supports physical, automatic, and group addressing modes Supports Forward Packet Type II and Backward Packet structures that enable communication between DALI master and DALI slaves on the bus Integrates control for up to four DALI slaves, which enables optimal design of RGBA-based ballasts The Cypress DALI solution consists of a set of library files and functions that implement a DALI receiver on the PowerPSoC platform using PSoC Designer PowerPSoC Platform Advantage There are many benefits to using the PowerPSoC platform to implement a DALI receiver system for control gears. Following are some key advantages: PowerPSoC devices have integrated high-performance power electronics that include 32 V/1 A rated internal FETs, programmable DACs, comparators, hysteretic controllers, and high-side CSAs. This hardware integration significantly reduces BOM cost in DALI-enabled LED ballasts and enables designers to create platforms that can be scaled for multiple designs and applications. The DALI receiver can be easily integrated with other lighting IP such as LED color control (in multi-led systems) and tunable white light solutions with accurate color temperature control. The PowerPSoC platform also integrates the Cypress PSoC core with programmable analog and digital resources that can be used to implement feedback systems based on temperature sensing and optical sensing (color, ambient light, and so on). 4.2 DALI Receiver Design The Cypress DALI library is written in C and compiled using the ImageCraft compiler. The protocol stack resides in the PowerPSoC flash, and the DALI receiver is implemented using timers, GPIOs, and EEPROM. There is also an I 2 C master to communicate with the onboard temperature sensor. Table 2 shows a snapshot of the resource requirements to implement a DALI receiver on a PowerPSoC device. Table 2. PowerPSoC Resource Use for DALI Receiver Flash (ROM) RAM Digital blocks Resource Analog blocks 0 Comm Blocks GPIOs Use Approximately bytes Approximately 374 bytes 2 (two timers) I 2 C (for temperature sensor) 2 (DALI_TX and DALI_Rx) Note that the flash use includes the I 2 C master, which uses approximately 1 KB of flash. The I 2 C master is only necessary if communicating with a temperature sensor for DALI Part 207 support. There are other ways to perform temperature measurement, such as an ADC for reading a thermistor. If DALI Part 207 support is not necessary, another 340 bytes are available. If only one LED channel is necessary, another 400 bytes are available. Configuring the firmware for these different options is explained in Using Cypress DALI Library in PSoC Designer. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 39

40 Lighting Control Interface: DALI While the PowerPSoC platform design works with 5-V signals on its GPIOs, the DALI bus operates at higher voltages (typically 16 V). As a result, an external DALI interface circuit is necessary for the DALI receiver to communicate with the PowerPSoC device on the bus. This is essentially a voltage translation circuit built using opto-couplers. Figure 42 shows a picture of the Cypress DALI interface board. This application note includes attachments with the design files, schematics, and BOM for this board. Schematics of the board are also shown in Appendix B. Figure 42. DALI PHY Reference Design Board 4.3 DALI Signal Decoding In the DALI protocol, bits are transmitted with biphase signaling, also referred to as Manchester coding. When transmitting logic high or bit 1, the master pulls the bus to a low level (approximately 0 V) for the first half bit-period and then pulls the bus to a high level for the second half. The transition is reversed for logic low or bit 0. Figure 43 shows the two bits encoded in Manchester signaling. Comparing the bus level during the two half-bits helps to determine the actual bit value received. Figure 43. Manchester Signaling on DALI Bus The signal decoding scheme in the Cypress DALI receiver system is implemented using an 8-bit timer and two GPIOs: DALI_Rx and DALI_Tx. Both GPIOs are coupled to the DALI bus by the voltage translation circuit. Two types of interrupts are used in the signal decoding process: GPIO interrupt: This is generated at every falling edge of the DALI bus (DALI_Rx pin). The bus is usually high in the idle state, and the first bit of every packet (start bit) is always logic 1. Therefore, the first change in level is a falling edge on the bus, which triggers a GPIO interrupt. GPIO interrupts are also triggered within a packet at every falling edge is to resynchronize the receiver to the received bit stream. Timer interrupt: This is generated when the DALI timer overflows. The period of this timer is one-fourth bit duration (set by a GPIO interrupt) or half-bit duration (set by the previous timer overflow interrupt). The DALI RX pin is read, and the half-bit value is stored. As shown in Figure 44, when the first GPIO interrupt occurs (at the start of a packet), the DALI timer is loaded with a period of one-fourth bit duration. When the timer generates an overflow interrupt, the DALI receiver samples the bus at the middle of the first half-bit, and its period is reloaded with half-bit duration. Thus, the next timer interrupt occurs such that the DALI receiver can sample the bus at the middle of the next half-bit. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 40

41 Lighting Control Interface: DALI Following this, the timer is loaded with a period of half-bit duration. If a falling edge on the DALI bus is encountered, the period of the timer is set to one-fourth bit duration, so that it can resynchronize itself to the edges on the bus. Thus, the interrupts are generated such that the DALI receiver samples the bus at the middle of each half-bit. All the captured half-bits are stored in a buffer, and the actual bit values are obtained by comparing two consecutive halfbits. The end of packet is signaled by an idle state for at least two consecutive bit periods. During this time, there is no GPIO interrupt (no falling edge), and the timer generates six interrupts. This is used by the DALI receiver to determine the end of packet. Figure 44. Manchester Signal Decoding Start Bit Stop Bit Stop Bit GPIO Interrupt (first falling edge) GPIO Interrupts (intra-packet) Resynchronize DALI Timer to edges on the DALI bus DALI Bus Idle DALI RX Line DALI Timer Interrupt occurs at ¼ bit duration after GPIO Interrupt DALI Timer Interrupt occurs ½ bit duration after previous timer interrupt, when no GPIO interrupt in the middle 6 DALI Timer Interrupts with no GPIO Interrupt => end of packet Figure 45 shows the flow diagram of the Cypress DALI library structure. It is a simplified flow chart of the DALI_ManageInterface routine, which is the library's main function. This routine decodes and responds to DALI commands received by the DALI slave. The DALI library uses interrupt-based processing for input data signals on the DALI bus. New packets are processed through interrupts, and Manchester encoding is decoded through software. When a new packet is received, the library determines if the command needs to be executed. Therefore, the first step is to resolve the destination address, that is, determine if the incoming address is a short address or a group address, or if it is a special or broadcast command. The library can control up to four ballasts simultaneously from a single PowerPSoC device. This is set by the value of the constant TOT_NUM_LED in the DALI library (a value from 1 to 4). This feature is useful when the library is installed in a fixture with multiple white LEDs for tunable white light or in multicolor RGBA systems for colored lighting applications Multichannel DALI Receiver Using Cypress DALI Library The Cypress DALI library supports up to four DALI slaves in a single PowerPSoC device. This is particularly useful when a single driver chip is used to control multiple LEDs installed in a single lamp. Other applications include tunable white-light systems where fixtures with a combination of warm and cool-white LEDs are used to achieve a specific shade of white light. It is also useful in multi-led systems such as RGB or RGBA lamps. These systems use dimming control of red, green, blue, and amber LEDs to generate a spectrum of colors. To extend the DALI library to support more than one channel, modify the value of TOT_LED_NUM with a value from 1 to 4. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 41

42 Lighting Control Interface: DALI Figure 45. Cypress DALI Library Flow Chart Start NO New Packet Received? YES Resolve Address; i := TOT_NUM_LED Does the ballast have to execute a normal command? YES Execute the normal command NO Does the ballast have to execute a normal command? YES Execute the special command NO i = i - 1 NO i = 0? YES Manage dimming for all ballasts Stop CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 42

43 Lighting Control Interface: DALI Cypress DALI Library APIs Required DALI Part 102 void DALI_Init(void) Function void DALI_ManageInterface (unsigned char *level) void Current_Monitor_Initialize(void) BYTE Current_Monitor_Test(BYTE channel, BYTE dimmingvalue) BYTE DALI_IsPhysicallySelected (BYTE channel, BYTE isopencircuit) BYTE DALI_GetDimmingCurve(BYTE channel) DALI Part 207 Function void DALI_SetFailureStatus(BYTE channel, BYTE flag) void Temperature_Monitor_Initialize(void) BYTE Temperature_Monitor_Test(void) Optional Function BYTE DALI_IsDataReceived(void) void DALI_SetLampFailure (char channel, char flag) void DALI_SetDeviceType (char channel, char type) void DALI_SetShortAddr (char channel, char addr) Initializes DALI library Purpose Manages the processing of received DALI packets, EEPROM storage, and LED dimming Initializes the current monitor algorithm for detecting the presence of an open circuit Returns the flag OPEN_CIRCUIT if the particular LED channel has an open circuit Returns TRUE if the particular channel is physically selected. This occurs when the channel reports an open circuit and physical selection mode is enabled. Returns the dimming curve type for the given channel. This is used to determine wheter the LED brightness needs to get updated. Purpose Sets the particular failure condition for the appropriate channel. The failure conditions include open circuit and thermal overloads. Initializes the I 2 C User Module for reading the temperature Reads the temperature and returns the failure status of the measurement Purpose Returns TRUE if a valid DALI message has been received. This is used while reading the I 2 C bus to check if a DALI message is received (higher priority) and should be processed. Reports a lamp failure (LEDs in this case) to the library Changes the device type (LED lamps are of type 6) Sets the 6-bit short address of the DALI slave. This function is available only if constant RANDOM_ADDR is commented Using Cypress DALI Library in PSoC Designer To control the different options for the DALI library, edit the following constant values in daliconst.h: If not supporting DALI Part 207, then comment the line: #define DALI_207 Set TOT_LED_NUM (from 1 to 4) to the desired number of channels. The CY3267 hardware does not support all the optional features in DALI Part 207. The features that are supported are in the following line in daliconst.h: #define FEATURES Select the desired DALI_PHYSICAL_MINIMUM_LEVEL. If TX_DALI and RX_DALI lines are normally high, do not comment the define statements for the TX_NORM_HIGH and RX_NORM_HIGH constants. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 43

44 Lighting Control Interface: DALI 4.4 Code Example Using CY3267 PowerPSoC Lighting Evaluation Kit The CY3267 PowerPSoC Lighting Evaluation Kit is a powerful platform to design, develop, and test LED lighting applications using PowerPSoC. It includes the CY8CLED04D01 four-channel PowerPSoC device that drives four independent channels using its internal FETs, hysteretic controllers, comparators, and DACs. The CY3267 has one LED per channel. The attached code example illustrates the use of the Cypress DALI library in PowerPSoC to implement a DALI receiver with four DALI slaves, corresponding to the four high-brightness LEDs on CY3267. Steps to re-create the code example are provided in Appendix D. The code example allows you to easily enable or disable the optional DALI Part 207. In main.c, there are two versions of the main function: one that supports Part 207 and one that does not. The main.c file highlights the following: Use of DALI_Init function to initialize the DALI library in main() Use of DALI_ManageInterface function to process commands from the DALI bus Use of the current monitor commands to detect an open circuit for physical selection and DALI Part 207 failure status Use of the temperature monitor commands to detect a thermal overload condition for DALI Part 207 failure status and LED brightness adjustment Setting up the four power channels to drive each of the four LEDs at a constant current of 300 ma and 20 percent ripple The comments in the code explain all the commands used to implement the DALI library Hardware and Software Requirements The setup for the DALI loop that is used to demonstrate the code example requires the following key components: CY3267 PowerPSoC Lighting Evaluation Kit Tridonic DALI USB Controller: Enables a PC-based GUI to send out DALI commands on the bus and control the LED. DALI Power Supply: Provides power to the DALI bus. This example uses the Tridonic DALI-BM-RS-232. DALI PHY Board: This interface board translates the high-level voltages on the DALI bus to 5 V on the PowerPSoC device. This board has a pair of screw terminals on one end that connect to the DALI bus. The other end has a 5-pin 100-mil female connector that mates with the 5-pin header J12 of the CY3267. Pins P1[0] and P1[1] are used as the DALI RX and TX pins. configtool v1.5 software from Tridonic: Enables the PC to be the DALI master to send commands to the DALI receiver on PowerPSoC. Download from CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 44

45 Lighting Control Interface: DALI Code Example Demonstration To see a working demonstration of the example, build the attached code example using the ImageCraft compiler in PSoC Designer, and program the hex code into the CY3267 PowerPSoC Lighting Evaluation Kit. 1. Connect the DALI USB controller, power supply, the interface board, and CY3267, as shown in Figure 46. Figure 46. Demonstration of DALI on CY Use a USB cable to connect the DALI USB Controller to a PC running configtool v Power ON all the components (the DALI power supply and the CY3267). 4. On the PC, launch configtool. This software enables the PC to interface with the Tridonic DALI USB Controller to function as the DALI master. The software has two tabs: Serial Interface and DALI Device Programmer. 5. In the configtool Serial Interface tab, select the appropriate port, as shown in Figure 47. When a valid controller is found, the software displays the phrase DALI USB Interface. Figure 47. Select DALI USB Interface CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 45

46 Lighting Control Interface: DALI 6. Click the DALI Device Programmer tab. In the 6 Steps to a good installation section, click the Test Installation button, as shown in Figure 48. Click the Start Test button. When the test is complete, click the Close button. configtool tests the DALI setup. If everything is set up correctly, all four LEDs blink (turn ON to MAX level, and then set to MIN level). Figure 48. Test DALI Installation 7. In the 6 steps to a good installation section, click the Search Devices button. configtool launches a wizard to search for available DALI devices on the bus and assign a short address to each of them, as shown in Figure 49. The code example has four DALI slaves instantiated by default (using TOT_LED_NUM in daliconst.h file), where each corresponds to one of the four LEDs on the CY3267 board. During this step, the software scans for DALI devices that already have a valid address and assigns a new one to each of the unaddressed devices. When assigning addresses, you can choose between Random Addressing and Physical Addressing. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 46

47 Lighting Control Interface: DALI Figure 49. Search for DALI-Enabled Devices In the DALI Addressing Wizard, click Next to start the wizard. Select Random Addressing and then click Next again. The four LED channels appear in the DALI USB interface list as four DALI slaves, each with a unique short address, as shown in Figure 50. This successfully sets up the DALI loop with the four DALI slaves. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 47

48 Lighting Control Interface: DALI Figure 50. Enumerate DALI Slaves 8. On the DALI Device Programmer tab, click the Adv Settings button. The Send DALI Commands dialog box appears, as shown in Figure 51. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 48

49 Lighting Control Interface: DALI Figure 51. Send DALI Commands 9. Use the Send DALI Commands dialog box to test the Cypress DALI library with any valid DALI command, with any valid addressing mode (Broadcast/Group/short Addr.). 4.5 Summary This section described the implementation of a DALI receiver using Cypress s PowerPSoC devices. DALI is evolving to become the lighting control standard of choice for building lighting applications. The PowerPSoC integrated highperformance power electronics along with its PSoC core can be used to create intelligent DALI-enabled LED lighting fixtures. The attached code example using the CY3267 PowerPSoC Lighting Evaluation Kit demonstrates the use of the Cypress DALI library on PowerPSoC. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 49

50 Appendix A DALI Interface Board Figure 52. DALI Interface Board Reference Design CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 50

51 DALI Interface Board Table 3. Bill of Materials (BOM) Qty Label Value Description Size Manufacturer Mfr Part# 1 C1 1uF-Tant-B 25 V 3 C2,C3,C4 100 nf-0603, 25 V 2 R1,R4 470R R2 6R R3,R7 2K R5 47K R6 1K D1 BAS16-7-SOT23 4 D2,D3,D4,D5 1 D6 1 Q1 1N4148W-7-F- SOD123 BZX284-C2V7- SOD110 BC817-25LT1G- SOT23 1 JP2 3x1 TH Header (M) 1 J1 2x1 screw terminal block 1 J2 5x1 TH Header (F) 2 U1,U2 4N37S-SMD6 1 U3 SN74AHC1G14DB VR-SOT23-5 CAP TANT 1.0UF 25 V 20% SMD CAP.1UF 25 V CERAMIC X7R 0603 RES 470 Ω 1/8W 1% 0805 SMD RES 6.8 Ω 1W 5% 2512 SMD RES 2.70 KΩ 1/8W 1% 0805 SMD RES 47.0 KΩ 1/8W 1% 0805 SMD RES 1.00 K Ω 1/8W 1% 0805 SMD DIODE SWITCH 75 V 350 MW DIODE SWITCH 100 V 400 MW SOD123 DIODE ZENER 400 MW 2.7 V 5% SOD110 TRANS NPN GP 500MA 45 V SOT mm pitch 3x1 through hole header - M Screw Terminal Block 2x mm pitch 5x1 through hole header - M OPTOISOLATOR W/BASE SMD IC SCHMITT-TRG INV GATE SOT23-5 Tant B ( ) 0603 Vishay/Sprague Panasonic - ECG 293D105X0025B2TE3 ECJ-1 B1E104K 0805 Rohm MCR10EZPF Panasonic - ECG ERJ-1TYJ6R8U 0805 Rohm MCR10EZPF Rohm MCR10EZPF Rohm MCR10EZPF1001 SOT-23 Diodes Inc BAS16-7 SOD-123 Diodes Inc 1N4148W-7-F SOD-110 SOT-23 NXP Semiconductors ON Semiconductor BZX284-C2V7 BC817-25LT1G Phoenix Contact SMD-6 LITE-ON INC 4N37S SOT-23-5 Texas Instruments SN74AHC1G14DBVR CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 51

52 Appendix B DALI Standard DALI is a royalty-free, interoperable open standard for digital lighting that is currently drafted as IEC Specification It is a command-based protocol with numerous commands used to control electronic ballasts, that is, electronic devices that control lighting fixtures. These ballasts are also referred to as DALI ballasts. Two key characteristics of all DALI ballasts are the following: Digital: Ballasts can decode and respond to digital data. Addressable: There can be several ballasts on the same lighting network that are individually addressed and controlled. Three key specifications from IEC describe the DALI standard: IEC 62386: Part 101 DALI System IEC 62386: Part 102 DALI Slave (Control Gear) IEC 62386: Part 103 DALI Master (Control Device) In addition to these specifications, DALI also addresses particular requirements for different types of DALI slaves such as fluorescent lamps, LED lamps, supply voltage controllers, and others. Some examples follow: IEC 62386: Part 201 Fluorescent Lamps IEC 62386: Part 202 Emergency Lighting IEC 62386: Part 203 Discharge Lamps IEC 62386: Part 204 Low-Voltage Halogen Lamps IEC 62386: Part 205 Supply Voltage Converter IEC 62386: Part 206 Digital-to-DC Voltage Conversion IEC 62386: Part 207 LED Modules (supported in the attached library) IEC 62386: Part 208 Switching Function IEC 62386: Part 209 Color Control IEC 62386: Part 2010 Sequencer CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 52

53 DALI Standard B.1 DALI System The DALI system uses a two-wire bus-based communication medium. Each DALI loop supports a maximum of 64 control devices or DALI masters and a maximum of 64 control gears or DALI slaves. Typical control devices include switches, scene controllers, dimmers, occupancy sensors, and communication modules that link the DALI bus to other networks such as Ethernet. Examples of control gears are ballasts that drive lighting fixtures such as fluorescent lamps, LED lamps, or halogen lamps. Figure 53 shows a simple DALI loop configuration with 64 slaves (control gears) and one dimming controller (control device). Each slave on the network is assigned a unique individual address. The dimmer sends commands to the ballasts to regulate the lamp intensity. DALI also supports commands for several query functions that retrieve status information from the ballasts. Figure 53. DALI Loop DALI Power Supply DALI employs bidirectional half-duplex asynchronous serial data transmission between nodes on the DALI bus with a data rate of 1200 bits per second. The digital signals on the two-wire bus are Manchester coded with a steady voltage difference between the wires in the range of 9.5 V to 22.5 V (typically 16 V). A voltage difference above 9.5 V represents logic high or 1, while a voltage difference below 6.5 V represents logic low or 0. Figure 54 shows the voltage levels of signals on the DALI bus. Figure 54. DALI Bus Signal Voltage Levels 9.5 V to 22.5 V (16 V typical) 8 V -6.5 V to 6.5 V (0 V typical) Bi-phase logical 1 A DALI power supply powers the DALI bus. It enables a maximum current input of 250 ma on the bus. Each device connected on the bus can consume a maximum of 2 ma. This feature allows the presence of low-power sensors on the network that may not require a separate high-voltage power line. The control gears (DALI slaves) respond to the control devices (DALI masters) by setting the level high or low. A high level is simply achieved by not interfering with the default high level on the bus set by the master. A low level is obtained by forcing a short circuit across the wires. This is possible because the DALI standard mandates the maximum current supply on the bus as 250 ma. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 53

54 DALI Standard B.2 Addressing Schemes The DALI protocol provides three addressing schemes to address DALI slaves on the network. B.2.1 Individual Addressing Ballasts or slaves may be assigned a unique individual address. There are 64 possible addresses (0 to 63). No two ballasts can have the same address on a DALI loop. An individual address command sends commands on a DALI loop to specific ballasts. The ballast with this address responds to the command. An individual address can be either of the following: Short address: An address between 0 and 63 that may be assigned to a device and that is normally used in the individual address command. Random address: This is a sequentially assigned number for a device on the DALI bus, regardless of the physical location, and is typically used during bus configuration. This is a 3-byte address. B.2.2 Group Addressing A group is a collection of addresses. With group addressing, the DALI master can control more than one device simultaneously. A DALI slave can belong to a maximum of 16 groups at once. B.2.3 Broadcast Addressing This scheme enables the controller to select and control all devices on the network. All DALI slaves must execute commands sent with a broadcast address. B.3 DALI Commands The DALI protocol consists of specifications with requirements for DALI masters (control devices) and DALI slaves (control gears). In addition, there are separate sub-specifications with particular requirements for different lighting fixtures such as halogen lamps, LED lamps, fluorescent lamps, and other DALI slaves such as voltage controllers and sequencers. There are three types of commands: Control Device Communication: Used for communication between two or more DALI masters in a network with multiple DALI masters. They are listed in IEC 62386: Part 101. Control Gear Generic Control: Used for communication between a DALI master and one or more DALI slaves on the network. They are listed in IEC 62386: Part 102, which also describes the general requirements common to all DALI slaves. Control Gear Specific Control: Used for communication between a DALI master and specific types of DALI slaves on the network. These commands control properties that are specific to a particular lighting fixture such as LED lamps or fluorescent lamps. They are listed in Parts 2xx of IEC For example, the commands listed in Part 207 are used when the DALI master controls specific properties of DALI-enabled LED lamps on the network. Table 4 in Appendix C lists the control gear generic control commands specified in IEC 62386: Part 102. The Cypress DALI receiver solution implements this library with a few exceptions. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 54

55 DALI Standard B.4 DALI Bus Setup The DALI bus can be defined as an auto-setting bus, because the ballast addresses can be assigned or modified by the DALI master, and the system does not necessarily require hardware methods (jumpers or DIP switches) to set the ballast's short address. Typically, new ballasts on the DALI bus have no short address, and the address is assigned by the DALI master. A short address can be assigned to a DALI slave (control gear) using a start-up sequence via two different methods: random and physical addressing. Random Addressing Initially, all DALI slaves (DALI ballasts) on the bus have no short address (short address = 255 represents no short address assigned). The random address of a DALI slave is 3 bytes long (factory programmed). The probability of two different ballasts on the bus with the same random address is very low. The startup sequence enables the DALI master to determine the random addresses of all DALI ballasts present on the bus and assign a unique short address to each such slave. The master broadcasts a SEARCH ADDRESS (also 3 bytes long) to all DALI slaves on the bus. Then the master queries the bus with a COMPARE command. If a ballast with a random address less than or equal to the search address is present on the bus, it responds to the COMPARE command. All other ballasts remain idle. Based on this procedure, the master executes an optimized search algorithm and determines if there are any DALI ballasts with the chosen Search Address. If no such ballast is found, the DALI master moves on to another Search Address. If the DALI ballast with its random address equal to the DALI master s Search Address is found, then it selects this ballast and assigns a unique short address (0 to 63). This ballast is then excluded from the startup sequence using a WITHDRAW command, and the algorithm continues to assign short addresses to the remaining DALI slaves. Physical Addressing This method is easier than the random addressing mechanism described in the previous section. The master broadcasts an INITIALIZE command followed by a PHYSICAL SELECTION command that puts all the DALI ballasts in the physical addressing method. The user then physically selects the DALI ballast using jumpers, DIP switches, or buttons that physically activate the DALI ballast. When the ballast is physically selected, it responds to the master s queries, and the master can then assign a new short address. The DALI ballasts on the bus must be physically selected in a sequential manner and then assigned short addresses. B.4.1 Packet Structure The DALI protocol uses three types of packets. Forward Packet Type I This packet structure is for communication between two or more DALI masters when there are multiple masters on the bus. The packet consists of the following: 1 start bit 8 bits of address 16 bits of data (commands or data) 2 stop bits Forward Packet Type II This packet structure is used by the DALI master to communicate with one or more DALI slaves on the bus. These packets are commonly used by DALI controllers such as dimmers or switches to control lighting fixtures and other devices on the DALI bus. The packet consists of the following: 1 start bit 8 bits of address 8 bits of data (command or data) 2 stop bits CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 55

56 DALI Standard Backward Packet This packet structure is used by the DALI slave to respond to the DALI master when queried for data. The DALI protocol supports several commands that retrieve status information from DALI slaves. The backward packet structure is used during this process. The packet consists of the following: 1 start bit 8 bits of data 2 stop bits B.4.2 Notes Start and stop bits are logic 1. Each packet is sent continuously without a time lag between successive bytes. The baud rate is 1200 bits per second with Manchester coding. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 56

57 Appendix C DALI Control Gear Command Library Table 4. IEC Part 102 Command Library Code Description 00 the lamp Extinguish without fading 01 Dim up 200 ms using the selected fade rate 02 Dim down 200 ms using the selected fade rate 03 Set the actual arc power level one step higher without fading (arc power level is increased by 1) 04 Set the actual arc power level one step lower without fading (arc power level is decreased by 1) 05 Set the actual arc power level to the maximum value 06 Set the actual arc power level to the minimum value 07 Set the actual arc power level one step lower without fading (arc power level is decreased by 1) 08 Set the actual arc power level one step higher without fading (arc power level is increased by 1) 09 Enable DAPC sequence 10 + scene Set the light level to the value stored for the selected scene 20 Reset the parameters to default settings 21 Store the current light level in the DTR 2A Store the value in the DTR as the maximum level 2B Store the value in the DTR as the minimum level 2C Store the value in the DTR as the system failure level 2D Store the value in the DTR as the power on level 2E Store the value in the DTR as the fade time 2F Store the value in the DTR as the fade rate 40 + scene Store the value in the DTR as the selected scene 50 + scene Remove the selected scene from the slave unit 60 + group Add the slave unit to the selected group 70 + group Remove the slave unit from the selected group 80 Store the value in the DTR as a short address 81 Enable write memory 90 Returns the status of the slave as XX XX 91 Check if the slave is working (YES/NO) 92 Check if there is a lamp failure (YES/NO) 93 Check if the lamp is operating (YES/NO) 94 Check if the slave has received a level out of limit (YES/NO) 95 Check if the slave is in reset state (YES/NO) 96 Check if the slave is missing a short address (YES/NO) 97 Returns the version number as XX XX (the device returns 0x0100, i.e., Version 1.0) 98 Returns the content of the DTR as XX XX 99 Returns the device type as XX XX (default type is 6) CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 57

58 DALI Control Gear Command Library 9A 9B 9C 9D A0 A1 A2 A3 A4 A5 B0 + scene C0 C1 C2 C3 C4 C5 E0 FE FF A1 00 A3 XX A5 XX A7 00 A9 00 AB 00 B1 HH B3 MM B5 LL B7 XX B9 XX BB 00 BD 00 C1 XX C3 XX C5 XX C7 XX Returns the physical minimum level as XX XX Check if the slave is in power failure mode (YES/NO) Query content of DTR1 Query content of DTR2 Returns the current light level as XX XX Returns the maximum allowed light level as XX XX Returns the minimum allowed light level as XX XX Returns the power on level as XX XX Returns the system failure level as XX XX Returns the fade time as X and the fade rate as Y XY Returns the light level XX for the selected scene XX Returns a bit pattern XX indicating which group (0-7) the slave belongs to XX Returns a bit pattern XX indicating which group (8-15) the slave belongs to XX Returns the high bits of the random address as HH HH Returns the middle bit of the random address as MM MM Returns the lower bits of the random address as LL LL Read memory location Application extended commands Query extended version number All special mode processes shall be terminated Store value XX in the DTR Initialize addressing commands for slaves with address XX Generate a new random address Compare the random address with the search address Withdraw from the compare process 8 high bits of the search address 8 mid bits of the search address 8 low bits of the search address Program the selected slave with short address XX Check if the selected slave has short address XX YES/NO The selected slave returns its short address XX XX Go into physical selection mode Enable device type XX Store XX into DTR1 Store XX into DTR2 Write memory location CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 58

59 Appendix D Steps to Create the Code Example This section describes the sequence of steps to implement a DALI receiver in PowerPSoC using the Cypress DALI library and PSoC Designer. If you are not familiar with the PSoC Designer platform, see for on-demand courses and workshops. The code example described here uses the CY3267 PowerPSoC Lighting Evaluation Kit and implements four DALI slave nodes mapped to red, green, blue, and amber LEDs on the board. The PowerPSoC device is programmed and set up as a common DALI receiver for all four nodes and implements the power supply for regulating the current through each of the four LEDs. 1. Create a new project in PSoC Designer for PowerPSoC (CY8CLED04D01), with the following Global Resources settings: 2. Add the following user modules: a. Two Timer8 b. Two EEPROM c. I2CHW Master 3. Rename Timer8_1 to Timer8_DALI, Timer8_2 to systimer, E2PROM_1 to DALI_E2PROM, and EEPROM_2 to GEAR_INFO. 4. Set the size of DALI_E2PROM to 128 bytes and its first block at end of flash (block 254). 5. Set the size of GEAR_INFO to 64 bytes and its first block at 253 (end of flash, just before DALI_E2PROM). 6. Set up the Timer8_DALI period such that its interrupt frequency is as close to 1200 Hz as possible. Preferably select high values for Timer8 Period. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 59

60 Steps to Create the Code Example 7. Configure systimer such that it interrupts every 1 ms. This is used to synchronize the main loop to a 3-ms duration. 8. Set up DALI TX/RX pins. For the attached example: a. Rename P1[0] to TX_DALI and set drive mode to Strong, DisableInt. b. Rename P1[1] to RX_DALI and set drive mode to High-Z, FallingEdge. 9. Set the define statements for constants TX_NORM_HIGH and RX_NORM_HIGH in the dali_int.c file. When this line is commented, the DALI bus is set to the default low level. When retained uncommented, the default level is high. 10. Set up the four power channels as follows: CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 60

61 Steps to Create the Code Example CSA: PWM dimming modulators: Hysteretic controllers: DACs: CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 61

62 Steps to Create the Code Example Comparators: 11. Build the project and generate the configuration files. 12. Add the following files to the project: main.c dali.c dali.h dali_api.c dali_api.h dali_int.c dali_int.h daliconst.h dali_startup.asm Current_Monitor.c Current_Monitor.h HBLED.c HBLED.h Temperature_Monitor.c Temperature_Monitor.h 13. Open template boot.tpl and set up the following interrupt vectors for DALI: 14. GPIO Interrupt Vector: ljmp _DALI_FallingEdgeRxISR 15. DALI_Timer8's PSoC Block: ljmp _DALI_Timer8_DALI_ISR 16. systimer s PSoC Block: ljmp _main_systimerisr 17. In the dali_startup.asm file, the ORG directive represents the start address of the flash area used by the GEAR_INFO and DALI_E2PROM (total size is 256 bytes). For PowerPSoC, this is 0x3F40 and 0x3F80, respectively. 18. Modify the constant values in daliconst.h according to your application. 19. Unlock the last four blocks of the PowerPSoC flash to enable writing into EEPROM. In the file flashsecurity.hex, change the last two occurrences of W in the file flashsecurity.txt to U. 20. Edit the main.c file to include any other application-specific code. 21. Build the project. CY8CLED0xx0x PowerPSoC Firmware Design Guidelines, Lighting Control Interfaces, Doc. No Rev. *H 62