ISA Bus Timing Diagrams

Transcription

1 SBS s ISA bus timing diagrams are derived from diagrams in the IEEE P996 draft specification which were, in turn, derived from the timing of the original IB AT computer. Please note that the IEEE P996 draft specification was never completed by the IEEE and is not an IEEE approved spec. Also, the latest IEEE draft is known to contain errors. In the absence of an approved IEEE specification, manufacturers of PC chip sets attempt to meet a consensus ISA bus standard. This has resulted in minor variations in signal interpretation and timing among the various PC chipset vendors. For this reason, SBS recommends that designers of interfaces to the ISA bus use the minimum number of bus signals needed to perform a required function (e.g. chip selection or signal synchronization). For example, at least one popular chipset does not drive AEN high during REFRESH. In certain instances, SBS has added logic to improve bus timing and/or signal relationships on CPU and peripheral boards. SBS s ISA bus timing diagrams include several corrections relative to the IEEE P996 draft specification. However, since these diagrams are derived from an uncompleted and unapproved IEEE specification, they may contain other errors. For comprehensive technical details on the ISA architecture and bus, SBS recommends the following book: ISA & EISA Theory and Operation, by Edward Solari; published by Annabooks ( This book contains a detailed technical exposition of the ISA and EISA buses and is written by the principal author of the IEEE P996 draft specification. 1

2 REF TYPE SIZE DESCRIPTION DRIVER RECEIVER IN AX IN AX 1 / LA setup to BALE deasserted / BALE pulse width / LA hold from BALE deasserted a 4b LA setup to Ex* asserted LA setup to Ex* asserted 5 / ECS* valid from LA / ECS* hold from LA 0 0 a b c a b c d 10a 10b 10c 10d 11a 11b 11c 11d IO IO IO IO SA, SBHE* setup to Ex* SA, SBHE* setup to IOx* SA, SBHE* setup to IOx* or Ex* Command width Command width Command width with ENDXFR* asserted Command width Read data access Read data access Read data access with ENDXFR* asserted Read data access Write data setup Write data setup Write data setup (even) Write data setup (odd) / SA, SBHE* hold a 13b 13c 15a 15b IO / / / Command deasserted Command deasserted Command deasserted Read data hold Write data hold / Read command to SD disabled ENDXFR* asserted from command IO / IOCS* asserted from SA IO / IOCS* hold from SA a 20b / valid from command asserted valid from command asserted 21 / deasserted pulse width / Command hold from / BALE asserted from command deasserted / Clock period (Tclk) a 25b 26a 26b / Data setup to deasserted (-bit even) Data setup to deasserted (-bit odd) LA hold to Ex* active LA hold to Ex* active 2 ENDXFR* setup to SYSCLK falling edge ENDXFR* hold from SYSCLK falling edge LA setup to ENDXFR* asserted SA setup to ENDXFR* asserted 3 61 Table 1. emory and I/O Timing

3 24 SYSCLK ER* EW* SD<15..0> 12 SA<..0> SBHE* BALE LA<23..1> 5 6 ECS* Note 1 Note 1: timings apply if deasserted. See Figure 4. Figure 1. -bit emory Timing 3

4 IOR*, IOW* SD<15..0> 12 SA<15..0> SBHE* 1 19 IOCS* 23 BALE Note 1 Note 1: timings apply if deasserted. See Figure 4. Figure 2. -bit I/O Timing 4

5 ER* EW* IOR* IOW* SD<..0> SA<19..0> 4 26 BALE LA<23..1> 5 6 ECS* Note 1 Note 1: timings apply if deasserted. See Figure 4. Figure 3. -bit emory and I/O Timing 5

6 SER* SEW* IOR* IOW* SD<15..0> Figure 4. Timing 6

7 SYSCLK 29 ENDXFR* LA<23..1> 3 SA<19..0> 1 EW* ER* 10c c SD<15..0> Note 1: Assertion of ENDXFR* within the maximum time from command is only required for a -bit cycle with zero wait states. Otherwise, ENDXFR* may be asserted at any time during the cycle while command is asserted. Figure 5. ENDXFR* Timing

8 REF DESCRIPTION DRIVER RECEIVER 1a 1b DACKn*, AEN setup to IOR* DACKn*, AEN setup to IORW* IN AX IN AX Address setup to EW*, IOW* a 3b 4a 4b 4c IOR* setup to EW* ER* setup to IOW* Data access from IOR* /bit Data access from ER* bit Data access from ER* bit Data setup to IOW* unasserted Read command hold from write command SBHE*, address hold Data hold from read command a 9b deasserted from bit memory command deasserted from bit memory command TC hold from command unasserted a 11b IOR* pulse width ER* pulse width IOW*, EW* width a 13b 13c DACKn* hold from IOW* DACKn* hold from IOW* AEN hold from command DREQ inactive from IOx* low width Tclk Tclk TC setup to command unasserted Table 2. DA Timing

9 Notes 1 and 4 DRQn DACKn* 2 SA<..0> SBHE LA <23...1> 1a 11 IOR*, ER* 1b IOW*, EW* 4 5 SD<15..0> 10 TC 9 Note 2 15 AEN Note 1: DRQn may be deasserted any time after DACKn* during a block mode DA transfer. Note 2: may be deasserted to insert additional wait states. Additional bus wait states are added in units of two bus clocks. Note 3: The DA controller activates TC during the last cycle of a DA request. Note 4: DA transfers may be broken up into multiple back-to-back cycles where the DA controller removes DACKn* and optionally releases the bus to allow higher priority cycles to occur. In this case, DACKn* will be temporarily deasserted even though DRQn is still asserted. 9

10 Figure 6. DA Timing REF DESCRIPTION DRIVER RECEIVER IN AX IN AX 1 ER* pulse width SA<0...> setup to ER* SA<0...> hold from ER* deasserted from ER* ER* deasserted from REFRESH* setup to ER* REFRESH* hold from ER* (Note 1) SA<11...0> tri-state from ER* high Tclk 9 width Tclk Tclk 10 A ownership delay (Note 2) 2*Tclk 2*Tclk 11 AEN asserted to REFRESH* active AEN hold to REFRESH* inactive REFRESH* asserted to SA<0...> valid REFRESH* hold from SA<0...> valid Address and Control disabled to REFRESH* asserted Table 3. Refresh Timing

11 6 REFRESH* SA<..0> 2 1 ER* AEN Note 1: The temporary master may exceed the maximum REFRESH* hold time in order to conduct another refresh operation. Note 2: The temporary master, if the current master, must tri-state the address and command signals prior to driving REFRESH* high (1). Figure. REFRESH Timing 11