UNIT-IV. The semiconductor memories are organized as two-dimensional arrays of memory locations.

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1 UNIT-IV MEMORY INTERFACING WITH 8086: The semi conductor memories are of two types: Static RAM Dynamic RAM The semiconductor memories are organized as two-dimensional arrays of memory locations. For Ex: 4K*8 or 4K byte memory contains 8-bit data and only one o the 4096 locations can be selected at a time. For addressing 4k bytes of memory, 12 address lines are required. For N memory locations, n address lines are required where n = Log 2 N For 4096 Locations, n = log Note: If out of N memory Locations, only P memory locations are to be inter faced, then the Least significant P address Lines out of available n lines can be directly connected from the microprocessor to the memory chip while the remaining (n-p) higher order address lines may be used for Address decoding (as I/P s to the chip selection logic) The o/p of the decoding ckt is connected with CS pin of the memory chip. Procedure of SRAM Inter facing: Arrange the available memory chips so as to obtain 16-bit data bus width. The upper 8-bit bank is called odd address Bank and Lower is called even address Bank. Connect available memory address Lines of memory chips with those of the up and also connect the memory RD& WR I/Ps to the corresponding processor control signal. Connect the 16-bit data bus of the memory bank to up.

2 The remaining add. lines, BHE and Ao are used for decoding chip select signals for odd and even memory banks. The CS of memory is derived from the o/p of the decoding ckt. Problem1: Interface two 4k*8 EPROMs and two 4k*8 RAM chips with Sol: After Reset, the CS and IP are initialized to form address FFFFOH. Hence, this address must lie in the EPROM. The address of RAM may be selected any where in the 1 MB address space of 8086, but we will select the RAM. Two 4k byte Location = 8 k bytes of EPROM =1024 *8 = 8192.Locations = address Lines (A0-A12) are needed. A 13 -A 19 are used for decoding to generate the chip select. The two 4k*8 chips of RAM and ROM are arranged in parallel to obtain n 16-bit data bus width. Depending upon the status of A 0, BHE lower byte or higher byte or whole word is accessed from even/odd address.

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5 Problem 2: Design an interface b/w CPU and two chips of 16k*8 EPROM and two chips of 32k*8 RAM. Select the address of EPROM so that RAM starts at 00000H. Sol: EPROM: Two 16k*8 chips 2 1 *2 4 *2 10. Byte locations 15 address lines are needed. (A0-A14) RAM: Two 32k*8 chips 2 1 *2 5 *2 10 byte locations

6 16 address lines are needed. (A 0 -A 15 ) It is better not to use a decoder to implement the above map b/c it is not continuous, i.e, there is some unused address space b/w the last RAM add. 0FFFFH RAM address(f8000h)

7 Example: Interface four 32K EPROM and four 32K RAM to 8086 based system. Design address decoders assigning the address range E0000H to FFFFFH for EPROM and 00000H to 1FFFFH to RAM. Show the memory map for the system.

8 INTERRUPT STRUCTURE OF 8086: While the CPU is executing a program, an interrupt breaks the normal sequence of execution of instructions, diverts its execution to some other program called Interrupt Service Routine (ISR). After executing ISR, the control is transferred back again to the main program which was being executed at the time of interruption. Interrupt Response In 8086, there are two interrupts pins: 1. NMI 2. INTR NMI :-- Non Maskable Interrupt input pin which means that any interrupt request at NMI input cannot to masked or disabled by any means. INTR:-- It can be masked using the Interrupt Flag (IF). If more than one type of INTR interrupt occurs at a time, then an external chip called programmable interrupt controller is required to handle them. (eg: 8259 interrupt controller). There are two types of interrupts 1.External interrupts These interrupts are generated by external devices i.e out side the processor (uing NMI, INTR pins). Eg: Keyboard interrupt. 1.Internal interrupts It is generated internally by the process circuit or by the execution of an interrupt instruction. Eg: INT instructions, overflow interrupt, divide by zero. At the end of each instruction cycle, the 8086 checks to see if any interrupts have been requested

9 Interrupt Vector Table 8259 (PROGRAMMABLE INTERRUPT CONTROLLER) The 8259A is a device specifically designed for usein real time, interrupt driven microcomputer systems. It manages eight levels or requests and has built-in features for expandability to other 8259A's (up to 64 levels). It is programmed by the system's software as an I/O peripheral. A selection of priority modes is available to the programmer so that the manner in which the requests are processed by the 8259A can be configured to match his system requirements. The priority modes can be changed or reconfigured dynamically at any time during the main program. This means that the complete interrupt structure canbe defined as required, based on the total system environment.

10 Interrupt Request Register (IRR) And In-Service Register (ISR): The interrupts at the IR input lines are handled by two registers in cascade, the Interrupt Request Register (IRR) and the In-Service (ISR). The IRR is used to store all the interrupt levels which are requesting service; and the ISR is used to store all the interrupt levels which are being serviced. Priority Resolver This logic block determines the priorites of the bits set in the IRR. The highest priority is selected and strobed into the corresponding bit of the ISR during INTA pulse. Interrupt Mask Register (IMR) The IMR stores the bits which mask the interrupt lines to be masked. The IMR operates on the IRR. Masking of a higher priority input will not affect the interrupt request lines of lower quality. INT (Interrupt) This output goes directly to the CPU interrupt input. The VOH level on this line is designed to be fully compatible with the 8080A, 8085A and 8086 input levels. INTA (Interrupt Acknowledge) INTA pulses will cause the 8259A to release vectoring information onto the data bus. The format of this data depends on the system mode of the 8259A. Data Bus Buffer This 3-state, bidirectional 8-bit buffer is used to interface the 8259A to the system Data Bus. Control words and status information are transferred through the Data Bus Buffer. Read/Write Control Logic The function of this block is to accept OUTput commands from the CPU. It contains the Initialization Command Word (ICW) registers and Operation Command Word (OCW) registers

11 which store the various control formats for device operation. This function block also allows the status of the 8259A to be transferred onto the Data Bus. CS (Chip Select) A LOW on this input enables the 8259A. No reading or writing of the chip will occur unless the device is selected. WR (Write) A LOW on this input enables the CPU to write control words (ICWs and OCWs) to the 8259A. RD (READ) A LOW on this input enables the 8259A to send the status of the Interrupt Request Register (IRR), In Service Register (ISR), the Interrupt Mask Register (IMR), or the Interrupt level onto the Data Bus. A0 This input signal is used in conjunction with WR and RD signals to write commands into the various command registers, as well as reading the various status registers of the chip. This line can be tied directly to one of the address lines. The Cascade Buffer/Comparator This function block stores and compares the IDs of all 8259A's used in the system. The associated three I/O pins (CAS0-2) are outputs when the 8259A is used as a master and are inputs when the 8259A is used as a slave. As a master, the 8259A sends the ID of the interrupting slave device onto the CAS0±2 lines. The slave thus selected will send its preprogrammed subroutine address onto the Data Bus during the next one or two consecutive INTA pulses. (See section ``Cascading the 8259A''.) CASCADING THE 8259: The 8259 can be easily interconnected in a system of one master with up to eight slaves to handle up to 64 priority levels.

12 The master controls the slaves through the 3 line cascade bus (CAS2-0). The cascade bus acts like chip selects to the slaves during the INTA sequence. In a cascade configuration, the slave interrupt outputs (INT) are connected to the master interrupt request inputs. When a slave request line is activated and afterwards acknowledged, the master will enable the corresponding slave to release the device routine address during bytes 2 and 3 of INTA. (Byte 2 only for 80C86/88/286). When the slave receives an interrupt signal on one of its IR inputs, it checks mask condition and priority of the interrupt request. If the interrupt is unmasked and its priority is higher than any other interrupt level being serviced in slave, then the slave will send an INT signal to the IR input of a master. If that IR input of the master is unmasked and if that input is a higher priority than any other IR inputs currently being serviced, then the master will send an INT signal to the 8086 INTR input.if the INTR interrupt is enabled, the 8086will go through its INTR interrupt procedure and sends out two INTA BAR pulses to both the master and the slave. The slave ignores the first Interrupt acknowledge pulse but the master outputs a 3 bit slave id number on the CAS0- CAS2 lines. Sending the 3 bit ID no enables the slave. When the slave receives the second INTA BAR pulse from the 8086, the slave will send the desired type number to the 8086 on eight data lines. If an interrupt signal is applied directly to one of the IR inputs of the master, the master. The master will send the desired interrupt type to the 8086 when it receives the second INTA BAR pulse from the PROGRAMMING The 8259A accepts two types of command words generated by the CPU: 1. Initialization Command Words (ICWs): Before normal operation can begin, each 8259A in the system must be brought to a starting pointð by a sequence of 2 to 4 bytes timed by WR pulses. 2. Operation Command Words (OCWs): These are the command words which command the 8259A to operate in various interrupt modes. These modes are: a. Fully nested mode b. Rotating priority mode c. Special mask mode d. Polled mode The OCWs can be written into the 8259A anytime after initialization.

13 INITIALIZATION COMMAND WORDS (ICWS) Whenever a command is issued with A0 e 0 and D4 e 1, this is interpreted as Initialization Command Word 1 (ICW1). ICW1 starts the initialization sequence during which the following automatically occur. a. The edge sense circuit is reset, which means that following initialization, an interrupt request (IR) input must make a low-to-high transition to generate an interrupt. b. The Interrupt Mask Register is cleared. c. IR7 input is assigned priority 7. d. The slave mode address is set to 7. e. Special Mask Mode is cleared and Status Read is set to IRR. f. If IC4 e 0, then all functions selected in ICW4 are set to zero. (Non-Buffered mode*, no Auto- EOI, MCS-80, 85 system). *NOTE: Master/Slave in ICW4 is only used in the buffered mode.

14 Initialization Command Words 1 and 2 (ICW1, ICW2) In an MCS 80/85 system, the 8 request levels will generate CALLs to 8 locations equally spaced in memory. These can be programmed to be spaced at intervals of 4 or 8 memory locations, thus the 8 routines will occupy a page of 32 or 64 bytes, respectively. The address format is 2 bytes long (A0±A15). When the routine interval is 4, A0±A4 are automatically inserted by the 8259A, while A5±A15 are programmed externally. When the routine interval is 8, A0±A5 are automatically inserted by the 8259A, while A6±A15 are programmed externally. The 8-byte interval will maintain compatibility with current software, while the 4-byte interval is best for a compact jump table. In an 8086 system A15±A11 are inserted in the five most significant bits of the vectoring byte and the 8259A sets the three least significant bits according to the interrupt level. A10±A5 are ignored and ADI (Address interval) has no effect. LTIM: If LTIM e 1, then the 8259A will operate in the level interrupt mode. Edge detect logic on the interrupt inputs will be disabled. ADI: CALL address interval. ADI e 1 then interval e 4; ADI e 0 then interval e 8. SNGL: Single. means that this is the only 8259A in the system. If SNGL e 1 no ICW3 will be issued. IC4: If this bit is setðicw4 has to be read. If ICW4 is not needed, set IC4 e 0.

15 Initialization Command Word 3 (ICW3) This word is read only when there is more than one 8259A in the system and cascading is used, in which case SNGL e 0. It will load the 8-bit slave register. The functions of this register are: a. In the master mode (either when SP e 1, or in buffered mode when M/S e 1 in ICW4) a ``1'' is set for each slave in the system. The master then will release byte 1 of the call sequence (for MCS- 80/85 system) and will enable the corresponding slave to release bytes 2 and 3 (for 8086 only byte 2) through the cascade lines. b. In the slave mode (either when SP e 0, or if BUF e 1 and M/S e 0 in ICW4) bits 2±0 identify the slave. The slave compares its cascade input with these bits and, if they are equal, bytes 2 and 3 of the call sequence (or just byte 2 for 8086) are released by it on the Data Bus.

16 Initialization Command Word 4 (ICW4) SFNM: If SFNM e 1 the special fully nested mode is programmed. BUF: If BUF e 1 the buffered mode is programmed. In buffered mode SP/EN becomes an enable output and the master slave determination is by M/S. M/S: If buffered mode is selected: M/S e 1 means the 8259A is programmed to be a master, M/S e 0 means the 8259A is programmed to be a slave. If BUF e 0, M/S has no function. AEOI: If AEOI e 1 the automatic end of interrupt mode is programmed. mpm: Microprocessor mode: mpm e 0 sets the 8259A for MCS-80, 85 system operation, mpm e 1 sets the 8259A for 8086 system operation. OPERATION COMMAND WORDS (OCWS) After the Initialization Command Words (ICWs) are programmed into the 8259A, the chip is ready to accept interrupt requests at its input lines. However, during the 8259A operation, a selection of algorithms can command the 8259A to operate in various modes through the Operation Command Words (OCWs). Operation Control Word 1 (OCW1) OCW1 sets and clears the mask bits in the Interrupt Mask Register (IMR). M7±M0 represent the eight mask bits. M e 1 indicates the channel is masked (inhibited), M e 0 indicates the channel is enabled.

17 Operation Control Word 2 (OCW2) R, SL, EOIÐThese three bits control the Rotate and End of Interrupt modes and combinations of the two.a chart of these combinations can be found on the Operation Command Word Format. L2, L1, L0ÐThese bits determine the interrupt level acted upon when the SL bit is active. Operation Control Word 3 (OCW3) ESMMÐEnable Special Mask Mode. When this bit is set to 1 it enables the SMM bit to set or reset the Special Mask Mode. When ESMM e 0 the SMM bit becomes a ``don't care''.

18 SMMÐSpecial Mask Mode. If ESMM e 1 and SMM e 1 the 8259A will enter Special Mask Mode. If ESMM e 1 and SMM e 0 the 8259A will revert to normal mask mode. When ESMM e 0, SMM has no effect. DOS AND BIOS INTERRUPTS: Interrupt Types Description BIOS Interrupts 0h-1Fh DOS Interrupts 20h-3Fh Reserved 40h-7Fh ROM BASIC 80h-F0h not used F1h-FFh The CPU does not generate the interrupt routine's address directly from the interrupt number. Doing so would mean that a particular interrupt routine must be placed in exactly the same location in every computer. Instead, the CPU uses the interrupt number to calculate the address of a memory location that contains the actual address of the interrupt routine INT 21h / AH=1 - read character from standard input, with echo, result is stored in AL. if there is no character in the keyboard buffer, the function waits until any key is pressed.

19 example: mov ah, 1 int 21h INT 21h / AH=2 - write character to standard output. entry: DL = character to write, after execution AL = DL. example: mov ah, 2 mov dl, 'a' int 21h INT 21h / AH=5 - output character to printer. entry: DL = character to print, after execution AL = DL. example: mov ah, 5 mov dl, 'a' int 21h INT 21h / AH=6 - direct console input or output. parameters for output: DL = (ascii code) parameters for input: DL = 255 for output returns: AL = DL for input returns: ZF set if no character available and AL = 00h, ZF clear if character available. AL = character read; buffer is cleared. example: mov ah, 6 mov dl, 'a' int 21h ; output character. mov ah, 6 mov dl, 255 int 21h ; get character from keyboard buffer (if any) or set ZF=1. INT 21h / AH=7 - character input without echo to AL. if there is no character in the keyboard buffer, the function waits until any key is pressed. example:

20 mov ah, 7 int 21h INT 21h / AH=9 - output of a string at DS:DX. String must be terminated by '$'. example: org 100h mov dx, offset msg mov ah, 9 int 21h ret msg db "hello world $" INT 21h / AH=0Ah - input of a string to DS:DX, fist byte is buffer size, second byte is number of chars actually read. this function does not add '$' in the end of string. to print using INT 21h / AH=9 you must set dollar character at the end of it and start printing from address DS:DX + 2. example: org 100h mov dx, offset buffer mov ah, 0ah int 21h jmp print buffer db 10,?, 10 dup(' ') print: xor bx, bx mov bl, buffer[1] mov buffer[bx+2], '$' mov dx, offset buffer + 2 mov ah, 9 int 21h ret DMA DATA TRANSFER: NEED FOR DMA: Normally, we use program Inst. to transfer data from ports to memory or from memory to ports. For some applications, such as transferring data bytes to memory from a magnetic or optical disk, the data bytes coming form the disk are faster than they can be read in with program inst. In this case, we use dedicated H/W device called a DMA (Direct Memory Access) controller to manage the data T/f.

21 The DMA controller borrows the add, data and control bus from CPU and transfers, the data bytes from the disk controller to a series of memory locations. Because it is handled totally in hardware, it is much faster than it would be it done by program inst. Types of Transfers: From memory to port transfers Memory to memory transfers Here s an example of how a common DMA controller is connected and used in 8086 minimum-mode system. When the system is first turned on, the switches are in the UP position, so the buses are connected form the up to system memory and peripherals. To read a disk file, we send a series of commands to disk controller device, to find and read the desired block of data from the disk, When the first byte of data is ready (from disk) it sends a DMA request DREQ to DMA controller. If that i/p (channel) of the DMA controller is unmasked, the DMA will send a HRQ (Hold request) signal to the up HOLD I/P. The up will respond to this i/p by floating its buses and sending out a HLDA to DMA controller. When the DMA controller receives the HLDA signal, it will send out a control signal which throws three switches down to their DMA position.

22 When it gets control of buses, it sends out the memory address where the first byte of data from disk is to be written. Next the DMA controller sends a DACKO (DMA Ack) signal to the disk to get ready to o/p the byte. Finally, the DMA asserts both MEMW and IOR lines on control bus. MEMW enables the addressed memory to accept data written to ti. IOR enables the disk controller to O/P the byte of data from the disk on the data bus. The byte of data then is transferred directly form the disk controller to the memory location w/o passing through the CPU or the DMA. When the data T/f is complete, the DMA un asserts the hold-request signal to the processor and releases the buses. The switches are effectively thrown back up to the CPU position. A DMA T/f from memory to the disk proceeds in a similar manner except that the DMA asserts MEMR& IOW For this process, each channel of DMA should contain an Address register and a Byte /word count register. o Initializing the controller consis5s of filling these resisters with the beginning (or ending address) of the memory array and the no. of bytes to be transferred. DMA CONTROLLER (8257) Internal Architecture of 8257: The chip supports four DMA channels, i.e, four peripheral devices can independently request for DMA data T/f. In addition, it has 8-bit data buffer, a read/write unit, a control unit, a priority resolving unit along with a set of registers. Resister Organization of 8257: Each of the four channels of 8257 has a pair of two 16-bit registers, DMA address Register Terminal count register. Two common registers for all channels Mode set register Status register. Thus there are a total of ten registers. These are selected using A 0 -A 3. The LSB and MSB of each register for a specific channel has the same address, but they are differentiated by an internal First/Last(F/L) flip flop. If F/L =0, LSB is to be read or written. F/L =1, MSB is to be read or written. The F/L FF needs to be cleared by resetting The least significant three address bits A 0 -A 1 indicate the specific register for a specific channel. The A 3 add.line is used to differentiate b/w all the channel registers and the mode set register, status registers.

23 The higher order bits (A 4 -A 15 ) may be used to derive the chip select signal CS of DMA ADDRESS REGISTERS: Each DMA channel has one DMA add.register. The function of it is to store the address of the starting memory location, which will be accessed by the DMA channel. Terminal Count Register: Like the add.register, each of the four DMA channels has one Terminal count register (TC). This 16-bit register is used for ascertaining that the data T/f through a DMA channel ceases or stops after the required number of DMA cycles. The Low order 14-bits of the TC are initialized with the Binary equivalent of the no. of required DMA cycles minus one. After each cycle, TC is decremented by 1. The bits 14 and 15 indicate the type of DMA operation Mode Set Register: This is used for programming the 8257 as per the requirements of the system. The function of it is to enable the DMA channels individually and also to set the various modes of operation. A DMA channel should not be enabled till the add register and TC contain valid information The bits D 0 -D 3 enable one of the four DMA channels. If the TC stop bit is set, the selected channel is disables after the TC condition is reached, and it further prevents any DMA cycle in the channel, To enable it again, this bit must be reprogrammed. The Auto Load bit, if set, enables channel 2 for the Repeat Block Chaining operations, w/o immediate s/w intervention b/w the two successive blocks.

24 The channel 2 registers are used as usual, while the channel 3 registers are used to store the block re initialization parameters. After the first block is transferred using DMA, the channel 2 registers are reloaded with the corresponding channel 3 registers for the next Block T/f. *If update flag is set). The extended write bit, if set to 1, extends the duration of MEMW and IOW signals. If the peripheral is not accessed with in the stipulated time, it is expected to give the NOT READY indication to 8257, to request it, to add one or more wait states in the DMA cycle. Status Register: If any of the four Lower order bits are set, it indicates that the specific cannel as reached the terminal count condition. These bits remain set till either the status is read by CPU or 8257 is reset.the update flag can only be affected by write operation, associated with the auto load bit of MSR. If update flag is set, the contents of the channel 3 registers are reloaded to the corresponding registers of channel 2, whenever the channel 2 reached a TC condition. Pointer of the DMA request: Fixed Priority: Rotating Priority:

25 In this scheme, any device requesting the service is guaranteed and given higher priority, once it is serviced it is given lowest priority. Ex: Data Bus Buffer Internal Bus: The bidirectional buffer interfaces the internal bus of 8257 with the external system bus under the control of various control signals.

26 Read/Write Logic: In an slave mode, the read/write logic accepts the I/O Read or Write Signals IOR, IOW, decodes the A 0 -A 3 lines and either writs the contents of data bus to addressed internal register or reads the contents of the selected register. In the master mode, the read/write logic generates the IOR & IOW signals to control the data flow to or from the selected peripheral. Control logic: It controls the sequences of operations and generates the signals like AEN, ADSTB in Master mode. Priority Resolver: It resolves the priority of four channels depending upon whether normal priority or Rotating priority. Questions: What are the registers available in 8257? What are their functions? Discuss the priorities of DMA request inputs of Draw and discuss the mode set register of Interfacing DMA 8257 with 8086: Prob: Interface DMA with 8086 so that the channel 0 DMA addresses reg. has an I/O address 80H. Initialize the 8257 with normal priority, TC stop and non-extended write. Auto load is not required. Write an ALP to move 2KB of data form peripheral device to memory address 2000H: 5000H, with the above initialization. The transfer has to take place using channel 0. Sol: DMA Add.register: This should contain the starting address of memory block i.e 5000H TC Register: The bits A 14 and A 15 are used for specification of type of operation. DMA write: A 15 A 14 = 0 1 The remaining 14-bits are will contain the binary equivalent of the required o. of DMA cycles i.e, no. of bytes to be transferred minus one.

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