BUS TIMING ANALYSIS. George E Hadley, Timothy Rogers, and David G Meyer 2018, Images Property of their Respective Owners

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1 BUS TIMING ANALYSIS George E Hadley, Timothy Rogers, and David G Meyer 2018, Images Property of their Respective Owners

2 LEARNING OBJECTIVES identify CPU and memory timing parameters draw a bus timing diagram for a simplex CPU-memory interface identify the critical read and write cycle paths on a bus timing diagram define setup and hold times as they pertain to a CPU-memory interface and discuss the consequences of violating them calculate read and write timing margins for a given CPU-memory combination describe the potential consequences of excessive read float delay define timing margin and discuss the consequences of an insufficient margin

3 OUTLINE Definitions of typical bus signals CPU-Memory interface circuit Timing parameters Synchronous read cycle timing chart Synchronous write cycle timing chart Critical path assessment Timing margin Example application

4 DEFINITIONS OF TYPICAL BUS SIGNALS BUS CLOCK (CLK) used to enable memory and I/O accesses (in conjunction with the R/W signal) in synchronous bus systems, one cycle of this clock usually corresponds to one unit of bus activity (e.g., a CPU read of a specific memory location or a CPU write to a specific I/O port)

5 DEFINITIONS OF TYPICAL BUS SIGNALS ADDRESS BUS outputs memory or I/O location address during valid memory reference cycles high impedance state if processor relinquishes bus to a secondary bus master (like a DMA controller) DATA BUS inputs data from memory or I/O location on read cycles, outputs data on write cycles high impedance state if processor relinquishes bus to a secondary bus master

6 DEFINITIONS OF TYPICAL BUS SIGNALS Read/Write (R/W ) indicates direction of data transfer on data bus (input for read, output for write ) high impedance if processor relinquishes bus to a secondary bus master memory and I/O control signals OE (output enable) and WE (write enable) are usually provided directly by CPU

7 DEFINITIONS OF TYPICAL BUS SIGNALS READY (RDY) in synchronous bus systems, asserted by the memory (or I/O device) being accessed to indicate the bus transaction requested by the CPU may be completed on the current bus cycle if negated, the CPU inserts wait states allows the CPU to accommodate slower memory or I/O devices

8 HIGH-LEVEL PICTURE OF EXTERNAL MEMORY Location in memory. Effective address Address Bus (Abus) Data Bus (Dbus) M-bits / N-bits / Upper-most bits / Address Decode PLD Is the chip turned on? 0=on, 1=off Chip Enable (CE) Address (in) Data (in/out) CPU Bits for the actual value Is the processor reading (load) or writing (store) Should memory output on data bus? 0=yes, 1=no External Memory Chip R/W Output Enable (OE) CLK Write Enable (WE) Bus Clock: Comes from CPU, tells memory when to do stuff. One cycle=time to do one read or write Should memory write bits on data bus into itself? 0=yes, 1=no

9 CPU TIMING PARAMETERS Common to READ and WRITE cycles t CY (CPU bus cycle time) t AD (CPU address generation delay) t AH (CPU address hold time) READ cycle t RS (CPU read data setup time) t RH (CPU read data hold time) WRITE cycle t DD (CPU write data generation delay) t WH (CPU write data hold time) t WZ (CPU write data float delay, after t WH )

10 MEMORY TIMING PARAMETERS READ Cycle t AA (memory address access time) t CE (memory chip enable access time) t OE (memory output enable access time) t OH (memory output hold time) t OZ (memory output data float delay, after t OH ) WRITE cycle t IS (memory input data setup time) t IH (memory input data hold time) t AW (memory address to write time) t CW (memory chip enable to write time) t WP (memory write pulse width) [2.A]-10

11 SUCCESSIVE SYNCHRONOUS READ CYCLES Successive = one read following another (i.e. no write cycles) Synchronous = one unit of bus activity per clock cycle Read = CPU loads (inputs) data Clock drives everything: CPU reads data on falling edge of clock

12 SUCCESSIVE SYNCHRONOUS READ CYCLES After falling edge of clock, CPU thinks, then initiates read Cross-hatch indicates signal is changing, and that its state is not guaranteed CPU driving stable R/W =1 shaded in green

13 SUCCESSIVE SYNCHRONOUS READ CYCLES R/W CLK OE is telling the memory when to drive the data bus This signal goes low when R/W =1 and CLK=1

14 SUCCESSIVE SYNCHRONOUS READ CYCLES CPU Drives the ADDR lines: they become valid at the same time R/W does

15 SUCCESSIVE SYNCHRONOUS READ CYCLES CE depends on ADDR: once ADDR stabilizes, CE stabilizes Blip (to one) indicates potential for CE to temporarily be invalid (could also just be shown as a cross-hatch ) Uppermost bits / Address Decode PLD ADDR

16 SUCCESSIVE SYNCHRONOUS READ CYCLES For the memory chip to supply data to the CPU on the read cycle, several conditions need to be met OE asserted Valid/stable address CE asserted Be told to output Have a valid address Turned on After taking some time to think about it, the memory chip turns on its tri-state buffers and places the data addressed on the data bus

17 SUCCESSIVE SYNCHRONOUS READ CYCLES Where CPU reads data on the bus CPU is completely driven by the clock Captures what is on the data bus on the falling edge

18 SUCCESSIVE SYNCHRONOUS READ CYCLES Where CPU reads data on the bus R/W takes Address Delay time from the falling edge of the clock to become valid R/W is held for Address Hold time after end of cycle (negation of CLK)

19 SUCCESSIVE SYNCHRONOUS READ CYCLES Where CPU reads data on the bus For CPU to read properly, data bus must satisfy setup and hold times (i.e. data can not change during the red window

20 SUCCESSIVE SYNCHRONOUS READ CYCLES Where CPU reads data on the bus For CPU to read properly, data bus must satisfy setup and hold times (i.e. data can not change during the red window Negating OE tells the memory to stop outputting (turns off tri-state buffers

21 SUCCESSIVE SYNCHRONOUS READ CYCLES Where CPU reads data on the bus Recall: Read/Write (R/W) timing parameters are associated with the CPU Input/Output (I/O) timing parameters are associated with the memory The memory keeps outputting valid data for the output hold time Output float delay is the time it takes the memory to get off (disconnect from) the data bus Negating OE tells the memory to stop outputting (turns off tri-state buffers

22 SUCCESSIVE SYNCHRONOUS READ CYCLES Where CPU reads data on the bus The data absolutely, positively has to be ready by the Fed-Ex line

23 SUCCESSIVE SYNCHRONOUS READ CYCLES Where CPU reads data on the bus These yellow segments represent the maximum (propagation delay) values the memory can have and still meet timing requirements they represent the read cycle critical paths

24 SUCCESSIVE SYNCHRONOUS READ CYCLES Where CPU reads data on the bus These yellow segments represent the maximum (propagation delay) values the memory can have and still meet timing requirements they represent the read cycle critical paths If memory is faster than nominally required (relative to the Fed-Ex line) there is a read timing margin

25 COLLABORATIVE CLICKER QUIZ (CCQ) Question 1 The Green (Fed-Ex) Line for a READ cycle refers to the instant that the data absolutely, positively has to be there (within nanoseconds) for the memory read operation to be successful. The Fed-Ex Line is determined by: A. the read setup time prior to the end of the bus cycle B. the bus cycle minus the address generation delay C. the bus cycle minus the data generation delay D. the read hold time prior to the end of the bus cycle E. none of the above

26 COLLABORATIVE CLICKER QUIZ (CCQ) Question 2 If the value on the data bus changes before the Green (Fed-Ex) Line : A. bus fighting might occur B. the wrong value might be read by the processor C. data might be read from the wrong address D. the memory chip might be damaged E. none of the above

27 COLLABORATIVE CLICKER QUIZ (CCQ) Question 3 If the value on the data bus changes t RS after the Green (Fed-Ex) Line : A. bus fighting might occur B. the wrong value might be read by the processor C. data might be read from the wrong address D. the memory chip might be damaged E. none of the above

28 COLLABORATIVE CLICKER QUIZ (CCQ) Question 4 If the value on the data bus changes t RS + t RH after the Green (Fed-Ex) Line : A. bus fighting might occur B. the wrong value might be read by the processor C. data might be read from the wrong address D. the memory chip might be damaged E. none of the above

29 COLLABORATIVE CLICKER QUIZ (CCQ) Question 5 The following parameter has no influence on the read timing margin available: A. t AA B. t OE C. t OH D. t CE E. none of the above

30 SUCCESSIVE SYNCHRONOUS WRITE CYCLES Successive = one write following another (i.e. no read cycles) Synchronous = one unit of bus activity per clock cycle Write = CPU stores (outputs) data

31 SUCCESSIVE SYNCHRONOUS WRITE CYCLES After falling edge of clock, CPU thinks, then initiates write Cross-hatch indicates signal is changing, and that its state is not guaranteed CPU driving stable R/W =0 shaded in green

32 SUCCESSIVE SYNCHRONOUS WRITE CYCLES WE is telling the memory to open its row of latches that correspond to the memory location addressed This signal goes low when R/W =0 and CLK=1 R/W CLK

33 SUCCESSIVE SYNCHRONOUS WRITE CYCLES WE is telling the memory to open its row of latches that correspond to the memory location addressed This signal goes low when R/W =0 and CLK=1 R/W CLK CPU Drives the ADDR lines: they become valid at the same time R/W does

34 SUCCESSIVE SYNCHRONOUS WRITE CYCLES CE depends on ADDR: once ADDR stabilizes, CE stabilizes Blip (to one) indicates potential for CE to temporarily be invalid (could also just be shown as a cross-hatch ) Uppermost bits / Address Decode PLD

35 SUCCESSIVE SYNCHRONOUS WRITE CYCLES For the memory chip to accept data from the CPU on the write cycle, several conditions need to be met WE asserted Valid/stable address CE asserted Be told to input Have a valid address Turned on

36 SUCCESSIVE SYNCHRONOUS WRITE CYCLES Latches in memory device open when WE is asserted Latches close (retain data) when WE is negated

37 SRAM FLASHBACK Conceptually, just a D-Latch where latch is open when SEL/WR are asserted

38 SUCCESSIVE SYNCHRONOUS WRITE CYCLES R/W takes Address Delay time from the falling edge of the clock to become valid R/W is held for Address Hold time after end of cycle (negation of CLK)

39 SUCCESSIVE SYNCHRONOUS WRITE CYCLES The CPU delays (by t DD ) driving the (write) data onto the bus, to provide a cushion for the previous cycle to complete this helps reduce the chance that bus fighting will occur

40 SUCCESSIVE SYNCHRONOUS WRITE CYCLES Recall: Read/Write (R/W) timing parameters are associated with the CPU Input/Output (I/O) timing parameters are associated with the memory The latches in memory also have a red window (setup and hold time) during which its inputs (supplied via the data bus) must remain stable

SUCCESSIVE SYNCHRONOUS WRITE CYCLES Recall: Read/Write (R/W) timing parameters are associated with the CPU Input/Output (I/O) timing parameters are associated

41 SUCCESSIVE SYNCHRONOUS WRITE CYCLES Recall: Read/Write (R/W) timing parameters are associated with the CPU Input/Output (I/O) timing parameters are associated with the memory The CPU keeps outputting valid data for the write hold time Write float delay is the time it takes the CPU to get off (disconnect from) the data bus

42 SUCCESSIVE SYNCHRONOUS WRITE CYCLES These yellow segments represent the write cycle critical paths minimum write pule width valid address prior to write valid chip enable prior to write If CPU provides data earlier than nominally required (relative to the Fed-Ex line) there is a write timing margin

43 COLLABORATIVE CLICKER QUIZ (CCQ) Question 1 The Green (Fed-Ex) Line for a WRITE cycle refers to the instant that the data absolutely, positively has to be there (within nanoseconds) for the memory write operation to be successful, which is: A. the input setup time prior to the end of the bus cycle B. the input setup time prior to the negation of write enable C. the input hold time following the negation of write enable D. the write pulse width E. none of the above

44 COLLABORATIVE CLICKER QUIZ (CCQ) Question 2 If the data supplied to memory changes t IS before the negation of write enable: A. bus fighting might occur B. the wrong value might be written to memory C. data might be written to the wrong address D. all of the above E. none of the above

45 COLLABORATIVE CLICKER QUIZ (CCQ) Question 3 If the data supplied to memory changes less than t IS before the negation of write enable: A. bus fighting might occur B. the wrong value might be written to memory C. data might be written to the wrong address D. all of the above E. none of the above

46 COLLABORATIVE CLICKER QUIZ (CCQ) Question 4 If the data supplied to memory changes less than t IH after the negation of write enable: A. bus fighting might occur B. the wrong value might be written to memory C. data might be written to the wrong address D. all of the above E. none of the above

47 COLLABORATIVE CLICKER QUIZ (CCQ) Question 5 If the data supplied to memory changes greater than t IH after the negation of write enable: A. bus fighting might occur B. the wrong value might be written to memory C. data might be written to the wrong address D. all of the above E. none of the above

48 AN EXAMPLE: CPU TIMING SPECS Used on both Read and Write Read Specific Write Specific Description Parameter Value Bus clock period t CY 200 ns Address generation delay t AD 30 ns Address hold time t AH 20 ns Read setup time t RS 30 ns Read hold time t RH 20 ns Write data generation delay t DD 80 ns Write hold time t WH 30 ns Write float delay (after t WH ) t WZ 10 ns Assume all glue logic delays are 10 ns

49 SRAM GLUE LOGIC For this example, assume all glue logic delays are 10 Address Bus (Abus) Data Bus (Dbus) CPU M-bits / N-bits / Upper-most bits / Glue Logic Address Decode PLD Propagation delay on ADDR to CE Propagation delays on R/W and CLK changing OE and WE Chip Enable (CE) Address (in) Data (in/out) External Memory Chip R/W CLK Output Enable (OE) Write Enable (WE)

50 SUCCESSIVE SYNC READ CYCLES W/ NUMBERS Parameter t CY t AD t AH t RS t RH t DD t WH t WZ Value 200 ns 30 ns 20 ns 30 ns 20 ns 80 ns 30 ns 10 ns

51 SUCCESSIVE SYNC READ CYCLES W/ NUMBERS Parameter t CY t AD t AH t RS t RH t DD t WH t WZ Value 200 ns 30 ns 20 ns 30 ns 20 ns 80 ns 30 ns 10 ns

52 SUCCESSIVE SYNC READ CYCLES W/ NUMBERS Parameter t CY t AD t AH t RS t RH t DD t WH t WZ Value 200 ns 30 ns 20 ns 30 ns 20 ns 80 ns 30 ns 10 ns

53 SUCCESSIVE SYNC READ CYCLES W/ NUMBERS Parameter t CY t AD t AH t RS t RH t DD t WH t WZ Value 200 ns 30 ns 20 ns 30 ns 20 ns 80 ns 30 ns 10 ns

54 SUCCESSIVE SYNC WRITE CYCLES W/ NUMBERS Parameter t CY t AD t AH t RS t RH t DD t WH t WZ Value 200 ns 30 ns 20 ns 30 ns 20 ns 80 ns 30 ns 10 ns

55 MATCHING OUR EXAMPLE CPU TO AN EXAMPLE SRAM Read Specific Write Specific Description Parameter Value Address access time t AA 80 ns min Chip enable access time t CE 80 ns min Output enable access time t OE 20 ns min Output hold from OE /CE negation or address change t OH 10 ns min Output float delay following t OH t OZ 10 ns max Input (write) data setup time t IS 30 ns min Input (write) data hold time t IH 20 ns min Write pulse width t WP 40 ns min Address valid prior to memory write t AW 90 ns min Chip enable valid prior to memory write t CW 80 ns min

SUCCESSIVE SYNC READ CYCLES W/ NUMBERS latest of these determines critical path, and the amount of read timing margin available Parameter t AA t

56 SUCCESSIVE SYNC READ CYCLES W/ NUMBERS latest of these determines critical path, and the amount of read timing margin available Parameter t AA t CE t OE t OH t OZ t IS t IH t WP t AW t CW Value 80 ns min 80 ns min 20 ns min 10 ns min 10 ns max 30 ns min 20 ns min 40 ns min 90 ns min 80 ns min

57 SUCCESSIVE SYNC WRITE CYCLES W/ NUMBERS Parameter t AA t CE t OE t OH t OZ t IS t IH t WP t AW t CW Value 80 ns min 80 ns min 20 ns min 10 ns min 10 ns max 30 ns min 20 ns min 40 ns min 90 ns min 80 ns min

58 CRITICAL PATH ASSESSMENT Typically three (primary) critical read paths to consider: t AA t CE t OE Why are the write paths typically not critical? The read paths are round trip whereas write paths are one way

TIMING MARGIN Definition: The difference between the nominal memory performance required and performance of actual memory component chosen Why a margin is needed: To accommodate normal variations

59 TIMING MARGIN Definition: The difference between the nominal memory performance required and performance of actual memory component chosen Why a margin is needed: To accommodate normal variations that occur in device performance due to operating temperature, lot variations, etc. What is a safe margin? Usually about 10% of the parameter in question What is the consequence of insufficient margin? Unstable performance!

60 EXAMPLE DESIGN RESULTS - SUMMARY This example illustrates the use of a 5 MHz (200 ns bus clock) CPU in conjunction with an 80 ns (t AA and t CE ) SRAM If a CPU (as specified) is interfaced to an SRAM (as specified), and the glue logic delay is 10 ns, then the following timing margins will be realized: read timing margin: 40 ns write timing margin: 100 ns

61 COLLABORATIVE CLICKER QUIZ (CCQ) Question 1 If the nominal t CE for a CPU-memory interface is 50 ns, the speed of SRAM that should be utilized in order to provide a 10% read timing margin is: A. 45 ns B. 50 ns C. 55 ns D. 60 ns E. none of the above

62 COLLABORATIVE CLICKER QUIZ (CCQ) Question 2 A possible consequence of insufficient timing margin is: A. sensitivity to relative humidity B. sensitivity to operating temperature C. sensitivity to switching noise D. all of the above E. none of the above

63 COLLABORATIVE CLICKER QUIZ (CCQ) Question 3 If the SRAM read float delay exceeds the processor s write data generation delay: A. bus fighting might occur B. the wrong value might be read by the processor C. metastability might occur D. all of the above E. none of the above Hint: Consider a read cycle followed by a write cycle

64 HOMEWORK PRACTICE CPU t CY t AD t AH t RS t RH t DD t WH t WZ Value 100 ns 30 ns 10 ns 20 ns 10 ns 40 ns 20 ns 10 ns Draw read cycle followed by write cycle SRAM t AA t CE t OE t OH t OZ t IS t IH t WP t AW t CW Value 20 ns min 20 ns min 10 ns min 0 ns min 30 ns max 20 ns min 10 ns min 10 ns min 20 ns min 20 ns min

Wed. Sept 20 Announcements

Wed. Sept 20 Announcements HW/Lab 5 Posted Lab 5 is done in pairs HW is probably more intensive than the lab. Module 1 Clicker Quiz Friday All module 1 fair game. Focus on stuff not yet quizzed on. [2.A]-1