FPGA IO Resources. FPGA pin buffers can be configured for. IO columns include Xilinx SelectIO resources. Slew rate. Serializer/Deserializer (IOSERDES)
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1 FPGA IO Resources FPGA pin buffers can be configured for Voltage impedance, Slew rate Pull(up/down) IO columns include Xilinx SelectIO resources Register (SDR/DDR in IOLOGIC) Fine grained delay adjustment (IODELAY) Serializer/Deserializer (IOSERDES) 121
2 FPGA IO Resources Challenge: High Data Rates, Low Power (!) IODDR (IDDR/ODDR) 122
3 FPGA IO Resources Even Higher Rates: LVDS Serial Transmission Panasonic GP MH322 LVDS Transmission 123
4 FPGA IO Resources LVDS: Low Voltage Differential Signalling 124
5 FPGA IO Resources LVDS: Low Voltage Differential Signalling 125
6 LVDS Deserializer Steps for deserialization Receive signal with proper termination and convert from differential to single ended Recover transmission clock from LVDS clock Align input data to recovered clock (sub bit) Convert serial data to parallel data Align parallel data at word level 126
7 LVDS Deserializer Steps for deserialization Receive signal with proper termination and convert from differential to single ended Recover transmission clock from LVDS clock Align input data to recovered clock (sub bit) Convert serial data to parallel data Align parallel data at word level 127
8 FPGA IO Resources IBUF(G)DS Primitive for buffering input differential signals G variant must be used when signal is clock and output goes to MMCM/PLL Optional 100 Ohm termination (for LVDS) 128
9 LVDS Deserializer Steps for deserialization Receive signal with proper termination and convert from differential to single ended Recover transmission clock from LVDS clock Align input data to recovered clock (sub bit) Convert serial data to parallel data Align parallel data at word level 129
10 Reminder: FPGA Clocking MMCM Multiply input clock by the serialization factor Feedback not required, we don t care about phase alignment Outputs go to Ios (fast clock) and internal logic (slow clock) Which buffers to use? (BUFG/BUFR/BUFIO) 130
11 Reminder: FPGA Clocking MMCM Multiply input clock by the serialization factor Feedback not required, we don t care about phase alignment Outputs go to IOs (fast clock) and internal logic (slow clock) Which buffers to use? (BUFG/BUFR/BUFIO) Use BUFG whenever possible (global reach) Use BUFR/BUFIO when BUFG is not fast enough 131
12 LVDS Deserializer Steps for deserialization Receive signal with proper termination and convert from differential to single ended Recover transmission clock from LVDS clock Align input data to recovered clock (sub bit) Convert serial data to parallel data Align parallel data at word level 132
13 FPGA IO Resources IODELAY (IDELAY/ODELAY) Primitive for fine grained delay on pin to fabric or fabric to pin paths 31 taps (delay values from original signal) Delay increments are PVT independent Can change delay during operation Useful for calibration of delay to daughterboards etc 133
14 LVDS Deserializer IDELAY Calibration Span range of IDELAY, looking for a transition in the output When a transition is encountered, we increase or decrease the IDELAY by half a bit period Afterwards, the sampling is in the middle of the data eye Discussion: limitations for this type of calibration 134
15 LVDS Deserializer Steps for deserialization Receive signal with proper termination and convert from differential to single ended Recover transmission clock from LVDS clock Align input data to recovered clock (sub bit) Convert serial data to parallel data Align parallel data at word level 135
16 FPGA IO Resources SERDES (Serializer/Deserializer) 136
17 FPGA IO Resources SERDES (Serializer/Deserializer) SDR/DDR input/output Up to 8 bits SDR/DDR with a single SERDES primitive, up to 14 bits DDR with two SERDES primitives (master/slave) CLK and CLKDIV must be phase aligned Outputs of parallel BUFR and BUFIO are phase aligned by design, for this purpose Bitslip mechanism for aligning data at word level 137
18 Implementation Constraints Implementation constraints affect IO placement (pin where signal is connected) IO buffer type (voltage of pin) IO buffer properties (slew, pullup etc) Timing Clock period Offsets before and after clock Multi cycle paths etc. Resource placement 140
19 Implementation Constraints IO constraints Placement: LOC constraint NET <signal> LOC=<pin name> Buffer type (IOSTANDARD=<pin type>) LVTTL, LVCMOS12/15/18/25/33, LVDS Many others Same type for all pins in a bank Drive strength (DRIVE=<mA>) PULLUP/PULLDOWN 141
20 Implementation Constraints Resource placement LOC constraint can also place Slices, BRAMs, DSPs AREA_GROUP and RANGE constraints Define a placement constraint for all logic of a certain type within the block May be specified separately for each resource type: Logic/Distributed RAM/Block RAM/DSP Example: constrain all logic driven by a BUFR to the clock region of the BUFR: AREA_GROUP "pblock_bufr" RANGE=CLOCKREGION_X1Y2:CLOCKREGION_X1Y2; 142
21 Further Reading Xilinx 7 Series IO Resources User Guide Xilinx Constraints Guide Xilinx PlanAhead Floorplanning Tutorial 143
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