Xilinx XC4VLX25-FF668AGQ FPGA. IOB Circuit Analysis

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1 Xilinx XC4VLX25-FF668AGQ FPGA IOB Circuit Analysis For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel:

2 Xilinx XC4VLX25-FF668AGQ FPGA IOB Some of the information in this report may be covered by patents, mask and/or copyright protection. This report should not be taken as an inducement to infringe on these rights Chipworks Incorporated This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization's corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. CAR VKJS Revision 1.0 Published: September 8, 2005 Revision 2.0 Published: May 30, 2008

3 Xilinx XC4VLX25-FF668AGQ FPGA IOB Table of Contents - Overview - Input/Output Block - Data Input Path - Data Output Path - Differential Termination - Tri-State Control - Data Input Path Control - Data Output Path Control - Differential Termination Control - Input Protection Control - Naming Conventions - Signal Cross-Reference List - Report Evaluation

4 Xilinx XC4VLX25-FF668AGQ FPGA IOB Overview List of Figures... Page 1 List of Schematics... Page 2 Introduction... Page 6 Device Summary Sheet... Page 7

5 Xilinx XC4VLX25-FF668AGQ FPGA IOB Page 1 List of Figures Package Markings Die Markings Package X-Ray Die Photograph Annotated Die Photograph Metal Register Cell Register Cell Register Cell Register Cell Register Cell Latch Definition Flip Flop Definition Definition of Level Shifter Definition of Level Shifter Definition of Level Shifter Definition of Level Shifter Definition of Level Shifter Definition of Level Shifter Multiplexer Multiplexer Delay Latch Element Delay Element to 1 Multiplexer XNOR Definition

6 Xilinx XC4VLX25-FF668AGQ FPGA IOB Page 2 List of Schematics Input/Output Block Data Input Path Input Buffers Input Protection Differential Input Buffer Differential Input Buffer Single Ended Input Buffer Differential Input Amplifier Input/Output Registers Data Input Logic Data Input Mux Data Input Mux Data Input Mux IDelay Fixed Delay Line to 1 Tapped Delay Line Multiplexers Bit Tapped Delay Line Serial to Parallel Converter Data Input Shift Register Data Input Select Data Output Path Data Output Logic Output Data Buffers to 1 Parallel to Serial Converter Output DDR Register Output DDR Register 2A Output DDR Register 2B Data Output Selection

7 Xilinx XC4VLX25-FF668AGQ FPGA IOB Page Data Output Multiplexer Data Output Buffer I Data Output Pull Up Drivers I Data Output Pull Down Drivers I Data Output Driver I Data Output Buffer II Data Output Pull Up Drivers II Data Output Pull Up Driver Data Output Pull Up Driver Data Output Pull Up Driver Data Output Pull Up Driver Data Output Pull Up Driver Data Output Pull Up Driver Data Output Pull Up Driver Data Output Pull Down Drivers II Data Output Pull Down Driver Data Output Pull Down Driver Data Output Pull Down Driver Data Output Pull Down Driver Data Output Pull Down Driver Data Output Pull Down Driver Data Output Driver II Differential Termination Tri-State Control Tri-State Configuration Register Tri-State Configuration Latches Tri-State Configuration Latches Tri-State Configuration Latches Tri-State Configuration Latch Clocks Tri-State Parallel to Serial Converter

8 Xilinx XC4VLX25-FF668AGQ FPGA IOB Page ISERDES Tri-State Control OSERDES Tri-State Control Data Input Path Control Data Input Control Logic I/O Data Select IDELAY Configuration Counter IDELAY Configuration Decoders Data Input Shift Register Control Register Clock Generator Data Input Control Logic Serial to Parallel Coverter Mux Control Register Clock Generator Control Data Input Control Logic Data Input Control Logic Data Output Path Control Parallel to Serial Converter Mux Control Data Output Control Logic Data Output Control Logic Output DDR Register 1 Mux Control Output DDR Register 2A Control Output DDR Register 2B Control Output DDR Register 2A & B Control Data Output Logic Options Data Output Driver Enable Data Output Slew Rate Control Data Output Control Logic Data Output Mux Select Configuration Select Data Output Control Logic Data Output Control Logic 5

9 Xilinx XC4VLX25-FF668AGQ FPGA IOB Page Differential Termination Control Differential Termination Logic Differential Termination Logic Differential Termination Logic N-type Resistance Control N-type Resistance Control Pull Up Resistance Control Pull Down Resistance Control P-type Resistance Control Differential Termination Control Options Input Protection Control Input Protection Control Logic Input Protection Control Logic 2

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