The Next Generation 65-nm FPGA. Steve Douglass, Kees Vissers, Peter Alfke Xilinx August 21, 2006
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1 The Next Generation 65-nm FPGA Steve Douglass, Kees Vissers, Peter Alfke Xilinx August 21, 2006 Hot Chips, 2006
2 Structure of the talk 65nm technology going towards 32nm Virtex-5 family Improved I/O Benchmarking Virtex-5 LUT6 fabric New Microblaze in Virtex-5 fabric Conclusion Hot Chips, 2006 slide 2
3 65nm Process Technology 40-nm gate length (physical poly) 1.6nm oxide thickness (16 Angstrom) ~5 atomic layers Triple-Oxide II technology 3 oxide thicknesses for optimum power and performance 1.0 Vcc core Lower dynamic power Mobility engineered transistors (strained silicon) Maximum performance at lowest AC power 65-nm Transistor Cross Section Over 1 Billion Transistors on a 23 x 23 mm Chip Hot Chips, 2006 slide 3
4 FPGAs Drive the Process 180 nm 150 nm 130 nm 90 nm 90nm Low cost New process technology drives down cost FPGAs can take advantage of new technology faster than ASICs and ASSPs 300mm wafers Low cost Triple Oxide Low power FPGA 2010: 32 nm, 5 Billion transistors 65 nm 45 nm 32 nm 12 layer copper, 1 volt core 1.0 Volt The cost of IC development increases. Therefore customers want to buy reconfigurable and programmable platforms, instead of developing their own. Hot Chips, 2006 slide 4
5 Challenges Higher leakage current and stand-by power Lower Vcc: good for power, tough for decoupling 3.3-V compatibility is getting more difficult 1 billion transistors, large chips, heat density 12-layer chip, 10-layer package, 16-layer pc-board Faster transitions, 2 V/ns and 50 ma/ns per pin, Pc-board signal integrity problems Complex chip, complex package, complex board Hot Chips, 2006 slide 5
6 LX Platform Overview Hot Chips, 2006
7 Two Generations of ASMBL (Application-Specific Modular BLock Architecture) Virtex-4 Virtex-5 Serial I/O Hot Chips, 2006 slide 7
8 2 nd Generation of ASMBL Easy to create sub-families LX : Logic + parallel IO LXT: Logic + serial I/O LX LXT Four Platforms SXT: DSP + serial I/O FXT: PPC + fastest serial I/O SXT FXT Hot Chips, 2006 slide 8 Many choices to optimize cost and performance
9 System components High-Performance 6-LUT Fabric More Configuration Options 36Kbit Dual-Port Block RAM / FIFO with ECC 25x18 Multiplier DSP Slice with Integrated ALU SelectIO with ChipSync + XCITE DCI 550 MHz Clock Management Tile DCM + PLL Hot Chips, 2006 slide 9
10 Virtex-5 Logic Architecture True 6-input LUTs with dual 5-input LUT option 1.4 times the value for actual logic only 1.15 times the cost in silicon area. 64-bit RAM per M-LUT about half of all LUTs 32-bit or 16-bit x 2 shift register per M-LUT RAM64 SRL32 RAM64 SRL32 RAM64 SRL32 RAM64 SRL32 LUT6 LUT6 LUT6 LUT6 Register/ Latch Register/ Latch Register/ Latch Register/ Latch Hot Chips, 2006 slide 10
11 Virtex-5 Virtex-4 Routing More symmetric pattern, connecting CLBs More logic reached per hop Same pattern for all outputs Fast Connect 1 Hop 2 Hops 3 Hops Hot Chips, 2006 slide 11
12 BRAM/FIFO 36 Kbit BRAM Integrated FIFO Logic for multi-rate designs Built-in ECC Cascadable to build larger RAM arrays Dual Port: a read and write every clock cycle Performance up to 550 MHz Hot Chips, 2006 slide 12
13 General Purpose I/O (Select I/O) All I/O pins are created equal Compatible with >40 different standards Vcc, output drive, input threshold, single/differential, etc Each I/O pin has dedicated circuitry for: On-chip transmission-line termination (serial or parallel) Fine timing adjustment in 75 ns steps (IDELAY + ODELAY) Serial-to-parallel converter on the input (CHIPSYNC) Parallel -to-serial converter on the output (CHIPSYNC) Clock divider, and high-speed regional clock distribution Ideal for source-synchronous I/O up to 1 Gbps Hot Chips, 2006 slide 13
14 75-ps Incremental Alignment CLK DATA MHz (calibration clk) ChipSync IDELAY INC/DEC ISERDES IDELAY CNTRL FPGA Fabric State Machine Calibration clock can be internal or external 64 delay elements of ~ 70 to 89 ps each Hot Chips, 2006 slide 14
15 ISERDES for Incoming Data Data CLK ChipSync ISERDES n CLKDIV FPGA Fabric CLK BUFIO BUFR Clock frequency division widens internal data path n = 2, 3, 4, 5, 6, 7, 8, 10 bits Dynamic signal alignment Bit alignment, Word alignment, Clock alignment Supports Dynamic Phase Alignment (DPA) using IDELAY Hot Chips, 2006 slide 15
16 OSERDES for Outgoing Data ChipSync n OSERDES m FPGA Fabric CLK DCM/PMCD CLKDIV Parallel-to-Serial converter Data SERDES: 2, 3, 4, 5, 6, 7, 8, 10 bits Three-state control SERDES: 1, 2, 4 bits Hot Chips, 2006 slide 16
17 Virtex-5 Applications Benchmarks Hot Chips, 2006
18 One MPEG4 Video Decoder High Definition resolution 720 vertical video lines, progressive RAM Memory Controller MPEG 4 Decoder Copy Controller Shared Memory Parser 1 FIFO Motion Comp. Object FIFO Texture Update Object 8 FIFO Object FIFO Inverse scan, Prediction, Inverse AC DC Prediction IDCT DCT Coeff Inverse Quantisatio n / IDCT Texture/ID CT Object FIFO Hot Chips, 2006 slide 18
19 8 MPEG4 decoders RAM RAM Off Chip Frame Memories Eight Ports of Compressed Video In Memory Memory Controller Controller Mpeg4 Decoder Mpeg4 Decoder Mpeg4 Decoder Mpeg4 Decoder Mpeg4 Decoder Mpeg4 Decoder Mpeg4 Decoder Mpeg4 Decoder Eight Ports of De-Compressed 720p Video Out Category Virtex-4 Virtex-5 Tools XST/ISE i XST/ISE 8.2i Devices XC4VFX Virtex5 part Hot Chips, 2006 slide 19
20 8 Decoders: Resources Diff. = ,809 Design Virtex-4 Virtex-5 Resources Used Used Registers 21,248 20,242 LUTs 67,523 44,148 BlockRAMs DSP Elements % fewer LUTs dramatic improvements for multiplexers, memory, and misc. logic Same VHDL source code used for both designs Hot Chips, 2006 slide 20
21 Logic Synthesis-Driven Results Virtex-5 Virtex-4 35,000 30,000 25,000 20,000 15,000 10,000 5,000 0 <= Hot Chips, 2006 slide 21 Number of Inputs Synthesis uses 6-input LUTs efficiently : fewer logic levels 23% increase in synthesized frequency, from 95MHz to 117MHz From 720p to 1080p video standards with little effort
22 Quad-Port Memory in Four LUT6 Read data Write Port: Four LUT6s share the data input and can also share a distributed write address Read Ports: Three independent read operations Write data 32 Write Port Register File 32X32 LUT Read Port 32 x 32 Quad-Port RAM structure in 64 LUTs Common write address LUT Independent read address Associated data 6x density improvement over Virtex-4 Common write data LUT Independent read address Associated data LUT Independent read address Associated data Hot Chips, 2006 slide 22
23 Application Example: new MicroBlaze 5.0 ILMB IOPB Instruction-side bus interface Bus IF Program Counter Instruction Buffer Instruction Decode Add/Sub Shift/Logical Multiply Register File 32X32b Data-side bus interface Bus IF DLMB DOPB Better use of new LUTs 1269 LUT4s in Virtex-4, MB LUT6s in Virtex-5, MB 5.0 from 3 stage -> 5 stage pipeline new processor: from 0.92 DMips/MHz to 1.14 DMips/MHz 180MHz -> 201 MHz 166 -> 230 Dhrystone Mips Use new 6 LUT, 2 stage deeper pipe, 10% more MHz, 39% better performance Hot Chips, 2006 slide 23
24 Suite of Benchmarks Suite of 74 designs run against ISE8.1i Slow speedgrade (-10) Virtex-4 4 compared to slow speedgrade (-1) Virtex Percent Improvement of Virtex-5 over Virtex Avg of Designs 0 ~30% average advantage for Virtex-5 5 fabric vs. Virtex-4 - As high as 56% advantage for some designs Hot Chips, 2006 slide 24
25 Virtex-5: Summary Leading 65 nm technology FPGA platform Better input and output I/O on all pins New 6-input LUT logic that is 30% better Demonstrated example of video benchmark with 35% fewer LUTs and 23% increased frequency New Microblaze with 39% improved performance Expect more: new announcements on serial I/O and integrated processor technology very soon Hot Chips, 2006 slide 25
26 Appendix: Virtex-5 LX Hot Chips, 2006
27 Virtex-5 LX Platform 5VLX30 5VLX50 5VLX85 5VLX110 5VLX220 5VLX330 Logic Cells 30,720 46,080 82, , , ,776 LUT6/FFs Distributed RAM Kbits 19, , , ,120 1, ,240 2, ,360 3,420 Block RAM Kbits 1,152 1,728 3,456 4,608 6,912 10,368 CMTs DSP48E Slices Total I/O Banks EasyPath No No Yes Yes Yes Yes Package Size IO FF FF FF FF , ,200 Hot Chips, 2006 slide 27
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