Architecture- level Security Issues for main memory. Ali Shafiee

Transcription

1 Architecture- level Security Issues for main memory Ali Shafiee

2 Aganda Replay- A;ack (bonsai) merkle tree NVM challenages Endurance stealing Side- channel A;ack due to resource sharing Time channel a;ack Covert channel a;ak Memory address ObfuscaGon

3 Why Memory? Secure CPU can protect computagon Memory is passive, on the crigcal path, and power hungry!

4 Replay A;ack Secret Key- Based EncrypGon is not enough We need unique seed per block per access.

5 Challenge One global Counter Need to update the engre memory! One on- chip counter per cache line 4B counter Occupy so much space! SoluGon Small counter per line Store in- memory Log(n) access / o(1) on- chip storage

6 Bonsai Merkle Tree (I) Assign New LPID on any block counter overflow

7 Bonsai Merkle Tree(II)

8 Non- VolaGle Memory (NVM) PCM is resistive memory: High resistance (0), Low resistance (1) PCM cell can be switched between states reliably and quickly

9 Stealing An NVM DIMM! 158 hard disks from ebay (2003) 74% contained old data Only 9% properly sanigzed Stolen smart Phone! i- NVMM Working set is kept un- encrypted Data predicted as not in working set à encrypt In turn off à encrypt all un- encrypted data

10 Endurance No more than 100 Million write!

11 DEUCE

12 Resource Sharing Branch- predictor, on- chip network, Cache, memory controller SD 0 SD 1 Core 0 $ Bus Core 1 $ Memory Requests per 5000 cycles Memory Time (cycle) 1

13 Temporal ParGGoning Each core has a slot to access memory Each core has its own queue SD 0 SD 1 Turn SD 0 Arbiter SD 1 Arbiter SD 0 SD 1 SD N DRAM Time Slots Time TransacGon Scheduler Bank 0 Bank 1 Bank 2 Bank 3

14 Oblivious RAM Encrypted computagon using secure processor Oblivious remote storage, secure computagon, etc. CPU (LLC) (op, addr, data) Write a0 d0 Read a0 Read a1 Read a0 On-chip ORAM Controller DRAM Obfuscated addr & ciphertext: Read a_#+> %&X Write a_=^+ 14

15 Path ORAM PosiGon Map: map each block to a random path Invariant: if a block is mapped to a path, it must be on that path ORAM controller DRAM root (B3, 0) Posi?on Map Block Path B0 0 B1 3 B2 3 B3 0 B4 1 (B0, 0) (B2, 3) dummy dummy dummy (B1, 3) path

16 Path ORAM OperaGon Access Block 1 Read all blocks on path 3 Remap B1 to a new random path Write as many blocks as possible back to path 3 (keep the invariant) ORAM controller dummy (B1, 1) Posi?on Map Block Path B0 0 B1 X 3 1 B2 3 B3 0 B4 1 DRAM root (B3, 0) (B0, 0) (B2, 3) dummy dummy dummy (B1, 3) path

17 Recursive ORAM Underlying ORAM + Recursion Freecursive ORAM Data ORAM PosMap ORAM PosMap ORAM... Block Pos Block N Pos N+1 Block Pos Pos(0), Pos(1),,Pos(X 1) 2 N+N/X- 1 N- 1 17

18 Outline Background on Path ORAM Our three improvements Idea 1: Cache PosMap ORAM + Security Fix recursive ORAM access page table walk! On- chip PosMap CR3 virtual address Input address a Block a Block Pos PosMap block 1 PosMap block 2 Pos(a[high]) PosMap ORAM PosMap ORAM Pos(a) Data ORAM mul?- level page table 18

19 Recursive ORAM Access Request for Block 0 Secure processor Block 0 On- chip PosMap Block Pos N Pos(N) N+1 External memory Pos(0) Pos(N) Data ORAM Pos(0), Pos(1),,Pos(X 1) PosMap ORAM Block Pos 0 Pos(0) 1 Pos(1) 2 N- 1 19

20 Cache PosMap Request for Block 0 PLB cache recent PosMap blocks On- chip PosMap Block Pos N Pos(N) N+1 Secure processor Block 0 External memory Pos(0) Pos(N) Data ORAM Pos(0), Pos(1),,Pos(X 1) PosMap ORAM Block Pos 0 Pos(0) 1 Pos(1) 2 N- 1 20

21 Cache PosMap Request for Block 0 Request for Block 1 PLB cache recent PosMap blocks On- chip PosMap Block Pos N Pos(N) N+1 Secure processor Block 1 External memory Pos(1) PosMap PLB Hit/Miss depends ORAM on access pavern! Data ORAM Pos(0), Pos(1),,Pos(X 1) Block Pos 0 Pos(0) 1 Pos(1) 2 N- 1 21

22 Security Fix: Unified ORAM Request for Block 0 Secure processor PLB cache recent PosMap blocks On- chip PosMap Block Pos N Pos(N) N+1 External memory Pos(N) ORAM for Data & PosMap Block Pos 0 Pos(0) 1 Pos(1) 2 N- 1 Pos(0), Pos(1),,Pos(X 1) 22

23 Security Fix: Unified ORAM Request for Block 0 Secure processor PLB cache recent PosMap blocks On- chip PosMap Block Pos N Pos(N) N+1 External memory Block 0 Pos(0) ORAM for Data & PosMap Block Pos 0 Pos(0) 1 Pos(1) 2 N- 1 Pos(0), Pos(1),,Pos(X 1) 23

24 Security Fix: Unified ORAM Request for Block 0 Request for Block 1 Secure processor PLB cache recent PosMap blocks On- chip PosMap Block Pos N Pos(N) N+1 External memory Block 1 Pos(1) ORAM for Data & PosMap Block Pos 0 Pos(0) 1 Pos(1) 2 N- 1 Pos(0), Pos(1),,Pos(X 1) Total # of ORAM accesses: small leakage 24