Embedded Memories. Advanced Digital IC Design. What is this about? Presentation Overview. Why is this important? Jingou Lai Sina Borhani

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1 1 Advanced Digital IC Design What is this about? Embedded Memories Jingou Lai Sina Borhani Master students of SoC To introduce the motivation, background and the architecture of the embedded memories. To specify some Design parameters for low power, high performance designs and introduce new cell topologies. Optimization on access pattern related techniques. Presentation Overview Why is this important? Motivation Background Principle of locality Embedded memory architecture (Memory hierarchy) About embedded NVM.. Optimizations on circuit and system view review of SRAM and DRAM basics SRAM new cell topologies Embedded DRAM optimization on access speed Conclusion Fast growth of VLSI lead the memory to High demand of: High Performance Low Power Small Area Sandy Bridge die with major sections labeled. Source: Intel

2 2 Why is this important? Why is this important? Figure shows that the Same bandwidth edram could as much as have more then 10 times less power then DRAM chip. MPU Versus DRAM Performances The widened gap drive the development of the e- mem. Two factors will make it easier complexity of process technology larger die size Background Background + SRAM has highest speed - Price and area hungry Principle of locality temporal locality The same data will be access frequently. spatial locality The same region of data will be access frequently. Relative performance for Embedded Memories.[1] Advantages of Memory Hierarchy reduce cost of implementation improved performance reducing power consumption

3 3 Embedded Memory Architecture Embedded Memory Architecture Memory Hierarchy[1] Registers Highest level memory, usually made by SRAM Operation speed =Processor core Cache keep subset data from lower level. also has hierarchy: e.g., L1, L2,L3.. Scratch pad Memory similar to L1 level cache but keep calculation result instead of data copies from main memory. Off-chip memory main memory Few words about embedded NVM Massive storage (which is un-important here ) Nonvolatile Memory can keep data for more than 10years and re-write at least 1 million times. Slower than the VM, due to materials physical limitations.

4 4 According to Moore s Law[2]: Sub-threshold Effect leakage current: Stressed when process technology scale down[2] Standby Disable WL Write Enable WL Apply voltage to both BLs to flip like in SR flipflop. Static Noise Margin(SNM) Write Margin(WRM) Cell Current Icell distribution Read Pre-charge both BLs, Enable WL Read and write BL share

5 5 Static Noise Margin(SNM) Definition: SNM is the maximum amount of noise voltage VN that can be tolerated at the both inputs of the cross-coupled inverters in two different directions while inverters still maintain bi-stable operating points and cell retains its data. [2] Write Margin(WRM) The write margin (WRM) is defined as the rest of potential difference between the BL level at which the data is flipped and the end-point (e.g., GND) [2]

6 6 SRAM new cell topology Cell Current Icell distribution It illustrates how fast BL will be discharged. Icell determines the access time.[2] mainly 8T-SRAM cell Advantage of 8T- SRAM cell Read stability (free from SNM) Increased Cell current Icell (using low VT for reading port) Dynamic and leakage power(no precharge on unselected BL, using high VT for inverters inside the cell) SRAM new cell topology SRAM new cell topology RdBL leakage will be further reduced by the 10-T SRAM cell[2]: 10T-SRAM cell

7 7 SRAM new cell topology DRAM Optimization on systematic view The comparisons of design options is shown[2]: 8T and 10T are designed for low power and high performance. 3T-1C DRAM[4]: Standby Disable WWL and RWL Read Pre-charge BL2, Enable RWL Write Apply data on BL1, Enable WWL DRAM Optimization on systematic view DRAM Optimization on systematic view DRAM has more density then SRAM Power hungry Better cell stability 1T-1C DRAM[5] Standby disable WL write enable WL, apply voltage on BL to charge Capacitor Read enable WL, and sense the BL (need to charge up afterwards)

8 8 DRAM Optimization on access speed DRAM Optimization on access speed For DRAM access[2]: Embedded memory Suppliers Conclusions Memory hierarchy make small embedded memory keep data fast and efficiently under the principal of locality. SRAM cell design important parameters: Static Noise Margin Write Margin Cell current and leakage.. 8-T SRAM and 10-T SRAM can address those problems Lists of several companies and their recent embedded DRAM products. Use bank interleaving to optimize DRAM structure.

9 9 References [1] K. Zhang (Ed.), Embedded Memories for Nano-Scale VLSIs, Integrated Circuits and Systems Series, Springer, [2] R. L. Smith, Estimating tails of probability distributions, Ann. Stats., 15(3): , [3] A. J. Bhavnagarwala, X. Tang, and J. D. Meindl, The impact of intrinsic device fluctuations on CMOS SRAM cell stability, IEEE J. Solid- State Circuits, 36(4): , [4] [5]