80 SEGMENT DRIVER FOR DOT MATRIX LCD S6A2067 S6A SEG DRIVER FOR STN LCD

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Candace Cobb
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1 80 SEGENT DRIVER FOR DOT ATRIX LCD S6A2067 S6A SEG DRIVER FOR STN LCD Jan Ver. 0.1 Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team. Precautions for Light Light has characteristics to move electrons in the integrated circuitry of semiconductors, therefore may change the characteristics of semiconductor devices when irradiated with light. Consequently, the users of the packages which may expose chips to external light such as COB, COG, TCP and COF must consider effective methods to block out light from reaching the IC on all parts of the surface area, the top, bottom and the sides of the chip. Follow the precautions below when using the products. 1. Consider and verify the protection of penetrating light to the IC at substrate (board or glass) or product design stage. 2. Always test and inspect products under the environment with no penetration of light. 1

2 S6A SEGENT DRIVER FOR DOT ATRIX LCD INTRODUCTION The S6A2067 is a LCD driver lc which is fabricated by low power COS technology. Basically this LSl consists of 40 x 2 bit bi-directional shift register, 40 x 2 bit data latch and 40 x 2 bit LCD driver (refer to Figure 1). This lc can be used as segment driver. FUNCTION Dot matrix LCD driver with 80 channel output. Input/Output signal Output: 40 x 2 channel waveform for LCD driving Input: Serial display data and control signal pulse from the controller lc. Bias voltage (V1 to V4) FEATURES Display driving bias: static - 1/5 Power supply voltage: 2.7V to 5.5V Supply voltage for display: 3.0V to 13.0V (V LCD = V DD - V EE ) Interface Driver (cascade connection) S6A0065, Other S6A2067 Controller S6A0069 S6A0070 S6A0073 COS Process 100QFP or bare chip available 2

3 80 SEGENT DRIVER FOR DOT ATRIX LCD S6A2067 BLOCK DIAGRA S1 S2 Part 1 S39 S40 S41 S42 Part 2 S79 S80 V1 V2 V3 V4 LCD DRIVER LCD DRIVER Data Latch (40 bits) Bidirectional Shift Register (40 bits) Data Latch (40 bits) Bidirectional Shift Register (40 bits) VDD VSS VEE SW CL1 CL2 Contr Logic DL1 SHL1 DR1 DL2 SHL2 DR2 Figure 1. S6A2067 Functional Block Diagram 3

4 S6A SEGENT DRIVER FOR DOT ATRIX LCD 4 PIN CONFIGURATION S71 S72 S73 S74 S75 S76 S77 S78 S79 S80 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S6A S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S NC NC DR2 DL2 DR1 DL1 CL2 VDD NC NC SHL2 SHL1 CL1 GND V4 V3 V2 V1 VEE S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S Figure QFP Top View

5 80 SEGENT DRIVER FOR DOT ATRIX LCD S6A2067 PAD DIAGRA S6A2067 Y (0, 0) X Chip size: Pad size: Unit: µm

6 S6A SEGENT DRIVER FOR DOT ATRIX LCD PAD CENTER COORDINATES Pad Pad Coordinate Pad Pad Coordinate Pad Pad Coordinate Num. Name X Y Num. Name X Y Num. Name X Y 1 S V S S V S S V S S V S S CL S S SHL S S SHL S S VDD S S CL S S DL S S DR S S DL S S DR S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S VEE S S V S S NOTE: S6A2067 arking: easy to find the PAD No.6, No.90. 6

7 80 SEGENT DRIVER FOR DOT ATRIX LCD S6A2067 PIN DESCRIPTION PIN (NO.) I/O Name Description Interface V DD (42) Power Operating Voltage For logical circuit ( V) Power V SS (GND)(36) 0V (GND) Supply V EE (31) Negative Supply Voltage V1, V2(32,33) Input LCD driver output voltage level For LCD driver circuit Bias voltage level for LCD drive (Select level) Power V3, V4(34,35) Input Bias voltage level for LCD drive (Non-select level) S1 - S40 Output LCD driver LCD driver output LCD SHL1(38) Input Part 1 Data Interface Selection of the shift direction of shift register SHL1 VDD DL1 OUT DR1 IN VSS IN OUT V DD or V SS DL1, DR1 (44,45) Input Output Data Input/output of shift register (part 1) Controller or S6A2067/ S6A0065 S41 - S80 Output LCD driver LCD driver output LCD SHL2 (39) Input Part 2 Data Interface Selection of the shift direction of shift register SHL2 VDD VSS DL2 OUT IN DR2 IN OUT V DD or V SS DL2, DR2 (46,47) Input Output (48) Input Alternated signal for LCD driver output CL1, CL2 (37,43) NC (40,41,49,50) Input Data shift/ latch clock Data Input/output of shift register (part 2) The alternating signal to convert LCD drive waveform to AC CL1 : Data latch clock CL2 : Data shift clock No connection Controller or S6A2067/ S6A0065 Controller NC 7

8 S6A SEGENT DRIVER FOR DOT ATRIX LCD AXIU ABSOLUTE LIIT (T A = 25 C) Characteristic Symbol Value Unit Operating Voltage V DD V Driver Supply Voltage V LCD V DD V DD +0.3 V Input Voltage 1 V ln V DD +0.3 V Input Voltage 2 (V1 - V4) V IN2 V DD V EE -0.3 V Operating Temperature T OPR Storage Temperature T STG C C NOTES: 1. Voltage greater than above may damage the circuit 2. V EE : connect a protection resistor (220Ω ± 5%) ELECTRICAL CHARACTERISTICS DC Characteristics (V DD = 2.7 to 5.5V, V DD -V EE = 3-13V, V SS = 0V, T A = -30 to 85 C) Characteristic Symbol Test condition in ax Unit Applicable pin Operating Current l DD f CL2 = 400kHz 1 ma V DD, V EE Supply Current l EE f CL1 = 1kHz 10 µa Input High Voltage V IH 0.7V DD V DD V CL1, CL 2,DL 1, Input Low Voltage V IL 0 0.3V DD DL 2, DR 1, Input Leakage Current l LKG V IN = 0 - V DD -5 5 µa SHL1, SHL2, Output High Voltage V OH I OH = -0.4mA VDD-0.4 DL 1, DL 2, Output Low Voltage V OL I OL = +0.4mA 0.4 V DR 1, DR 2 DR 2, Voltage Descending V D1 I ON = 0.1mA for one of S1 V D2 - S80 I ON = 0.05mA for each S1 - S80 Leakage Current I V V IN = V DD - V EE (Output S1 - S80: floating) 1.1 V (V1-V4)-S (S1-S80) µa V1 - V4 8

9 80 SEGENT DRIVER FOR DOT ATRIX LCD S6A2067 AC Characteristics (V DD = 2.7 to 5.5V, V DD -V EE = 3-13V, V SS = 0V, T A = -30 to 85 C) Characteristic Symbol Test condition in ax Unit Applicable pin Data Shift Frequency f CL 400 khz CL2 Clock High Level Width t WCKH 800 ns CL1, CL2 Clock Low Level Width t WCKL 800 CL2 Clock Set-up Time t SL from CL 2 to CL CL1,CL2 t LS from CL 1 to CL Clock Rise/Fall Time t R /t F 200 Data Set-up Time t SU 300 DL1,DL2,DR1,DR2 Data Hold Time t DH 300 DL1,DL2,DR1,DR2 Data Delay Time t D C L = 15pF 500 DL1,DL2,DR1,DR2 9

10 S6A SEGENT DRIVER FOR DOT ATRIX LCD TIING CHARACTERISTICS CL2 VIH VIL twckl VIL VIH tr twckh tf tdh tsu Data in (DL1,DL2) (DR1, DR2) VIH td VIL Data out (DL1,DL2) (DR1, DR2) VOH VOL tsl tls tls CL1 VIH VIL twckh tsu tr tf FL VIH VIL Figure 3. AC Characteristics 10

11 80 SEGENT DRIVER FOR DOT ATRIX LCD S6A2067 LCD OUTPUT WAVEFORS Output of Latch (DATA) V2 V2 V4 V4 OUTPUT (S1 - S80) V3 V3 V1 V1 11

12 S6A SEGENT DRIVER FOR DOT ATRIX LCD APPLICATION CIRCUIT CO1 - CO16 common signal LCD S6A0069 (controller) VDD D CLK1 CLK2 V1 V2 V3 V4 V5 S1 - S80 SHL1 SHL2 DL1 DR1 DL2 CL1 CL2 S6A2067 (seg driver) DR2 Segment signal S1 - S80 SHL1 SHL2 DL1 DR1 DL2 CL1 CL2 S6A2067 (seg driver) DR2 open VEE V1 V2 V3 V4 VEE V1 V2 V3 V4 VDD GND or Other Voltage 12

RW CH Segment Driver

RW CH Segment Driver Functions: Dot matrix LCD driver with two 40 channel outputs Bias voltage (V1 ~ V4) Input/output signals Input : Serial display data and control pulse from controller IC Output : 40 X 2 channels waveform