The following electrical characteristics apply when sealed in a Sanyo standard QIC-100 package.

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1 Ordering number: EN 6157 COS IC LC790YC,791YC Dot-matrix LCD Drivers Overview The LC790YC and LC791YC are segment driver ICs for driving large, dotmatrix LCD displays. They read bit parallel or serial input, display data from a controller into an 80bit latch, and then generate LCD drive signals corresponding to that data. The LC790YC and LC791YC feature mirrorimage pin assignments, allowing them to be used together to increase component density. They are designed to be used with the LC792YC common driver to drive large LCD panels. Features 80 builtin LCD display drive circuits 1/8 to l/128 display duty cycle Serial or bit parallel data input Chip disable for low power dissipation for largesized panels Bias supply voltags can be supplied externally Operating supply voltage and ambient temperature to 5.5 V logic supply ( V DD ) at Ta = 20 to 85 C - 8 to 20V LCD supply (V DD V EE ) at Ta = 20 to 85 C COS process Specifications The following electrical characteristics apply when sealed in a Sanyo standard QIC-100 package. Absolute aximum atings at Ta = 25 ± 2 C, V SS = 0 V Parameter Symbol atings Unit Logic supply voltge V DD max 0.3 to 7.0 V LCD supply voltage, See Note below. V DD V EE max 0 to 22 V Input voltage V I max 0.3 to V DD 03 C Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co., Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, JAPAN (ID) No /13

2 LC790YC, LC791YC Operating temperature range T opr 20 to 85 C Storage temperature range T stg 0 to 125 C Note V DD V 1 > V 3 > V > V EE Parameter Symbol atings Unit ecommended Operating Condltions at Ta = 20 to 85 C, V SS = 0V atings Parameter Symbol Conditions min typ max Unit Logic supply voltage V DD V LCD supply voltage V DD V EE See Notes 1 and V HIGHlevel input voltage V IH SDl, P/S, DISPOFF and 0.8V DD V, CDl, DI1 to DI3,, LOWlevel inpvt voltage V IL SDl, P/S,DISPOFF and,, Dl1 to DI3,, Notes 1. V DD V l > V 3 > V > V EE 2. At turn ON, the LCD supply should be energized after or simultaneously with the logic supply. At turn OFF, the logic supply should be cut after or simultaneously with the LCD supply. Electrlcai Characterfstlcs at Ta = 25 ± 2 C,V SS = 0V, V DD = 2.7 to 5.5 V 0.2V DD V shift clock frequency f 3.3 Hz pulsewidth t WC 100 ns pulsewidth t WL 100 ns DIn and to setup time t SETUP 80 ns DIn and to hold time t HOLD 80 ns to time t CL1 0 ns t CL2 100 ns to time t LC 100 ns rise time t 50 ns fall time t F 50 ns rise time t L 50 ns fall time t FL 50 ns Parameter Symbol Conditions HIGHlevel input current I IH P/S, DI1 to DI3, SDl,, V IN =V DD ;,,, and DISPOFF LOWlevel input current I IL CDl, P/S, DI1 to DI3,, VIN = VSS;,,, and DISPOFF atings min typ max Unit 1 µa 1 µa HIGHlevel output voltage V OH I OH = 00 µa V DD 0. V LOWlevef output voltage V OL I OL = 00 µa 0. V O1 to O80 driver ON resistance ON V DD V EE = 18 V, V DE V O = 0.25 V. See note 2 kω No /13

3 LC790YC, LC791YC Parameter Symbol Conditions 200 µa V DD to V SS standby supply current I ST V DD V EE = 18 V, f = 3.3 Hz, = V DD, no output load ; V SS V DD to V ss operating supply current I SS f = 3.3 Hz, I = khz, V DD V EE = 18 V, f = 52 Hz ;VSS Note V DE = V 1 or V 3, or V or V EE, V 1 = V DD, V 3 = 9/11 (V DD V EE ), V = 2/11 (V DD V EE ) Switching Characteristics at Ta = 25 ± 2 C,V SS = 0V, V DD = 2.7 to 5.5 V atings min typ max 1.0 ma 0.1 ma V DD to V EE operating supply current I EE f = 3.3 Hz, f = 5,156 khz, V DD V EE = 18V, f = 52 Hz ; V EE input capacitance C I f = 3.3 Hz ; 5 pf Unit atings Parameter Symbol Conditions min typ max Unit output delay time t D C L = 30 pf 200 ns Switching Characteristics Waveform t twc tf twc 0.8VDD 0.2VDD tset UP thold DI1 to 3 tcl (1) tl tcl (2) tfl twl tlc td td No /13

4 LC790YC, LC791YC No /13 Pad Layout (Top view) O1 O2 O3 O O5 O6 O7 O8 O9 O10 O11 O12 O13 O1 O15 O16 O17 O18 O19 O20 O21 O22 O23 O2 O25 O26 O27 O28 O29 O30 O80 O79 O78 O77 O76 O75 O7 O73 O72 O71 O70 O69 O68 O67 O66 O65 O6 O63 O62 O61 O60 O59 O58 O57 O56 O55 O5 O53 O52 O51 O31 O32 O33 O3 O35 O36 O37 O38 O39 O0 O1 O2 O3 O O5 O6 O7 O8 O9 O50 DI3 DI2 DI1 P/S DISPOFF VDD V VSS LC790YC O1 O2 O3 O O5 O6 O7 O8 O9 O10 O11 O12 O13 O1 O15 O16 O17 O18 O19 O20 O21 O22 O23 O2 O25 O26 O27 O28 O29 O30 O80 O79 O78 O77 O76 O75 O7 O73 O72 O71 O70 O69 O68 O67 O66 O65 O6 O63 O62 O61 O60 O59 O58 O57 O56 O55 O5 O53 O52 O51 O50 O9 O8 O7 O6 O5 O O3 O2 O1 O0 O39 O38 O37 O36 O35 O3 O33 O32 O31 DISPOFF P/S DI1 DI2 DI3 VSS V VDD LC791YC

5 LC790YC, LC791YC LC790YC Pad Location chip size :.830 mm x mm Pin_No. Name X Y Pin_No. Name X Y 1 O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O DISPOFF O P/S O V SS O V EE O V O V O O V DD O V O O DI O DI O DI O O O O No /13

6 LC790YC, LC791YC LC791C Pad Location chip size :.830 mm x mm Pin No. Name X Y Pin No. Name X Y 1 O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O DI O DI O DI O O V O V DD O O V O V O V EE O V SS O P/S O DISPOFF O O O No /13

7 LC790YC, LC791YC Block Diagram V Level LCD Drive Circuit (80 bits) 80 Level Shifter (80 bits) 80 2nd Latch (80 bits) 80 1st Latch (80 bits) VDD VSS DISP OFF DI3 DI2 DI1 bits Data Bus Interface CLK 20 Address Decoder Address Counter (7 bits) P/S SE/PA Control Chip Disable & Latch Control Pin Functions LC790YC Pin No. LC791YC Symbol I/O Function V SS Supply V DD 87 9 V EE V DD V SS is the logic supply. V DD V EE is the LCD supply V 3 Supply V V LCD panel drive voltage supplies V 1 and V EE are selected levels. V 3 and V are notselected levels. l00 81 I Display data Input clock (fallingedge trigger) I Chip disable. Data is read in when LOW, and not road in when HIGH I Display data latch clock (fallingedge trigger). On the falling edge, the LCD drive signals set by the display data are output I Serial data input DI3 bit parallel data input pins DI D11 I Data input LCD driver outputs O O8 O80 DI3 O3 O7 O79 DI2 O2 O6 O78 DI1 O1 O5 O77 In serial data input mode, DI1 to DI3 should all be tied HIGH or LOW. No /13

8 LC790YC, LC791YC LC790YC Pin No. LC791YC I LCD panel drive voltage output alternation control signal P/S I Data input mode select. bit parallel input when HIGH, and serial input when LOW O Symbol I/O Function Cascade connection pin for extension segment drivers. Data is read out when HIGH. Goes LOW after data is read out. Connected to the input of the next chip. LCD drive outputs. The output drive level is determined by the display data, signal and DISP OFF input as shown below. Q DISP OFF Output LOW LOW HIGH V 3 1 to to 1 Ol to O80 O LOW HIGH HIGH V DISPOFF I NC NC NC Note x = don t care (tied HIGH or LOW) O1 to O80 output control input pin. When LOW, is output on the O1 to 080 outputs, See the truth table. No connection. HIGH LOW HIGH V HIGH HIGH HIGH V EE LOW V 1 No /13

9 LC790YC, LC791YC Application Notes LCD Panel 1 V V (LC790YC) LC791YC V V V V (LC790YC) LC791YC (LC790YC) LC791YC 2 OD1 ED1 V V (LC790YC) LC791YC VDD controller LA to 13V OD1 ED1 FL CL1 CL2 OD2 ED2 V2 V V5 6 DI01 01 LC792YC 06 DI06 V2 V5 100 DI01 01 LC792YC 036 V5 V2 V LC790YC (LC791YC) LC791YC V LCD panel ( pixels) LC790YC LC790YC (LC791YC) (LC791YC) LC791YC V LC791YC V LC790YC (LC791YC) LC791YC V OD2 ED2 No /13

10 LC790YC, LC791YC LCD Panel 2 7 VDD V bit Data LC791YC-#8 LC791YC-#2 LC791YC-# FL DI01 controller LC792YC-#1 100 bit Data LCD panel ( pixels) 100 DI LC792YC-#2 LA5311 V5 V2 V2 V V5 6 V LC791YC-#8 2 2 LC791YC-# V LC791YC-#1 11 to 13V 2 bit Data bit Data 2 No /13

11 LC790YC, LC791YC 100 x 20-pixel LCD Panel Application A pixel LCD panel requires the following drivers. 3 x LC790YC (or LC791YC) drivers 2 x LC792YC drivers An example using l/l00 duty cycle is shown below. Frame Signal 1,79 (m,n) : pixel address Segment line (n) Common line (m) DI01 01 S/LS 02 LC792YC #1 063 DI06 06 DI01 01 S/LS 02 LC792YC #2 036 DI06 O37 to O6 are open. 1,1 2,1 63,1 6,1 65,1 66,1 100,1 01 1,2 2,2 63,2 6,2 65,2 66,2 100,2 02 1,79 1,80 1,81 1,82 LCD Panel ( pixels) 6,80 6,81 65,80 65,81 100,79 100,80 100,81 100, ,160 6,160 65, , ,161 6,161 65, , ,20 2,20 6,20 65,20 100, LC790YC (LC791YC) #1 LC790YC (LC791YC) #2 LC790YC (LC791YC) #2 Data latch clock Alternating signal Serial Data Data Shift clock P/S DI1 DI2 DI3 P/S DI1 DI2 DI3 P/S DI1 DI2 DI3 1. The LC792YC chips are cascaded by connecting DIO6 on chip I to DIO1 on chip 2. For a 100bit shift register, O37 to O6 on chip 2 are left open. 2. The LC790YC (or LC791YC) chips are cascaded by connecting on chip I to on chip 2, and on chip 2 to on chip 3. on chip I is tied to GND, and on chip 3 is not used. This configuration allows the input of 20bit serial data. No /13

12 LC790YC, LC791YC 100 x 20-pixel LCD Panel Timing Diagram 1,1 1,2 1,79 1,80 1,81 1,160 1,161 1,20 #1 SDO #2 #3 Chip 1 data read Chip 2 data read Chip 3 data read 1 frame (20 bits) 1,1 1,2 1,239 1,20 2,1 2,20 3,1 100,20 1st line data read 2nd line data read 1frame ( bits) #1 DIO1 01 1,1 2,1 98,1 99,1 100,1 1,1 99,1 100,1 #1 02 1,2 2,2 98,2 99,2 100,2 1,2 99,2 100,2 #2 # ,80 2,80 98,80 99,80 100,80 1,80 99,80 100,80 1,81 2,81 98,81 99,81 100,81 1,81 99,81 100,81 1,160 2,160 98,160 99, ,160 1,160 99, ,160 1,161 2,161 98,161 99, ,161 1,161 99, ,161 1,20 2,20 98,20 99,20 100,20 1,20 99,20 100,20 LCD driver output data No /13

13 LC790YC, LC791YC Segment Data Not ultiples of Example. LCD panel ( pixels) LC790YC # LC790YC # LC790YC #3 m,1 m,2,228 m,229 m,230 m1,1 m1,2,228 m1,229 m1,230 If this timing data is sent, data elements (m, 229), (m, 230), (m1, 229), (m1. 230)... will not appear in the output (O69 and O70 on chip 3). This is because the LC790YC (or LC791YC) converts serial/parallel data in bit units, which also decreases power dissipation. For data that is not a multiple of, like 230, the following scheme is used. m,1 m,2,228 m,229 m,230 m,231 m,232 Valid display data Dummy data In this case, (m, 231) is output on O71 on chip 3, and (m, 232) on O72 on chip 3. However, these outputs are not connected to the panel and are, therefore, invalid. ultiple of Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of June, Specifications and information herein are subject to change without notice. No /13

LC79401KNE. CMOS LSI Dot-Matrix LCD Drivers. Ordering number : ENA1419

LC79401KNE. CMOS LSI Dot-Matrix LCD Drivers. Ordering number : ENA1419 Ordering number : ENA1419 COS LSI Dot-atrix LCD Drivers Overview The is a 80-outputs segment driver LSI for graphic dot-matrix liquid crystal display systems. The latches 80 bits of display data sent from