Need more memory! What do we do if our 2K of SRAM isn t enough? Doing complex DSP calculations Large matrix math

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Dylan Davidson
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2 Need more memory! What do we do if our 2K of SRAM isn t enough? Doing complex DSP calculations Large matrix math We need a bigger scratch pad Must interface to external memory module!

3 The HCS12 Solution The way that the HCS12 deals with this problem is to use what is called Multiplexed External Bus Interfacing (MEBI) This basically takes the internal data/address bus and sends it out to the Port A and Port B pins. In this way, we are directly connecting the external SRAM to our processor.

4 The HCS12 Solution But why? This seems like a lot of work We can now, on startup, initialize our micro so that it s aware of this new memory. This involves writing to various registers (we ll get to this later) Altogether, this means that we can place our SRAM into the micro s address space and use it just as we would our embedded SRAM (there s just a lot more of it now).

5 Memory Hierarchy On the HCS12, the memory spaces are prioritized. External memory has the lowest priority. We should put the external SRAM into the space where other memory doesn t exist

6 Generally (micro signals) Let s consider a very general system for external memory interfacing The micro will send or receive only a few signals Address bus Data bus Read/Write (R/W ) Clock (CLK)

7 Generally (micro signals) Address bus Micro tells the SRAM which address it s interested in (read or write) Data bus Bidirectional Input to micro on read cycles Output from micro on write cycles

8 Generally (micro signals) R/W Micro tells the SRAM whether the current cycle is a read or a write. For a read cycle, R/W = 1 For a write cycle, R/W = 0 CLK Micro bus clock Is used to generate SRAM control signals combinationally (with the PLD).

9 Generally (SRAM signals) The external SRAM will require certain signals in order to perform its operations. Address bus Data bus OE CE WE

10 Generally (SRAM signals) Address bus/data bus are directly connected to the micro. OE : (R/W & CLK) Output enable Tells the SRAM to take control of the data bus and send out the read data. during the second half (CLK = ) of a read cycle during first half of read cycle and always during write cycles

11 Generally (SRAM signals) WE : ((R/W ) & CLK) Write enable Tells the SRAM to write the data on the data bus to the address on the address bus. The SRAM write occurs on the rising edge of WE. during second half (CLK = ) of write cycle during first half of write cycle and always during read cycles

12 Generally (SRAM signals) CE (ADDR[15] & CLK) Chip enable (chip select) Enables or disables the SRAM chip operation. This functionality is useful if you want to design a system with multiple SRAM chips. Notice, CE is a function of ADDR[15], which would mean that we could select between two 32KB SRAM chips, depending on the address. to enable chip (always in our case) to disable chip

13 Putting It Together Now that we understand the requirements of both sides of the transactions, let s start assembling the circuit We can assume that we will use a PLD to perform the generation of the SRAM signals (OE, WE, CE ) These signals are only a function of R/W, CLK and ADDR[15]

14 Putting It Together Micro DATA 8 or 16 SRAM ADDR R/W CLK ADDR[15] 16 PLD OE WE CE

15 CLK = t=0 Micro DATA 8 or 16 (Prev. Data) SRAM ADDR 16 (Prev. Addr) R/W CLK ADDR[15] PLD OE WE CE

16 CLK = t=t AH Micro DATA 8 or 16 (Prev. Data) SRAM ADDR 16? R/W CLK ADDR[15]? PLD OE WE CE

17 CLK = t=t AD Micro DATA 8 or 16 (Prev. Data) SRAM ADDR 16 (New Addr) R/W CLK ADDR[15] PLD OE WE CE

18 CLK = t=t AD +t PLD Micro DATA 8 or 16 (Prev. Data) SRAM ADDR 16 (New Addr) R/W CLK ADDR[15] PLD OE WE CE PLD Prop. Delay = t PLD

19 CLK = t=t/2 Micro DATA 8 or 16 (Prev. Data) SRAM ADDR 16 (New Addr) R/W CLK ADDR[15] PLD OE WE CE PLD Prop. Delay = t PLD

20 CLK = t=t/2+t PLD Micro DATA 8 or 16 (Prev. Data) SRAM ADDR 16 (New Addr) R/W CLK ADDR[15] PLD OE WE CE PLD Prop. Delay = t PLD

21 There are three SRAM timing parameters that the micro must meet in order to guarantee a valid read or write. All of these parameters are measured from where their respective signal becomes valid. t AA Memory address access time to data valid This is the amount of setup time the SRAM requires for the address lines before valid data can be output. It is measured off of the time where the address becomes valid (typically t=t AD ).

22 t OE Memory output enable valid to data valid This is the amount of setup time the SRAM requires for the OE before valid data can be output. It is measured off of the time where OE becomes valid (t=t/2 + t PLD ). t CE Memory chip enable valid to data valid This is the amount of setup time the SRAM requires for the CE before valid data can be output. It is measured off of the time where CE becomes valid (t=t AD + t PLD ).

23 CLK = t=t AD +t AA Micro DATA 8 or 16 (Prev. Data) SRAM ADDR 16 (New Addr) R/W CLK ADDR[15] PLD OE WE CE PLD Prop. Delay = t PLD

24 CLK = t=t AD +t PLD +t CE Micro DATA 8 or 16 (Prev. Data) SRAM ADDR 16 (New Addr) R/W CLK ADDR[15] PLD OE WE CE PLD Prop. Delay = t PLD

25 CLK = t=t/2+t PLD +t OE Micro DATA 8 or 16 (Prev. Data) SRAM ADDR 16 (New Addr) R/W CLK ADDR[15] PLD OE WE CE PLD Prop. Delay = t PLD

26 Let us define another parameter which will correspond to the absolute critical time referenced off t=0 (Brown Line) called t CRIT t CRIT will be the max of the absolute valid times for ADDR, OE and CE, t CRIT = max(t AD +t AA, t AD +t PLD +t CE, T/2+t PLD +t OE ) Please note: this equation only holds for the general, non-time-multiplexed case.

27 CLK = t=t CRIT Micro DATA 8 or 16 (New Data) SRAM ADDR 16 (New Addr) R/W CLK ADDR[15] PLD OE WE CE PLD Prop. Delay = t PLD

28 The last requirement for successful operation is for the DATA line to satisfy the micro s read data setup time (t RS ). This means that the DATA line must be valid t RS before the occurrence of the read (t=t or the rising edge of CLK). If this setup time is violated, the micro cannot guarantee that it read the correct data.

29 Micro DATA 8 or 16 CLK = Read Occurs (New Data) t=t SRAM ADDR 16 (New Addr) ADDR[15] PLD OE R/W CLK WE CE PLD Prop. Delay = t PLD

30 The read timing margin is the amount of time that the DATA bus is valid before the read setup time requires it to be valid. Read timing margin = T t RS t CRIT

31 Successive Write Cycles: Write cycles follow the same procedure with a few signal differences. R/W = 0, signifying a write cycle OE = and WE = --> 0 Since DATA is now be supplied by the micro, the DATA valid time is no longer a function of SRAM parameters. Instead, the micro parameter t DD determines the write data valid time.

32 Successive Write Cycles: The setup write setup and hold times are now described by t IS and t IH The write occurs at the rising edge of WE, which will occur at t=t+t PLD

33 Time-division multiplexing When interfacing to SRAM with the HCS12, we use time-division multiplexing. In this case, the ADDR and DATA busses are time-division multiplexed. The two logical busses share one set of physical wires. The ADDR is displayed during the first half of the cycle and the DATA is displayed during the second half.

34 Time-division multiplexing One thing to note is that the address needs to be displayed to the SRAM during the whole cycle. A consequence of this is that the address A consequence of this is that the address needs to be latched for the second half of the cycle since the DATA will be on the bus during this part of the cycle.

35 CLK = t=0 Micro ADDR[7:0] ADDR[15:8]/ DATA R/W CLK 8 8 (Prev. Addr) (Prev. Data) PLD SRAM ADDR[7:0] DATA[7:0] 8 LA[7:0] (Prev.LA) ADDR[15:8] OE WE CE

36 CLK = t=t AH Micro ADDR[7:0] ADDR[15:8]/ DATA R/W CLK 8 8?? PLD SRAM ADDR[7:0] DATA[7:0] 8 LA[7:0] (Prev.LA) ADDR[15:8] OE? WE CE

37 CLK = t=t AD Micro ADDR[7:0] ADDR[15:8]/ DATA R/W CLK 8 8 (Addr. LSB) (Addr. MSB) PLD SRAM ADDR[7:0] DATA[7:0] 8 LA[7:0] (Prev.LA) ADDR[15:8] OE WE? CE

38 CLK = t=t AD +t PLD Micro ADDR[7:0] ADDR[15:8]/ DATA R/W CLK 8 8 (Addr. LSB) (Addr. MSB) PLD SRAM ADDR[7:0] DATA[7:0] 8 LA[7:0] (Prev.LA) ADDR[15:8] OE WE CE PLD t PD = t CO = t PLD

39 CLK = t=t/2 Micro ADDR[7:0] ADDR[15:8]/ DATA R/W CLK 8 8 (Addr. LSB) (Addr. MSB) PLD SRAM ADDR[7:0] DATA[7:0]? 8 LA[7:0] ADDR[15:8]? OE WE CE PLD t PD = t CO = t PLD

40 The diagram depicts the shared address/data bus from the micro s perspective You should notice that ADDR is held for t MAH after the rising edge of ECLK.

41 CLK = t=t/2+t PLD Micro ADDR[7:0] ADDR[15:8]/ DATA R/W CLK 8 8 (Addr. LSB) (Addr. MSB) PLD SRAM ADDR[7:0] DATA[7:0] 8 LA[7:0] (Prev.LA) ADDR[15:8] OE WE CE PLD t PD = t CO = t PLD

42 After t=t/2 + t MAH, you see that the micro switches the ADDR/DATA from an output to an input which allows the SRAM to drive the read data on to the bus. t = 0 t = T/2 + t MAH

43 CLK = t=t/2+t MAH Micro ADDR[7:0] ADDR[15:8]/ DATA R/W CLK 8 8 (Addr. LSB)? PLD SRAM ADDR[7:0] DATA[7:0] 8 LA[7:0] (Prev.LA) ADDR[15:8] OE WE CE PLD t PD = t CO = t PLD

44 From here, now we can use our traditional analysis for margin using t AA, t CE and t OE to determine t CRIT (Brown Line) making sure to measure these parameters from when their respective signals become valid.

45 CLK = t=t/2 + t CRIT Micro ADDR[7:0] ADDR[15:8]/ DATA R/W CLK 8 8 (Addr. LSB) (New Data) PLD SRAM ADDR[7:0] DATA[7:0] 8 LA[7:0] (Prev.LA) ADDR[15:8] OE WE CE PLD t PD = t CO = t PLD

46 Finally, we have to check that t RS is satisfied and can derive our read timing margin as before. If margin is negative, the data that is read by the micro is not guaranteed to be correct.

47 Micro ADDR[7:0] ADDR[15:8]/ DATA R/W CLK 8 8 CLK = Read Occurs (Addr. LSB) (New Data) PLD t=t SRAM ADDR[7:0] DATA[7:0] 8 LA[7:0] (Prev.LA) ADDR[15:8] OE WE CE PLD t PD = t CO = t PLD

BUS TIMING ANALYSIS. George E Hadley, Timothy Rogers, and David G Meyer 2018, Images Property of their Respective Owners

BUS TIMING ANALYSIS. George E Hadley, Timothy Rogers, and David G Meyer 2018, Images Property of their Respective Owners BUS TIMING ANALYSIS George E Hadley, Timothy Rogers, and David G Meyer 2018, Images Property of their Respective Owners LEARNING OBJECTIVES identify CPU and memory timing parameters draw a bus timing diagram