CPLD/FPGA Development System
|
|
- Blake Ramsey
- 6 years ago
- Views:
Transcription
1 Chapter 1 CPLD/FPGA Development System As shown in Figure 1-1, CPLD (Complex Programmable Logic Device) and FPGA (Field-Programmable Gate Array) are the programmable logic devices (PLDs) whose internal circuitry can be programmed by users through appropriate software. Under some limitations, CPLD and FPGA devices can be designed as any digital circuits either combinational or sequential circuits. Figure 1-1 Classification of logic devices About the CIC-310 The CIC-310 CPLD/FPGA Development System shown in Figure 1-2 is self-contained equipment. It consists of two primary boards: 1-1
2 1. Development Board EPF8282ALC84 Development Board SN-PLDE2 or EPF10K10LC84 Development Board SN-PLDE3 2. Experiment Board: SN-PLDE3A Figure 1-2 CPLD/FPGA development system We will discuss the Development Board SN-PLDE2 and Experiment Board SN-PLDE3A below. The SN-PLDE3 Development Board will be described in Chapter 9. Development Board SN-PLDE2 The SN-PLDE2 Development Board shown in Figure 1-3 contains an Altera SRAM-based FPGA type EPF8282ALC84-4 (5,000 gate count), AT89C2051 microcontroller, configuration device 24LC64, 89C52 expansion socket, and an RS-232 interface circuit. The AT89C2051 microcontroller is used to load the configuration data to FPGA or SEEPROM devices via RS-232 serial port. Through three 40-pin connectors J1, J2, and J3, the Development Board can easily be connected to a variety of experimental circuits such as the Experiment Board SN-PLDE3A, project board or the user s circuits on breadboard. 1-2
3 The RESET button S1 is used to reset the development system. The EXE MODE connector J6 is used to execute a configuration file when a jumper cap is in the position. The next configuration file (displayed on SEEPROM in DNLD window) will be loaded and executed by removing and inserting the jumper cap every time. Connector J5 provides a +5V dc power supply for external circuits. The RS232 connector P1 links the Development Board to personal computer using the supplied RS232 cable. Figure 1-3 SN-PLDE2 development board 1-3
4 The architecture of Altera s Flexible Logic Element MatriX (FLEX) devices support five different configuration schemes for loading a design into a single FLEX 8000 device on the circuit board. Refer to Chapter 8 for detailed information. The FLEX 8000 architecture uses SRAM cells to store the configuration data for the device. These SRAM cells must be loaded every time the circuit powers up and begins operation. The process of physically loading the SRAM programming data into the FLEX 8000 device is called configuration. After configuration, the FLEX 8000 device resets its registers, enables its I/O pins, and begins operating as a logic device. The reset operation is called initialization. Together, the configuration and initialization processes are called command mode; normal incircuit device operation is called user mode. When active configuration is selected, the configuration data of FPGA stored in external serial ROM (SROM) or parallel ROM is read and then written to internal SRAM. The CPLD/FPGA Development System reserves the U4 socket for installing Microchip s SROM type 37LV65 (8 KB). The SROM occupies five FPGA pins: DATA0, nconfig, DCLK, CONF_DONE, and nstatus. To define the active configuration mode, a jumper cap must be placed in the lowest position of J8. If passive configuration is selected, the configuration data of FPGA is transmitted from a host (personal computer) to FPGA s configuration RAM via the RS-232 serial communication port. Your CPLD/FPGA Development System CIC-310 is designed to operate in this mode. Therefore two jumper caps are in the upper two positions of J8. Additionally, the configuration data on PC is written into SEEPROM (24LC64, U5) for storing configuration files, and reloading an autoexecutable configuration file to FPGA when the system reboots. The system is equipped with a 24LC64 (8 KB) chip for this purpose 1-4
5 and can be expanded to 32 KB memory space (4 chips of 24LC64, U5-U8). This configuration mode is defined by the pins NSP, MSEL0, and MSEL1. An AT89C52 microcontroller can be installed in the 89C52 socket to associate with the FPGA device for high-performance designs. Figure 1-4 shows the pin assignments of 89C52. Figure 1-4 Pin assignments of 89C52 socket Through 40-pin connectors J1, J2, J3, the FPGA I/O pins are connected to the various I/O devices on the SN-PLDE3A Experiment Board. The pin assignments of J1-J3 are shown in Figure 1-5. The JP18 on the Experiment Board is used to select the clock signal to FPGA I54 pin from either MTX2 ( MHz) or P84 (pulser generator SWP4). 1-5
6 Figure 1-5 J1-J3 connectors Experiment Board SN-PLDE3A The SN-PLDE3A Experiment Board, shown in Figure 1-6, provides several different input and output devices, which are widely used in modern electronic products. These devices include: LEDs, 7- segment and 16-segment displays for display, logic input switches for data input, clock and pulse generators for signal generation. The FPGA pins are marked on the Experiment Board panel. 1-6
7 Figure 1-6 SN-PLDE3A experiment board 1-7
8 The Experiment Board is divided into the following sections: 1. Logic Switch Input Section In this section three 8-bit slide switches (S1, S2, and S3) are defined as logic inputs. The pin-out is described in Table 1-1. The circuit diagram of logic input switch is shown in Figure 1-8. Each slide switch is pulled up to V CC level (logic 1) by a 2.2-KΩ resistor when the slide button is placed in the ON position; otherwise it is pulled down to GND level (logic 0) by a 10-KΩ resistor. Figure 1-7 Logic switches S1-S3 Figure 1-8 Logic input switch circuit 1-8
9 Table 1-1 Logic input switch pin-out S1 FPGA S2 FPGA S3 FPGA S1-1 P01 S2-1 P34 S3-1 P43 S1-2 P02 S2-2 P35 S3-2 P44 S1-3 P03 S2-3 P36 S3-3 P45 S1-4 P04 S2-4 P37 S3-4 P46 S1-5 P06 S2-5 P39 S3-5 P48 S1-6 P07 S2-6 P40 S3-6 P49 S1-7 P08 S2-7 P41 S3-7 P50 S1-8 P09 S2-8 P42 S3-8 P51 The logic state of each switch is indicated by the corresponding logic LED display D1 through D Logic LED Display Section There are two sets of 16-LED display as shown in Figure 1-9. The LEDs (D1 through D16) located at the lower right side of the Experiment Board are usually used to indicate the logic state of the logic input switches. However, D1-D16 can be used as output indicators if necessary. In such a case, all of the logic input switch must be in ON position. The other set of 16-LED display is located at the upper right side of the Experiment Board. The LEDs (D17 through D32) are dedicated to indicate the logic state of outputs. These 32 LEDs are buffered by CD40106 ICs as shown in the circuit of Figure 1-10 and the pinout in Table
10 Figure 1-9 Logic LED display Figure 1-10 Logic LED display circuit 1-10
11 Table 1-2 Logic LED display pin-out LED FPGA LED FPGA LED FPGA LED FPGA D1 P01 D9 P34 D17 P55 D25 P64 D2 P02 D10 P35 D18 P56 D26 P65 D3 P03 D11 P36 D19 P57 D27 P66 D4 P04 D12 P37 D20 P58 D28 P67 D5 P06 D13 P39 D21 P60 D29 P69 D6 P07 D14 P40 D22 P61 D30 P70 D7 P08 D15 P41 D23 P62 D31 P71 D8 P09 D16 P42 D24 P63 D32 P DIG Parallel-Serial 7-Segment Display Section The 6-digit parallel-serial 7-segment display, located at the upper side of the Experiment Board, consists of six common-cathode 7- segment displays. The segment names and pin assignments are shown in Figure The pin-out of the 6-digit 7-segment display is described in Table 1-3. Figure 1-11 Pin assignments of 7-segment display 1-11
12 Table digit 7-segment display pin-out DP1 FPGA DP2 FPGA DP3 FPGA SA1 P13 SA2 P22 SA3 P55 SB1 P14 SB2 P23 SB3 P56 SC1 P15 SC2 P24 SC3 P57 SD1 P16 SD2 P25 SD3 P58 SE1 P18 SE2 P27 SE3 P60 SF1 P19 SF2 P28 SF3 P61 SG1 P20 SG2 P29 SG3 P62 SP1 P21 SP2 P30 SP3 P63 SC1* P76 SC2* P77 SC3* P78 DP4 FPGA DP5 FPGA DP6 FPGA SA4 P64 SA5 P34 SA6 P43 SB4 P65 SB5 P35 SB6 P44 SC4 P66 SC5 P36 SC6 P45 SD4 P67 SD5 P37 SD6 P46 SE4 P69 SE5 P39 SE6 P48 SF4 P70 SF5 P40 SF6 P49 SG4 P71 SG5 P41 SG6 P50 SP4 P72 SP5 P42 SP6 P51 SC4* P79 SC5* P08 SC6* P09 Note: *=Common-cathode terminal The common-cathode terminal SC of each digit can be connected to FPGA pin or ground with a jumper cap. When connected to GND, the digit operates in parallel mode (individual mode). If connected to FPGA pin, the digit operates in serial mode (scan mode). In parallel mode, the 8 LED segments (SA-SP) of each digit must be connected to FPGA pins on the left side of each selector (JP8, JP9, JP10, JP11, JP12, JP13) with 8-jumper caps as shown in Figure 1-12(a). 1-12
13 To operate in serial mode, the common-cathode terminals SC1 through SC6 must be connected to the FPGA pins P76-P79, P08, and P09, respectively, with jumper caps. The same segments of all digits must be connected in parallel by placing the 8-jumper caps in JP8A through JP13A positions as well as JP8. Figure 1-12(b) shows the positions of jumper caps for serial operation. In such a case, the segments SA through SP are connected to the FPGA pins P13 through P21, and the common-cathode terminals SC1 through SC6 are connected to the FPGA pins P76-P79, P08, and P09, respectively. (a) Parallel mode 1-13
14 (b) Serial mode Figure 1-12 Operating modes of 6-digit 7-segment display 4. Pulser Generator Section This section located at the lower side of the board consists of four debounced push-button switches (SWP1, SWP2, SWP3, and SWP4), which are defined as pulse outputs. Each push-button signal is defined as a logic 1 when pressed; when unpressed it becomes a logic 0. Each of the switches SWP1-SWP4 is a spring-loaded push button switch. When it is pressed and released, the output produces a low-high-low pulse, which is suitable for the clock input of counters or registers. The circuit of pulser generator is shown in Figure 1-13 and the pin-out in Table
15 Figure 1-13 Pulser generator Table 1-4 Pulser generator pin-out Pulser generator FPGA pin SWP1 P81 SWP2 P82 SWP3 P83 SWP4 P84 5. Clock Generator Section The clock generators RCOSC1 and RCOSC2 are RC oscillators constructed from CD40106 and the associated resistors and capacitors. The RCOSC1 generator can operate in low-frequency range (JP15 LF pins closed) or high-frequency range (JP15 LF pins open). The output frequency is controlled by the HFQ ADJ knob ranging from 5 to 500 KHz. Similarly, the RCOSC2 generator can operate in low-frequency range (JP17 LF pins closed) or highfrequency range (JP17 LF pins open). Its output frequency is adjusted by the LFQ ADJ knob ranging from 0.1 Hz to 20 KHz. RCOSC1 output is connected to FPGA pin 31 (I31) by placing a jumper cap in the I31 position of JP15 and RCOSC2 output is connected to FPGA pin 73 (I73) by placing a jumper cap in the I73 position of JP
16 The circuits of clock generators and 20-MHz crystal oscillator are shown in Figure The output of the crystal oscillator is connected to FPGA pin 12 (I12) for clocking the device. A 20-MHz crystal oscillator is installed in factory, and it can be replaced by another oscillator if a different frequency is needed for different circuit designs. Figure 1-14 Clock generators 6. SW and Keyboard Section The 4x4 matrix keyboard can be used in individual and scan modes. 1-16
17 (a) Individual buttons (b) Circuit Figure 1-15 Matrix keyboard in individual mode 1-17
18 (a) Scanned keyboard Figure 1-16 (b) Circuit Matrix keyboard in scan mode 1-18
19 When the matrix keyboard is used in individual mode (8-jumper caps placed in PKI1, PKI2, and PKI3) as shown in Figure 1-15(a), these 16 buttons act as individual buttons and the circuit is shown in Figure 1-15(b). If the keyboard is used in scan mode (8-jumper caps placed in SCN1, SCN2, and SCN3) as shown in Figure 1-16(a), these 16 buttons act as a 4x4 scanned keyboard and the circuit is shown in Figure 1-16(b). The keyboard pin-out is described in Table 1-5. Table 1-5 Matrix keyboard pin-out Individual Mode Scan Keyboard FPGA Keyboard FPGA Mode SW0 P34 SW8 P43 KIN1 SW1 P35 SW9 P44 KIN2 SW2 P36 SWA P45 KIN3 SW3 P37 SWB P46 KIN4 SW4 P39 SWC P48 SCN1 SW5 P40 SWD P49 SCN2 SW6 P41 SWE P50 SCN3 SW7 P42 SWF P51 SCN Segment Display Section The 16-segment display is common-cathode type. Its segment names and pin assignments is shown in Figure The commoncathode terminal C-SEL must be connected to GND when using the 16-segment display. 1-19
20 Figure segment display The pin assignments of the 16-segment display socket JP21 are shown in Figure The circuit is shown in Figure Figure segment display socket 1-20
21 Figure segment display circuit The 16-segment display pin-out is described in Table 1-6. When using the 16-segment display, 8-jumper caps must be placed in JP8, JP9, JP10 positions and a jumper cap must be in JP23. Table segment display pin-out 16-segment FPGA 16-segment FPGA A1 P13 (DA1) E2 P23 (DB2) A2 P14 (DB1) G1 P24 (DC2) B1 P15 (DC1) G2 P25 (DD2) B2 P16 (DD1) H1 P27 (DE2) C1 P18 (DE1) H2 P28 (DF2) C2 P19 (DF1) I1 P29 (DG2) D1 P20 (DG1) I2 P30 (DP2) D2 P21 (DP1) DP P63 (DP3) E1 P22 (DA2) C-SEL JP23 (GND) 1-21
22 7. 5 x 7 DOT LED Section The pin assignments of the 5x7 dot LED are shown in Figure The socket for the dot LED (JP22) and the dot selector connector (JP24) are shown in Figure Figure 1-22 shows the circuits of JP22 and JP24. Figure 1-20 Pin assignments of 5x7 dot LED Figure x7 dot LED socket JP22 and dot selector JP
23 Figure 1-22 JP22 and JP24 signals Table 1-7 indicates the pin-out of the 5x7 dot LED. When using the 5x7 dot LED, the 8-jumper caps must be installed in JP8 and JP24. Table 1-7 5x7 dot LED pin-out Dot LED FPGA Dot LED FPGA PA1 P13 C1 P22 PA2 P14 C2 P23 PA3 P15 C3 P24 PA4 P16 C4 P25 PA5 P18 C5 P27 PA6 P19 PA7 P20 8. LCD 2021 Section The JP20 connector shown in Figure 1-23 is for connecting an external LCD module LCD2021 to the FPGA device. The potentiometer VR1 is used to adjust the contrast of LCD screen and is not installed in factory. If you want to use the function, remove the jumper in VR1 block and install a 10-KΩ potentiometer as shown in Figure 1-23(b). The pin-out is described in Table
24 (a) LCD2021 connector (b) JP20 circuit Figure 1-23 LCD2021 module Table 1-8 LCD2021 pin-out LCD FPGA LCD FPGA DB0 P13 E P22 DB1 P14 R/W P23 DB2 P15 D/I P24 DB3 P16 LCT DB4 P18 DB5 P19 DB6 P20 DB7 P
25 System Setup Follow the procedure to install the software and hardware of the CIC- 310 CPLD/FPGA Development System. The system software includes MAX+plus II manager and download manager DNLD programs. Installing Software 1. Put the supplied CPLD/FPGA Development CD-ROM into CD player. The install program auto runs and the MAX+pus II Install window is shown in Figure Figure 1-24 MAX+pus II Install window 2. Choose the Full/Custom/FLEXIm Server to open the Welcome window shown in Figure
26 Figure 1-25 Welcome window 3. Click on the Next button to open the MAX+plus II License Agreement window as shown in Figure Figure 1-26 MAX+plus II License Agreement window 1-26
27 4. Read the license agreement throughout and then click on Yes button. The Information window is shown in Figure Figure 1-27 license agreement information 5. Click Next to open the User Information window as shown in Figure Figure 1-28 User information window 1-27
28 6. Type your name and company in the Name and Company fields, respectively. Then click on Next to open the Setup Type window shown in Figure Figure 1-29 Setup type selection 7. Select Full Installation item and click Next button to open the first Choose Destination Location window shown in Figure Figure 1-30 First Choose Destination Location window 1-28
29 8. Click Next to open the second Choose Destination Location window as shown in Figure Figure 1-31 second Choose Destination Location window 9. Click Next to open the third Choose Destination Location window as shown in Figure Figure 1-32 Choosing destination 1-29
30 10. Click Next to open the Select Program Folder window as shown in Figure Figure 1-33 Select Program Folder window 11. Click Next to open the Start Coping Files window as shown in Figure Figure 1-34 Start Coping Files window 1-30
31 12. Click Next to start installing the software. Once completed, a Question dialog box is shown in Figure Figure 1-35 Question dialog box 13. Click on Yes button. A readme window will display as shown in Figure Figure 1-36 Readme window 1-31
32 14. Close the windows. Execute C:\Programs\Altera\MAX+plus II v10.1 program to open the MAX+plus II Manager window as shown in Figure Figure 1-37 MAX+plus II Manager window 15. Use the Options-License Setup command on the toolbar to open the License Setup window as shown in Figure Figure 1-38 License Setup window 1-32
33 16. Click on the System Info button to view your system information as shown in Figure Figure 1-39 System information 17. Write down your C: drive serial number displayed and click OK. Close the License Setup window. Visit Altera web site and select MAX+plus II Software for Students and Universities item to request free software license. 18. Altera will a license.dat file to you. Save this file into C:\maxplus2 folder. Open the License Setup window again. Click on Browse and select C:\maxplus2\license.dat as shown in Figure Then click on OK button. Close the License Setup window 1-33
34 Figure 1-40 License setup 19. Copy E:\DNLD3.exe (or DNLD82.exe for WIN2000/NT/XP) file to maxplus2 folder (from My Computer or File Manager). Create DNLD3 shortcut on desktop. 20. The software installation is now completed. 21. Copy E:\EXP folder (this folder includes 3 example folders) files to max2work folder (from My Computer or File Manager). 1-34
35 Installing Hardware To load the completed designs to FPGA device for emulation, you must link the computer to the CPLD/FPGA Development System CIC- 310 using RS-232 cable. 1. With all powers off, connect the RS-232 port (COM1 or COM2) on personal computer to the RS-232 connector (P1) on FPGA board SN-PLDE2 using the supplied 9-pin cable. 2. Make sure that the voltage select switch 115V/230V on the bottom panel of CIC-310 is in a correct position. Connect the AC socket on CIC-310 rear panel to the wall outlet via the supplied AC cord. 3. Turn on the power. The power indicator should light up. If not, turn off the power and check the fuse on the rear panel. 4. Proceed to the next Chapter for basic operation of software and hardware. 1-35
36 1-36
Bolt 18F2550 System Hardware Manual
1 Bolt 18F2550 System Hardware Manual Index : 1. Overview 2. Technical specifications 3. Definition of pins in 18F2550 4. Block diagram 5. FLASH memory Bootloader programmer 6. Digital ports 6.1 Leds and
More informationFPGA Discovery-III XC3S200 Board Manual
FPGA Discovery-III XC3S200 Board Manual 77/9 SOI LADPRAO 1, LADPRAO ROAD, JOMPOL, JATUJAK DISTRICT, BANGKOK THAILAND 10900 TEL. 66(0)2939-2084 FAX.66(0)2939-2084 http://www.ailogictechnology.com 1 FPGA
More informationNios Embedded Processor Development Board
Nios Embedded Processor Development Board July 2003, ver. 2.2 Data Sheet Introduction Development Board Features Functional Overview This data sheet describes the features and functionality of the Nios
More informationCopyright 2011 R.S.R. Electronics, Inc. All rights reserved. 04/11. Ver. 1.0web
For XILINX WebPack Copyright 2011 R.S.R. Electronics, Inc. All rights reserved. 04/11 Ver. 1.0web 1 Table of Contents 1.0 INTRODUCTION...3 2.0 GENERAL DESCRIPTION...5 3.0 BRIEF DESCRIPTION Of PLDT-3 BOARD...6
More informationCEIBO FE-5111 Development System
CEIBO FE-5111 Development System Development System for Atmel W&M T89C5111 Microcontrollers FEATURES Emulates Atmel W&M T89C5111 4K Code Memory Real-Time Emulation and Trace Frequency up to 33MHz/5V ISP
More informationPVK40. User's manual. Feature Rich Development and Educational Kit for 40-pin Microchip PIC microcontrollers
PVK40 User's manual Feature Rich Development and Educational Kit for 40-pin Microchip PIC microcontrollers CONTENTS PVK40 3 On-board peripherals: 3 Power supply 4 Microcontroller 4 Reset circuitry 4 Oscilator
More informationSection 3. System Integration
Section 3. System Integration This section includes the following chapters: Chapter 9, Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family Chapter 10, Hot-Socketing
More informationAVR Intermediate Development Board. Product Manual. Contents. 1) Overview 2) Features 3) Using the board 4) Troubleshooting and getting help
AVR Intermediate Development Board Product Manual Contents 1) Overview 2) Features 3) Using the board 4) Troubleshooting and getting help 1. Overview 2. Features The board is built on a high quality FR-4(1.6
More informationFEATURES Supports following ST upsd3200 family of microcontrollers ( both package of QFP52 and QFP80)
ME-3200 Emulator INTRUDUCTION ME-3200 is a real-time in-circuit emulator dedicated to ST upsd3200 family of microcontrollers. It has the architecture of HOST and POD and is linked to PC via the parallel
More informationCONTENTS BIGAVR2 KEY FEATURES 4 CONNECTING THE SYSTEM 5 INTRODUCTION 6
CONTENTS BIGAVR2 KEY FEATURES 4 CONNECTING THE SYSTEM 5 INTRODUCTION 6 Switches 7 Jumpers 8 MCU Sockets 9 Power Supply 11 On-board USB 2.0 Programmer 12 Oscillator 14 LEDs 15 Reset Circuit 17 Push-buttons
More informationFPGA Interfacing of HD44780 Based LCD Using Delayed Finite State Machine (FSM)
FPGA Interfacing of HD44780 Based LCD Using Delayed Finite State Machine (FSM) Edwin NC Mui Custom R & D Engineer Texco Enterprise Ptd. Ltd. {blackgrail2000@hotmail.com} Abstract This paper presents a
More informationDESCRIPTION FEATURES. PT6321 Fluorescent Display Tube Controller Driver
ANGUS ELECTRONICS CO., LTD Tel: (852) 2345 0540 Fax: (852) 2345 9948 Web Site: www.angus.com.hk PT6321 Fluorescent Display Tube Controller Driver DESCRIPTION The PT6321 is a dot matrix fluorescent display
More informationDEV-1 HamStack Development Board
Sierra Radio Systems DEV-1 HamStack Development Board Reference Manual Version 1.0 Contents Introduction Hardware Compiler overview Program structure Code examples Sample projects For more information,
More informationMega128-DEVelopment Board Progressive Resources LLC 4105 Vincennes Road Indianapolis, IN (317) (317) FAX
Mega128-DEVelopment Board Progressive Resources LLC 4105 Vincennes Road Indianapolis, IN 46268 (317) 471-1577 (317) 471-1580 FAX http://www.prllc.com GENERAL The Mega128-Development board is designed for
More informationKeywords Digital IC tester, Microcontroller AT89S52
Volume 6, Issue 1, January 2016 ISSN: 2277 128X International Journal of Advanced Research in Computer Science and Software Engineering Research Paper Available online at: www.ijarcsse.com Digital Integrated
More informationLABORATORY MANUAL Interfacing LCD 16x2, Keypad 4x4 and 7Segment Display to PIC18F4580
LABORATORY MANUAL Interfacing LCD 16x2, Keypad 4x4 and 7Segment Display to PIC18F458 1. OBJECTIVES: 1.1 To learn how to interface LCD 16x2, Keypad 4x4 and 7Segment Display to the microcontroller. 1.2 To
More informationEmbedded World Television, Radio, CD player, Washing Machine Microwave Oven Card readers, Palm devices
A presentation on INTRODUCTION We are living in the Embedded World. We are surrounded with many embedded products and our daily life largely depends on the proper functioning of these gadgets. Television,
More information8051 Intermidiate Development Board. Product Manual. Contents. 1) Overview 2) Features 3) Using the board 4) Troubleshooting and getting help
8051 Intermidiate Development Board Product Manual Contents 1) Overview 2) Features 3) Using the board 4) Troubleshooting and getting help 1. Overview 2. Features The board is built on a high quality FR-4(1.6
More informationUSB-16COMi-M 16-Port RS-422/485 USB Serial Adapter User Manual. Features and Specifications. Power Supply
USB-16COMi-M 16-Port RS-422/485 USB Serial Adapter User Manual The USB to industrial 16-Port RS-422/485 Adapter is designed to make serial port expansion quick and simple. Connecting to a USB port on your
More informationINTERFACING 16 2 LCD WITH 8051
INTERFACING 16 2 LCD WITH 8051 LCD display is an inevitable part in almost all embedded projects and this article is about interfacing 16 2 LCD with 8051 microcontroller. Many guys find it hard to interface
More informationOSC Ring Type Ring or Resonator type (optional) RESET Pin No Yes
General Description Features est Series is a series of 3 to 340 seconds single chip high quality voice synthesizer IC which contains one 4-bit Input port (provided for est005 and above); three 4-bit I/O
More informationConfiguring FLEX 8000
Configuring FLEX 8000 Devices June 2000, ver. 3.03 Application Note 33 Introduction The architecture of Altera s Flexible Logic Element MatriX (FLEX) devices supports several different configuration schemes
More informationFPGA Development Board Hardware and I/O Features
CHAPTER 2 FPGA Development Board Hardware and I/O Features Photo: The Altera DE1 board contains a Cyclone II FPGA, external SRAM, SDRAM & Flash memory, and a wide assortment of I/O devices and connectors.
More informationEasyPIC5 Development System
EasyPIC5 Development System Part No.: MPMICRO-PIC-Devel- EasyPIC5 Overview EasyPIC5 is a development system that supports over 120 8-, 14-, 18-, 20-, 28- and 40-pin PIC MCUs. EasyPIC5 allows PIC microcontrollers
More information4. Hot Socketing & Power-On Reset
4. Hot Socketing & Power-On Reset CII51004-3.1 Introduction Cyclone II devices offer hot socketing (also known as hot plug-in, hot insertion, or hot swap) and power sequencing support without the use of
More informationFigure 2.1 The Altera UP 3 board.
Figure 2.1 The Altera UP 3 board. USB Port PS-2 Port USB PHY Chip Heat Sink Parallel Port B B VGA Port I2C PROM Chip... JP19 Headers for I2C Bus Signals J3 Mounting Hole Santa Cruz Expansion Long Connector
More informationGENERAL DESCRIPTION FEATURES NOTICE. FEBL Semiconductor MSM9831 EVA Board. Pre-Production ROM Evaluation Board
Pre-Production ROM Evaluation Board This version: Feb. 2000 Previous version: Aug. 1999 GENERAL DESCRIPTION The is a pre-production EPROM evaluation board that enables a user to evaluate user s sound data
More informationEasyAVR6 Development System
EasyAVR6 Development System Part No.: MPMICRO-AVR-Devel-EasyAVR6 Overview EasyAVR6 is a development system that supports a wide range of 8-, 14-, 20-, 28- and 40-pin AVR MCUs. EasyAVR6 allows AVR microcontrollers
More informationFPGA Configuration EEPROM Memory AT17C020A AT17LV020A
Features Serial EEPROM Family for Configuring Altera FLEX Devices Simple Interface to SRAM FPGAs EE Programmable 2M-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate
More informationExclusive 2.5 GHz Frequency Counter
Exclusive 2.5 GHz Frequency Counter with blue 2 x 16 LCD display This manual will guide you how to assemble, test and tune this frequency counter KIT. Features: Frequency range from 5 MHz to 2.5GHz Factory
More informationLocktronics PICmicro getting started guide
Page 2 getting started guide What you need to follow this course 2 Using the built-in programs 3 Create your own programs 4 Using Flowcode - your first program 5 A second program 7 A third program 8 Other
More informationDigilab 2 Reference Manual
125 SE High Street Pullman, WA 99163 (509) 334 6306 (Voice and Fax) www.digilentinc.com PRELIMINARY Digilab 2 Reference Manual Revision: November 19, 2001 Overview The Digilab 2 (D2) development board
More informationCPLD board datasheet EB
CPLD board datasheet EB020-00-3 Contents. About this document... 2 2. General information... 3 3. Board layout... 4 4. Testing this product... 5 5. Circuit description... 6 Appendix Circuit diagram Copyright
More informationIN-CIRCUIT DEBUG (ICD) USER GUIDE
April 2003 IN-CIRCUIT DEBUG (ICD) USER GUIDE The Western Design Center, Inc., 2002 WDC TABLE OF CONTENTS 1. Introduction...3 2. Debug Port...4 3. The ICD Registers...4 4. ICDCTRL Register Bit Definitions...5
More informationAltera EP4CE6 Mini Board. Hardware User's Guide
Altera Hardware User's Guide 1. Introduction Thank you for choosing the! is a compact FPGA board which is designed based on device. It's a low-cost and easy-to-use platform for learning Altera's Cyclone
More informationJUL. 27, 2001 Version 1.0
S SPLC782A 6COM/8SEG Controller/Driver JUL. 27, 2 Version. SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO. is
More informationSANKALCHAND PATEL COLLEGE OF ENGINEERING, VISNAGAR. ELECTRONICS & COMMUNICATION DEPARTMENT Question Bank- 1
SANKALCHAND PATEL COLLEGE OF ENGINEERING, VISNAGAR ELECTRONICS & COMMUNICATION DEPARTMENT Question Bank- 1 Subject: Microcontroller and Interfacing (151001) Class: B.E.Sem V (EC-I & II) Q-1 Explain RISC
More informationSection II. Software Settings
Section II. Software Settings Configuration options can be set in the Quartus II and MAX+PLUS II development software. You can also specify which configuration file formats Quartus II or MAX+PLUS II generates.
More informationAVR Peripheral Board. Campus Component Pvt. Ltd.
AVR Peripheral Board Campus Component Pvt. Ltd. DISCLAIMER Information furnished is believed to be accurate and reliable at the time of publication. However, Campus Component Pvt. Ltd. assumes no responsibility
More informationEEE3410 Microcontroller Applications Department of Electrical Engineering Lecture 4 The 8051 Architecture
Department of Electrical Engineering Lecture 4 The 8051 Architecture 1 In this Lecture Overview General physical & operational features Block diagram Pin assignments Logic symbol Hardware description Pin
More informationRevision: 5/7/ E Main Suite D Pullman, WA (509) Voice and Fax. Power jack 5-9VDC. Serial Port. Parallel Port
Digilent Digilab 2 Reference Manual www.digilentinc.com Revision: 5/7/02 215 E Main Suite D Pullman, WA 99163 (509) 334 6306 Voice and Fax Overview The Digilab 2 development board (the D2) features the
More informationPCI bit Digital Input/ Output Card for PCI Bus. User s Manual
PCI-1751 48-bit Digital Input/ Output Card for PCI Bus User s Manual Copyright This documentation and the software included with this product are copyrighted 1998 by Advantech Co., Ltd. All rights are
More informationDigilab 2E Reference Manual
Digilent 2E System Board Reference Manual www.digilentinc.com Revision: February 8, 2005 246 East Main Pullman, WA 99163 (509) 334 6306 Voice and Fax Digilab 2E Reference Manual Overview The Digilab 2E
More information9. Configuration, Design Security, and Remote System Upgrades in Arria II Devices
July 2012 AIIGX51009-4.3 9. Configuration, Design Security, and Remote System Upgrades in Arria II Devices AIIGX51009-4.3 This chapter describes the supported configuration schemes for Arria II devices,
More informationAX-12. PIC12F675 microcontroller Activity board
AX- PICF67 microcontroller Activity board Optional of AX- board DC adaptor 9-V Small stepper motor Microcontroller unit features : Microchip s 8-pin PIC microocntroller PICF67 on-board KWord Program memory
More information16COM/40SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
6COM/4SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD INTRODUCTION is a dot matrix LCD driver & controller LSI which is fabricated by low power CMOS technology It can display, 2-line with 5 x 8 or 5 x dots
More informationAPEX DSP Development Board
APEX DSP Development Board (Starter Version) April 2002, ver. 1.3 Data Sheet Features Powerful development board for digital signal processing (DSP) designs featuring the APEX EP20K200E-1X device in a
More informationmelabs Serial LCD Firmware Version 1.1 3/5/07
melabs Serial LCD Firmware Version 1.1 3/5/07 The melabs Serial LCD (SLCD) can display serial data from either asynchronous RS232-style or synchronous I 2 C input. A range of baud rates from 2400 to 57,600
More informationOperating temperature Topr 40 to +85 C Storage temperature Tstg 55 to +125 C
Ordering number : EN3356A SANYO Semiconductors DATA SHEET LC7185-8750 Overview This 27 MHz band, PLL frequency synthesizer LSI chip is designed specifically for CB transceivers. The specifications are
More information16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
INTRODUCTION KS0070B is a dot matrix LCD driver & controller LSI which is fabricated by low power CMOS technology. It is capable of displaying 1 or 2 lines with the 5 7 format or 1 line with the 5 10 dots
More information中显液晶 技术资料 中显控制器使用说明书 2009年3月15日 北京市海淀区中关村大街32号和盛大厦811室 电话 86 010 52926620 传真 86 010 52926621 企业网站.zxlcd.com
http://wwwzxlcdcom 4 SEG / 6 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD June 2 Ver Contents in this document are subject to change without notice No part of this document may be reproduced or transmitted
More informationmelabs Serial LCD Firmware Version 1.0 2/7/07
melabs Serial LCD Firmware Version 1.0 2/7/07 The melabs Serial LCD (SLCD) can display serial data from either asynchronous RS232-style or synchronous I 2 C input. A range of baud rates from 2400 to 57,600
More informationAC/DC. Adapter. Ribbon. Cable Serial. Serial. Adapter. Figure 1. Hardware Setup using an EC2 Serial Adapter
C8051F32X DEVELOPMENT KIT USER S GUIDE 1. Kit Contents The C8051F32x Development Kit contains the following items: C8051F320 Target Board C8051Fxxx Development Kit Quick-Start Guide C8051F32x Development
More informationUSB-COMi-TB USB to Industrial Single RS-422 / 485 Adapter Manual. Specifications and Features
USB-COMi-TB USB to Industrial Single RS-422 / 485 Adapter Manual The USB-COMi-TB USB-to-Industrial Single RS-422/485 Adapter is designed to make industrial communication port expansion quick and simple.
More informationSierra Radio Systems. HamStack. Project Board Reference Manual V1.0
Sierra Radio Systems HamStack Project Board Reference Manual V1.0 Welcome HamStack Project Board Reference Manual Revision 1.0.3 2011 George Zafiropoulos, KJ6VU and John Best, KJ6K This guide provides
More informationGoal: We want to build an autonomous vehicle (robot)
Goal: We want to build an autonomous vehicle (robot) This means it will have to think for itself, its going to need a brain Our robot s brain will be a tiny computer called a microcontroller Specifically
More informationDEV16T. LCD Daughter board
LCD Daughter board Table of Contents 1 Introduction...2 2 Features...3 3 Expansion Connectors...4 3.1 Daughter Board Connectors...4 4 LCD Display...5 5 Input Buttons S1 to S4...5 6 Buzzer...5 7 Connector
More informationDigilab 2 XL Reference Manual
125 SE High Street Pullman, WA 99163 (509) 334 6306 (Voice and Fax) www.digilentinc.com PRELIMINARY Digilab 2 XL Reference Manual Revision: May 7, 2002 Overview The Digilab 2 XL (D2XL) development board
More informationARM programmer and daughter board
ARM programmer and daughter board www.matrixtsl.com EB185 Contents About this document 3 Board layout 3 General information 4 Circuit description 4 Protective cover 5 Circuit diagram 6 2 Copyright About
More informationTranscendent Frequency Counter
Transcendent Frequency Counter with blue 2 x 16 LCD display This manual will guide you how to assemble, test and operate this frequency counter KIT. Features: The transcendent counter has two input channels
More information3.3V regulator. JA H-bridge. Doc: page 1 of 7
Digilent Cerebot Board Reference Manual Revision: 11/17/2005 www.digilentinc.com 215 E Main Suite D Pullman, WA 99163 (509) 334 6306 Voice and Fax Overview The Digilent Cerebot Board is a useful tool for
More informationSH69P55A EVB. Application Note for SH69P55A EVB SH69P55A EVB SH69V55A
Application Note for SH69P55A EVB SH69P55A EVB The SH69P55A EVB is used to evaluate the SH69P55A chip's function for the development of application program. It contains of a SH69V55A chip to evaluate the
More informationSTK200 Starter Kit User Guide May 2004
STK200 Starter Kit User Guide ---------------------------------------------------------------- May 2004 R Table of Contents Section 1 Introduction... 1-1 1.1 Device Support...1-1 Section 2 Getting Started...
More informationNTE1731 Integrated Circuit CMOS 10 Number Pulse Dialer
NTE1731 Integrated Circuit CMOS 10 Number Pulse Dialer Description: The NTE1731 is a CMOS LSI repertory dialer with ten 16 digit number memory storage in a 16 Lead DIP type package. The pulse and mute
More informationThursday, September 15, electronic components
electronic components a desktop computer relatively complex inside: screen (CRT) disk drive backup battery power supply connectors for: keyboard printer n more! Thursday, September 15, 2011 integrated
More informationF²MC-8FX FAMILY MB95100 SERIES EMULATOR HW SETUP 8-BIT MICROCONTROLLER APPLICATION NOTE. Fujitsu Microelectronics Europe Application Note
Fujitsu Microelectronics Europe Application Note MCU-AN-395002-E-V10 F²MC-8FX FAMILY 8-BIT MICROCONTROLLER MB95100 SERIES EMULATOR HW SETUP APPLICATION NOTE Revision History Revision History Date 2004-10-12
More informationCEIBO FE-51RD2 Development System
CEIBO FE-51RD2 Development System Development System for Atmel AT89C51RD2 Microcontrollers FEATURES Emulates Atmel AT89C51RD2 60K Code Memory Real-Time Emulation Frequency up to 40MHz / 3V, 5V ISP and
More information16COM / 40SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
INTRODUCTION KS0066U is a dot matrix LCD driver & controller LSI whichis fabricated by low power CMOS technology It can display 1or 2 lines with the 5 8 dots format or 1 line with the 5 11 dots format
More informationConfiguration Devices
Configuration Devices for APEX & FLEX Devices November 1999, ver. 10.03 Data Sheet Features Serial device family for configuring FLEX and APEX TM devices Easy-to-use 4-pin interface to FLEX and APEX devices
More informationAC/DC. Adapter. Serial. Adapter. Figure 1. Hardware Setup
C8051F35X DEVELOPMENT KIT USER S GUIDE 1. Kit Contents The C8051F35x Development Kit contains the following items: C8051F350 Target Board Serial Adapter (RS232 to Target Board Debug Interface Protocol
More informationManual of Board ET-PIC STAMP 18F8722-K22 ET-PIC STAMP 18F8722-K22
ET-PIC STAMP 18F8722-K22 ET-PIC STAMP 18F8722-K22 is Board Microcontroller in a series of PIC18F87K22 80-Pin TQFP from Microchip. It designs I/O of MCU on board to interface with CONNECTOR in the format
More informationRevision: February 19, E Main Suite D Pullman, WA (509) Voice and Fax. Switching Power Supplies 3V3 1V2 2V5 1V8
Nexys Board Reference Manual Revision: February 19, 2007 215 E Main Suite D Pullman, WA 99163 (509) 334 6306 Voice and Fax Overview s Nexys circuit board is an integrated circuit development platform based
More informationRTE-V850E/GP1-IE USER'S MANUAL (REV.1.01) RealTimeEvaluator
RTE-V850E/GP1-IE USER'S MANUAL (REV.1.01) RealTimeEvaluator REVISION HISTORY Rev. 1.00 June 20, 2002 Rev. 1.01 November 15, 2002 First edition Revising following chapters * "Measured value of execution
More informationConfiguring SRAM-Based LUT Devices
Configuring SRAM-Based LUT Devices February 2002, ver. 3.0 Application Note 116 Introduction APEX TM II, APEX 20K, Mercury TM, ACEX TM 1K, FLEX 10K, and FLEX 6000 devices can be configured using one of
More informationDisplay Real Time Clock (RTC) On LCD. Version 1.2. Aug Cytron Technologies Sdn. Bhd.
Display Real Time Clock (RTC) On LCD PR12 Version 1.2 Aug 2008 Cytron Technologies Sdn. Bhd. Information contained in this publication regarding device applications and the like is intended through suggestion
More informationDrexel University Electrical and Computer Engineering Department ECE 200 Intelligent Systems Spring Lab 1. Pencilbox Logic Designer
Lab 1. Pencilbox Logic Designer Introduction: In this lab, you will get acquainted with the Pencilbox Logic Designer. You will also use some of the basic hardware with which digital computers are constructed
More informationConfiguring Cyclone FPGAs
Configuring Cyclone FPGAs March 2003, ver. 1.1 Application Note 250 Introduction You can configure Cyclone TM FPGAs using one of several configuration schemes, including the new active serial (AS) configuration
More informationARM programmer and daughter board EB Technical datasheet
ARM programmer and daughter board EB185-00-1 Technical datasheet Contents 1 About this document...2 2 General information...3 3 Description...3 4 Board layout...4 5 Testing this product...5 6 Circuit description...7
More informationCMOS IC 1/8, 1/9 Duty Dot Matrix LCD Display Controllers/Drivers with Key Input Function
Ordering number : ENA47B LC7582PT CMOS IC /8, /9 Duty Dot Matrix LCD Display Controllers/Drivers with ey Input Function http://onsemi.com Overview The LC7582PT is /8, /9 duty dot matrix LCD display controllers/drivers
More information16COM/80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
6COM/80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD INTRODUCTION The is a dot matrix LCD driver & controller LSI which is fabricated by low power CMOS technology It is capable of displaying or 2 lines with
More informationAssignment 5. You can configure hardware options by setting jumper on the mainboard. See Figure 2-1 for jumper locations. Set a jumper as follows:
CIS 170 Microcomputer Hardware Name: Assignment 5 From the lack of having enough peripherals for this course (at least at this point), we have the necessity of doing some experiments mentally rather than
More informationAVR Development Board
AVR Development Board Campus Component Pvt. Ltd. DISCLAIMER Information furnished is believed to be accurate and reliable at the time of publication. However, Campus Component Pvt. Ltd. assumes no responsibility
More informationAK-STM32-ETH Development Board
AK-STM32-ETH Development Board Reference manual Copyright 2011 Artekit Italy All rights reserved Contents About this document... 3 Revision history... 3 Contact information... 3 Life support policy...
More informationCEIBO FE-W7 Development System
CEIBO FE-W7 Development System Development System for Winbond W7xxxx Microcontrollers FEATURES Emulates Winbond W77xxx or W78xxx Microcontrollers 125K Code Memory Real-Time Emulation Frequency up to fmax
More informationFR30-RAM-Stack-Board Documentation Part-Number: FR-RAM-STACK1-100P-M06
FR30-RAM-Stack-Board Documentation Part-Number: FR-RAM-STACK1-100P-M06 Fujitsu Mikroelektronik GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag, Germany Revision: Date: 1.1 30/7/99 Page 1 Contents Hardware
More information10. Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
September 2012 SIV51010-3.5 10. Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices SIV51010-3.5 This chapter describes the configuration, design security, and remote system
More information13. Configuring Stratix & Stratix GX Devices
13. Configuring Stratix & Stratix GX Devices S52013-2.0 Introduction You can configure Stratix TM and Stratix GX devices using one of several configuration schemes. All configuration schemes use either
More informationProgrammer. User Guide
Programmer User Guide Trademarks & Copyright Windows and Windows NT are registered trademarks of Microsoft Corporation. MCS-51 and Pentium are registered trademarks of Intel Corporation. AVR is registered
More informationInstallation Guide of Hi-Speed USB to Octal RS-232/422/485 Adapter
Installation Guide of Hi-Speed USB to Octal RS-232/422/485 Adapter Introduction The USB to Octal Serial Adapter is designed to make serial port expansion quick and simple. Connecting to a USB port on your
More informationMercury Baseboard Reference Manual
Mercury Baseboard Reference Manual www.micro-nova.com OVERVIEW The Baseboard is a great addition to the Mercury Module, providing a host of on-board components that can be used to design and test a wide
More informationBIG8051. Development system. User manual
BIG8051 User manual All s development systems represent irreplaceable tools for programming and developing microcontroller-based devices. Carefully chosen components and the use of machines of the last
More informationTEMIC 51T (Temic) EMULATION
Note: To use with frequencies above 40Mhz it will be required to use an emulator board that has been specially modified to obtain high frequency operation and will work only with the POD-51Temic. The EPROM
More informationPRELAB! Read the entire lab, and complete the prelab questions (Q1- Q3) on the answer sheet before coming to the laboratory.
PRELAB! Read the entire lab, and complete the prelab questions (Q1- Q3) on the answer sheet before coming to the laboratory. 1.0 Objectives In this lab you will get familiar with the concept of using the
More informationUniversity of Florida EEL 4744 Drs. Eric M. Schwartz, Karl Gugel & Tao Li Department of Electrical and Computer Engineering
Page 1/9 Revision 1 OBJECTIVES In this document you will learn how to solder and to debug a board as you are building it. REQUIRED MATERIALS Website documents o UF 68HC12 Development Board Manual (board
More informationDevelopment System Rev. 0014A
Development System Rev. 0014A NetMedia, Inc. Tucson, Arizona NetMedia, Inc. 10940 N. Stallard Pl Tucson, Arizona 85737 TEL: (520) 544-4567 FAX: (520) 544-0800 PURCHASE TERMS AND CONDITIONS The laws of
More informationZ8 Encore! XP Family of Microcontrollers Development Kits
Z8 Encore! XP Family of Microcontrollers Development Kits Introduction This describes how to set up your Z8 Encore! XP Development Kit and start using it to build designs and applications. Kit Contents
More informationAN 547: Putting the MAX II CPLD in Hibernation Mode to Achieve Zero Standby Current
AN 547: Putting the MAX II CPLD in Hibernation Mode to Achieve Zero Standby Current January 2009 AN-547-10 Introduction To save power, the MAX II CPLD can be completely powered down into hibernation mode
More informationCarrier Board Socket Modem CAB/MOD1
Carrier Board Socket Modem CAB/MOD1 User Manual Content 1 INTRODUCTION...3 1.1 Conventions used in this Document...3 1.2 Checklist...4 1.3 Main Features...5 2 BOARD LAYOUT...6 3 BOARD COMPONENTS...7 3.1
More informationCYTRON USB PIC Programmer v2009 UP00B
CYTRON USB PIC Programmer v2009 UP00B User s Manual V1.0 Nov 2008 Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded
More informationZL10AVR. Versatile Evaluation Board for AVR Microcontrollers
Versatile Evaluation Board for AVR Microcontrollers Thank you for buying ZL10AVR evaluation board. We hope that the power and quality of our tool allow you to appreciate the advantages of AVR microcontrollers
More information