LC75818PT/D. 1/8 to 1/10-Duty Dot Matrix LCD Controller & Driver with Key Input Function

Transcription

1 /8 to /0-Duty Dot Matrix LCD Controller & Driver with ey nput Function Overview The LC7588PT is /8 to /0 duty dot matrix LCD display controllers/drivers that support the display of characters, numbers, and symbols. n addition to generating dot matrix LCD drive signals based on data transferred serially from a microcontroller, the LC7588PT also provide on-chip character display ROM and RAM to allow display systems to be implemented easily. These products also provide up to 4 generalpurpose output ports and incorporate a key scan circuit that accepts input from up to 30 keys to reduce printed circuit board wiring. Features ey input function for up to 30 keys (A key scan is performed only when a key is pressed.) Controls and drives a 57, 58, or 59 dot matrix LCD. Supports accessory display segment drive (up to 80 segments) Display technique: /8 duty /4 bias drive (57 dots) /9 duty /4 bias drive (58 dots) /0 duty /4 bias drive (59 dots) Display digits: 6 digits line (57 dots, 58 dots, 59 dots) Display control memory CGROM: 240 characters (57, 58, or 59 dots) CGRAM: 6 characters (57, 58, or 59 dots) ADRAM: 65 bits DCRAM: 648 bits nstruction function Display on/off control Display shift function Sleep mode can be used to reduce current drain. Built-in display contrast adjustment circuit The frame frequency of the common and segment output waveforms can be controlled by instructions. Serial data /O supports CCB* format communication with the system controller. ndependent LCD driver block power supply VLCD A voltage detection type reset circuit is provided to initialize the C and prevent incorrect display. The NH pin is provided. This pin turns off the display, disables key scanning, and forces the general-purpose output ports to the low level. RC oscillator circuit TQFP20 4x4 / TQFP20 * Computer Control Bus (CCB) is an ON Semiconductor s original bus format and the bus addresses are controlled by ON Semiconductor. ORDERNG NFORMATON See detailed ordering and shipping information on page 44 of this data sheet. Semiconductor Components ndustries, LLC, 207 Publication Order Number : June Rev. LC7588PT/D

2 Specifications Absolute Maximum Ratings at Ta = 25C, VSS = 0 V LC7588PT Parameter Symbol Conditions Ratings Unit Maximum supply voltage VDD max VDD 0.3 to +4.2 V VLCD max VLCD 0.3 to +.0 nput voltage VN, CL, D, NH 0.3 to +4.2, CL, D, NH VDD=2.7 to 3.6V 0.3 to +6.5 VN2 OSC, to 5, TEST 0.3 to VDD +0.3 VN3 VLCD,,, 0.3 to VLCD +0.3 Output voltage VOUT DO 0.3 to +6.5 VOUT2 OSC, S to S6, P to P4 0.3 to VDD +0.3 VOUT3, S to S80, COM to COM0 0.3 to VLCD +0.3 Output current OUT S to S A OUT2 COM to COM0 3 OUT3 S to S6 OUT4 P to P4 5 Allowable power Pd max dissipation Ta = 85C 200 mw Operating temperature Topr 40 to +85 C Storage temperature Tstg 55 to +25 C V V ma Stresses exceeding those listed in the Maximum Ratings table may damage the device. f any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Allowable Operating Range at Ta = 40C to +85C, VSS = 0 V Parameter Symbol Conditions Ratings min typ max Supply voltage VDD VDD VLCD VLCD When the display contrast adjustment circuit is used. VLCD When the display contrast adjustment circuit is not used Output voltage +4.5 VLCD nput voltage VLCD VLCD 3/4 ( ) 2/4 ( ) /4 ( ) 0.5 nput high level voltage VH, CL, D, NH 0.8VDD 3.6, CL, D, NH VDD = 2.7 to 3.6 V 0.8VDD 5.5 VH2 OSC external clock operating mode 0.8VDD VDD unit V V V V VH3 to 5 0.6VDD VDD nput low level voltage VL, CL, D, NH, to VDD V VL2 OSC external clock operating mode 0 0.2VDD Output pull-up voltage VOUP DO V Continued on next page. 2

3 Continued from preceding page. LC7588PT Parameter Symbol Conditions Ratings min typ max unit Recommended external Rosc OSC RC oscillator operating mode resistor for RC oscillation 0 k Recommended external Cosc OSC RC oscillator operating mode capacitor for RC 470 pf oscillation Guaranteed range of RC fosc OSC RC oscillator operating mode oscillation khz External clock operating fc OSC external clock operating mode [Figure 4] frequency khz External clock duty cycle DC OSC external clock operating mode [Figure 4] % Data setup time tds CL, D [Figure 2],[Figure 3] 60 ns Data hold time tdh CL, D [Figure 2],[Figure 3] 60 ns wait time tcp, CL [Figure 2],[Figure 3] 60 ns setup time tcs, CL [Figure 2],[Figure 3] 60 ns hold time tch, CL [Figure 2],[Figure 3] 60 ns High level clock pulse tφh CL [Figure 2],[Figure 3] width 60 ns Low level clock pulse tφl CL [Figure 2],[Figure 3] width 60 ns DO output delay time tdc DO RPU=4.7k CL=0pF *[Figure 2],[Figure 3].5 s DO rise time tdr DO RPU=4.7k CL=0pF *[Figure 2],[Figure 3].5 s Note: *. Since the DO pin is an open-drain output, these times depend on the values of the pull-up resistor RPU and the load capacitance CL. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. Electrical Characteristics for the Allowable Operating Ranges Parameter Symbol Pins Conditions Ratings min typ max Hysteresis VH, CL, D, NH, 0.VDD V to 5 Power-down detection VDET V voltage nput high level H, CL, D, NH V = 3.6 V 5.0 current V = 5.5 V 5.0 VDD = 2.7 to 3.6 V A H2 OSC V = VDD external clock 5.0 operating mode nput low level current L, CL, D, NH V = 0 V -5.0 L2 OSC V = 0 V external clock operating A -5.0 mode nput floating voltage VF to VDD V Pull-down resistance RPD to 5 VDD = 3.3 V k Output off leakage OFFH DO VO = 5.5 V 6.0 A current Output high level VOH S to S80 O = 20 A VLCDO voltage 0.6 VOH2 COM to VLCDO COM0 O = 00 A 0.6 V VOH3 S to S6 O = 250 A VDD VDD VDD VOH4 P to P4 O = ma VDD 0.9 Output low level VOL voltage S to S80 O = 20 A +0.6 VOL2 COM to COM0 O = 00 A +0.6 V VOL3 S to S6 O = 2.5 A VOL4 P to P4 O = ma 0.9 VOL5 DO O = ma unit Continued on next page. 3

4 Continued from preceding page. Parameter Output middle level voltage *2 Symbo l Pins LC7588PT Conditions VMD S to S80 O = 20 A 2/4 ( ) 0.6 Ratings min typ max 2/4 ( ) /4 ( ) +0.6 /4 ( ) +0.6 VMD2 COM to O = 00 A 3/4 COM0 ( V ) 0.6 VMD3 COM to O = 00 A /4 COM0 ( ) 0.6 Oscillator frequency fosc OSC Rosc = 0 k khz Cosc = 470 pf Current drain DD VDD sleep mode 00 DD2 VDD VDD = 3.6 V output open fosc = 300 khz LCD VLCD sleep mode 5 LCD2 VLCD VLCD = 0.0 V output open fosc = 300 khz When the display contrast adjustment circuit is used A LCD3 VLCD VLCD = 0.0 V output open fosc = 300 khz When the display contrast adjustment circuit is not used Note: *2. Excluding the bias voltage generation divider resistor built into the, VLCD,,, and. (See Figure.) unit VLCD CONTRAST ADJUSTER VLCD To the common and segment drivers Excluding these resistors [Figure ] Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4

5 () When CL is stopped at the low level VH CL 50% VL D VH VL DO tds th tdh tl VH tcp D0 tcs tdc D tch VL tdr [Figure 2] (2) When CL is stopped at the high level CL D tl th VH 50% VL V H VL VH tcp tcs tch VL tds tdh DO D0 D tdc tdr (3) OSC pin clock timing in external clock operating mode [Figure 3] OSC VH2 50% VL2 tch tcl fc= [khz] tch + tcl tch DC= tch + tcl 00[%] [Figure 4] 5

6 Package Dimensions unit : mm TQFP20 4x4 / TQFP20 CASE 932AZ SSUE A (.2) MAX (.0) to 0 SOLDERNG FOOTPRNT* 5.40 GENERC MARNG DAGRAM* (Unit: mm) XXXXXXXX YMDDD 5.40 XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data *This information is generic. Please refer to device data sheet for actual part marking NOTE: The measurements are not to guarantee but for reference only. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 6

7 7 Pin Assignments LC7588PT (TQFP20) S5 S S4 S3 S2 S S0 S9 S8 S7 S6 S6 S22 S5 S4 S3 S2 S2 S20 S9 S8 S7 S25 S24 S23 S27 S26 S30 S29 S28 S40 S39 S38 S37 S36 S34 S35 S32 S33 S3 S45 S44 S43 S42 S4 S50 S49 S48 S47 S46 S55 S54 S53 S52 S5 S60 S59 S58 S57 S56 S74 S75 S65 S6 S62 S63 S64 S66 S67 S68 S69 S70 S7 S72 S73 S76 S77 S78 S79 S80 COM0 COM9 COM8 COM7 COM6 COM COM5 COM4 COM3 COM S6 5 VDD VLCD VLCD TEST VSS P2 P P3 OSC P4 NH DO CL D S2 S4 S3 S5 S Top view

8 Block Diagram S80 COMMON DRVER S E G M E N T D R V E R L A T C H NSTRUCTON DECODER ADRAM 80 bits CGRAM 596 bits CGROM bits CONTRAST ADJUSTER NSTRUCTON REGSTER ADDRESS COUNTER ADDRESS REGSTER DCRAM 648 bits S H F T R E G S T E R VDET TMNG GENERATOR CLOC GENERATOR OSC DO D CL S6 S5 S4 S3 S2 S COM COM0 S79 S78 S VLCD VLCD VDD CCB NTERFA EY BUFFER VSS TEST EY SCAN NH P P2 P3 P4 GENERAL PORT 8

9 Pin Functions Handling Pin Pin No. Function Active /O when unused S to S80 to 80 Segment driver outputs. - O OPEN COM to COM0 90 to 8 Common driver outputs. - O OPEN S to S6 9 to 96 ey scan outputs. Although normal key scan timing lines require diodes to be inserted in the timing lines to prevent shorts, since these outputs are unbalanced CMOS transistor outputs, these outputs will not be damaged by shorting when these outputs are used to form a key matrix. - O OPEN to 5 97 to 0 ey scan inputs. These pins have built-in pull-down resistors. H GND P to P4 02 to 05 General-purpose outputs. P4 can be used as a clock output port with the "set key scan output port/general-purpose output port state" instruction. - O OPEN OSC 5 Oscillator connections. An oscillator circuit is formed by connecting an external resistor and capacitor to this pin. This pin can also be used as the external clock input pin with the "set display technique" instruction. - /O V DD 8 Serial data interface connections to the controller. Note that DO, H CL 9 being an open-drain output, requires a pull-up resistor. : Chip enable GND D 20 CL: Synchronization clock - DO 7 D: Transfer data DO: Output data - O OPEN NH 6 nput that turns the display off, disables key scanning, and forces the general-purpose output ports low. When NH is low (V SS ): Display off S to S80= L (V LCD 4) COM to COM0= L (V LCD 4) General-purpose output ports P to P4=low (V SS ) ey scanning disabled: S to S6=low (V SS ) All the key data is reset to low. L V DD When NH is high (V DD ): Display on The state of the pins as key scan output pins or general-purpose output ports can be set with the "set key scan output port/general-purpose output port state" instruction. ey scanning is enabled. However, serial data can be transferred when the NH pin is low. TEST 4 This pin must be connected to ground. - - V LCD 0 08 LCD drive 4/4 bias voltage (high level) supply pin. The level on this pin can be changed by the display contrast adjustment circuit. However, (V LCD 0 - V LCD 4) must be greater than or equal to 4.5V. - O OPEN Also, external power must not be applied to this pin since the pin circuit includes the display contrast adjustment circuit. V LCD 09 LCD drive 3/4 bias voltage (middle level) supply pin. This pin can be used to supply the 3/4 (V LCD 0 - V LCD 4) voltage level - OPEN externally. V LCD 2 0 LCD drive 2/4 bias voltage (middle level) supply pin. This pin can be used to supply the 2/4 (V LCD 0 - V LCD 4) voltage level externally. - OPEN Continued on next page. 9

10 Continued from preceding page. Pin Pin No. Function Active /O Handling when unused V LCD 3 LCD drive /4 bias voltage (middle level) supply pin. This pin can be used to supply the /4 (V LCD 0 - V LCD 4) voltage level - OPEN externally. V LCD 4 2 LCD drive 0/4 bias voltage (low level) supply pin. Fine adjustment of the display contrast can be implemented by connecting an external variable resistor to this pin. However, (V LCD 0 - V LCD 4) must be greater than or equal to 4.5V, and V LCD 4 must be in the range 0V to.5v, inclusive. - GND V DD 06 Logic block power supply connection. Provide a voltage of between 2.7to 3.6V V LCD 07 LCD driver block power supply connection. Provide a voltage of between 7.0 to 0.0V when the display contrast adjustment circuit is used and provide a voltage of between 4.5 to 0.0V when the circuit is not used. V SS 3 Power supply connection. Connect to ground Block Functions AC (address counter) AC is a counter that provides the addresses used for DCRAM and ADRAM. The address is automatically modified internally, and the LCD display state is retained. DCRAM (data control RAM) DCRAM is RAM that is used to store display data expressed as 8-bit character codes. (These character codes are converted to 57, 58, or 59 dot matrix character patterns using CGROM or CGRAM.) DCRAM has a capacity of 648 bits, and can hold 64 characters. The table below lists the correspondence between the 6-bit DCRAM address loaded into AC and the display position on the LCD panel. When the DCRAM address loaded into AC is 00H. Display digit DCRAM address (hexadecimal) A 0B 0C 0D 0E 0F However, when the display shift is performed by specifying MDATA, the DCRAM address shifts as shown below. Display digit DCRAM address (hexadecimal) A 0B 0C 0D 0E 0F 0 (shift left) Display digit DCRAM address (hexadecimal) 3F A 0B 0C 0D 0E (shift right) Note: *3. The DCRAM address is expressed in hexadecimal. Least significant bit LSB DCRAM address DA0 DA DA2 DA3 DA4 DA5 Hexadecimal Most significant bit MSB Hexadecimal Example: When the DCRAM address is 2EH. DA0 DA DA2 DA3 DA4 DA

11 ADRAM (Additional data RAM) ADRAM is RAM that is used to store the ADATA display data. ADRAM has a capacity of 65 bits, and the stored display data is displayed directly without the use of CGROM or CGRAM. The table below lists the correspondence between the 4-bit ADRAM address loaded into AC and the display position on the LCD panel. When the ADRAM address loaded into AC is 0H. (Number of digit displayed: 6) Display digit ADRAM address (hexadecimal) A B C D E F However, when the display shift is performed by specifying ADATA, the ADRAM address shifts as shown below. Display digit ADRAM address (hexadecimal) A B C D E F 0 (shift left) Display digit ADRAM address (hexadecimal) F A B C D E (shift right) Note: *4. The ADRAM address is expressed in hexadecimal. Least significant bit LSB ADRAM address RA0 RA RA2 RA3 Hexadecimal Most significant bit MSB Example: When the ADRAM address is AH. RA0 RA RA2 RA3 0 0 CGROM (Character generator ROM) CGROM is ROM that is used to generate the 240 kinds of 57, 58, or 59 dot matrix character patterns from the 8- bit character codes. CGROM has a capacity of bits. When a character code is written to DCRAM, the character pattern stored in CGROM corresponding to the character code is displayed at the position on the LCD corresponding to the DCRAM address loaded into AC. CGRAM (Character generator RAM) CGRAM is RAM to which user programs can freely write arbitrary character patterns. Up to 6 kinds of 57, 58, or 59 dot matrix character patterns can be stored. CGRAM has a capacity of 645 bits.

12 Serial Data nput () When CL is stopped at the low level CL D DO D0 D D2 D3 D4 B0 B B2 B3 A0 A A2 A3 nstruction data (Up to 64 bits) D62 D63 (2) When CL is stopped at the high level CL D DO D0 D B0 B B2 B3 A0 A A2 A3 D2 D3 D4 D62 D63 nstruction data (Up to 64 bits) B0 to B3, A0 to A3: CCB address 42H D0 to D63: nstruction data The data is acquired on the rising edge of the CL signal and latched on the falling edge of the signal. When transferring instruction data from the microcontroller, applications must assure that the time from the transfer of one set of instruction data until the next instruction data transfer is significantly longer than the instruction execution time. 2

13 nstruction Table nstruction D0 D... D39 D40 D4 D42 D43 D44 D45 D46 D47 D48 D49 D50 D5 D52 D53 D54 D55 D56 D57 D58 D59 D60 D6 D62 D63 Set display technique DT DT2 FC OC *5 Display on/off control DG DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG0 DG DG2 DG3 DG4 DG5 DG6 M A SC SP Display shift M A R/L X 0 0 Set AC address DA0 DA DA2 DA3 DA4 DA5 X X RA0 RA RA2 RA DCRAM data write *6 AC0 AC AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA DA2 DA3 DA4 DA5 X X M X X X 0 0 ADRAM data write *7 AD AD2 AD3 AD4 AD5 X X X RA0 RA RA2 RA3 X X X X M X X X 0 0 CGRAM data write CD CD2 CD40 CD4 CD42 CD43 CD44 CD45 X X X CA0 CA CA2 CA3 CA4 CA5 CA6 CA7 X X X X 0 Set display contrast CT0 CT CT2 CT3 X X X X CTC X X X Set key scan output port/ general-purpose output port state C C2 C3 C4 C5 C6 PC40 PC4 PC PC2 PC3 X 0 0 Notes: *5. Be sure to execute the "set display technique" instruction first after power-on (VDET-based system reset). Note that the execution time of this first instruction is 08s (fosc=300khz, fc=300khz). *6. The data format differs when the DCRAM data write instruction is executed in the increment mode (M = ). (See detailed instruction descriptions.) *7. The data format differs when the ADRAM data write instruction is executed in the increment mode (M = ). (See detailed instruction descriptions.) *8. The execution times listed here apply when fosc=300khz, fc=300khz. The execution times differ when the oscillator frequency fosc or the external clock frequency fc differs. Example: When fosc = 20kHz, fc = 20kHz s = 39s, 08s = 55s *9.When the sleep mode (SP = ) is set, the execution time is 27s (when fosc = 300kHz, fc = 300kHz). Execution time *8 0s/08s *5 0s/27s *9 27s 27s 27s 27s 27s 0s 0s X: don t care 3

14 Detailed nstruction Descriptions Set display technique... <Sets the display technique> (Display technique) Code D56 D57 D58 D59 D60 D6 D62 D63 DT DT2 FC 0C X: don t care DT, DT2: Sets the display technique DT DT2 Display technique LC7588PT COM9 Output pins COM0 0 0 /8 duty, /4 bias drive level level 0 /9 duty, /4 bias drive COM9 level 0 /0 duty, /4 bias drive COM9 COM0 FC: Sets the frame frequency of the common and segment output waveforms FC /8 duty, /4 bias drive f8[hz] Frame frequency /9 duty, /4 bias drive f9[hz] /0 duty, /4 bias drive f0[hz] 0 fosc/3072, f C /3072 fosc/3456, f C /3456 fosc/3840, f C /3840 fosc/536, f C /536 fosc/728, f C /728 fosc/920, f C /920 OC: Sets the RC oscillator operating mode and external clock operating mode. OC OSC pin function 0 RC oscillator operating mode External clock operating mode Note: *. When selecting the RC oscillator operating mode, be sure to connect an external resistor Rosc and an external capacitor Cosc to the OSC pin. Display on/off control... <Turns the display on or off> (Display ON/OFF control) Code D40 D4 D42 D43 D44 D45 D46 D47 D48 D49 D50 D5 D52 D53 D54 D55 D56 D57 D58 D59 D60 D6 D62 D63 DG DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG0 DG DG2 DG3 DG4 DG5 DG6 M A SC SP X: don t care M, A: Specifies the data to be turned on or off M A Display operating state 0 0 Both MDATA and ADATA are turned off (The display is forcibly turned off regardless of the DG to DG6 data.) 0 Only ADATA is turned on (The ADATA of display digits specified by the DG to DG6 data are turned on.) 0 Only MDATA is turned on (The MDATA of display digits specified by the DG to DG6 data are turned on.) Note: Be sure to execute the "set display technique" instruction first after power-on (VDET-based system reset). Both MDATA and ADATA are turned on (The MDATA and ADATA of display digits specified by the DG to DG6 data are turned on.) Note: *0. COMn (n=9,0): Common output Note: *2. MDATA, ADATA 57 dot matrix display 58 dot matrix display 59 dot matrix display ADATA ADATA ADATA --- MDATA --- MDATA --- MDATA 4

15 DG to DG6: Specifies the display digit LC7588PT Display digit Display digit data DG DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG0 DG DG2 DG3 DG4 DG5 DG6 For example, if DG to DG7 are, and DG8 to DG6 are 0, then display digits to 7 will be turned on, and display digits 8 to 6 will be turned off (blanked). SC: Controls the common and segment output pins SC Common and segment output pin states 0 Output of LCD drive waveforms Fixed at the V LCD 4 level (all segments off) Note: *3. When SC is, the S to S80 and COM to COM0 output pins are set to the level, regardless of the M, A, and DG to DG6 data. SP: Controls the normal mode and sleep mode SP 0 Normal mode Mode Sleep mode The common and segment pins go to the V LCD 4 level and the oscillator on the OSC pin is stopped (although it operates during key scan operations) in RC oscillator operating mode (OC="0") and reception of the external clock is stopped (external clock is received during key scan operations) in external clock operating mode (OC=""), to reduce current drain. Although the "display on/off control", "set display contrast" and "set key scan output port/general-purpose output port state" (disallowed to set the clock output at the P4 pin) instructions can be executed in this mode, applications must return the C to normal mode to execute any of the other instruction setting. When the C is in external clock operating mode, be sure to stop the external clock input after the lapse of the instruction execution time (27s: f C =300kHz). Display shift... <Shifts the display> (Display shift) Code D56 D57 D58 D59 D60 D6 D62 D63 M A R/L X 0 0 X: don t care M, A: Specifies the data to be shifted M A Shift operating state 0 0 Neither MDATA nor ADATA is shifted 0 Only ADATA is shifted 0 Only MDATA is shifted Both MDATA and ADATA are shifted R/L: Specifies the shift direction R/L Shift direction 0 Shift left Shift right 5

16 Set AC address... <Specifies the DCRAM and ADRAM address for AC> (Set AC) Code D48 D49 D50 D5 D52 D53 D54 D55 D56 D57 D58 D59 D60 D6 D62 D63 DA0 DA DA2 DA3 DA4 DA5 X X RA0 RA RA2 RA X: don t care DA0 to DA5: DCRAM address DA0 DA DA2 DA3 DA4 DA5 LSB MSB Least significant bit Most significant bit RA0 to RA3: ADRAM address RA0 RA RA2 RA3 LSB MSB Least significant bit Most significant bit This instruction loads the 6-bit DCRAM address DA0 to DA5 and the 4-bit ADRAM address RA0 to RA3 into the AC. DCRAM data write... <Specifies the DCRAM address and stores data at that address> (Write data to DCRAM) Code D40 D4 D42 D43 D44 D45 D46 D47 D48 D49 D50 D5 D52 D53 D54 D55 D56 D57 D58 D59 D60 D6 D62 D63 AC0 AC AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA DA2 DA3 DA4 DA5 X X M X X X 0 0 X: don t care DA0 to DA5: DCRAM address DA0 DA DA2 DA3 DA4 DA5 LSB MSB Least significant bit Most significant bit AC0 to AC7: DCRAM data (character code) AC0 AC AC2 AC3 AC4 AC5 AC6 AC7 LSB Least significant bit MSB Most significant bit This instruction writes the 8 bits of data AC0 to AC7 to DCRAM. This data is a character code, and is converted to a 57, 5 8, or 59 dot matrix display data using CGROM or CGRAM. M: Sets the method of writing data to DCRAM M DCRAM data write method 0 Normal DCRAM data write (Specifies the DCRAM address and writes the DCRAM data.) ncrement mode DCRAM data write (ncrements the DCRAM address by + each time data is written to DCRAM.) 6

17 Notes: *4. DCRAM data write method when M = 0 CCB address D DCRAM () 24 bit CCB address () 24 bit CCB address () 24 bit CCB address () 24 bit nstruction execution time DCRAM data write finishes nstruction execution time DCRAM data write finishes nstruction execution time DCRAM data write finishes nstruction execution time DCRAM data write finishes DCRAM data write method when M = (nstructions other than the DCRAM data write instruction cannot be executed.) CCB address D DCRAM CCB address CCB address CCB address CCB address CCB address () (2) (2) (2) (2) (3) 24 bit 8 bit 8 bit 8 bit 8 bit 6 bit nstruction execution time DCRAM data write finishes nstruction execution time nstruction execution time DCRAM data write finishes DCRAM data write finishes nstruction execution time nstruction execution time DCRAM data write finishes DCRAM data write finishes nstructions other than the DCRAM data write instruction cannot be executed. nstruction execution time DCRAM data write finishes Data format at () (24 bits) Code D40 D4 D42 D43 D44 D45 D46 D47 D48 D49 D50 D5 D52 D53 D54 D55 D56 D57 D58 D59 D60 D6 D62 D63 AC0 AC AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA DA2 DA3 DA4 DA5 X X M X X X 0 0 X: don t care Data format at (2) (8 bits) D56 Code D57 D58 D59 D60 D6 D62 D63 AC0 AC AC2 AC3 AC4 AC5 AC6 AC7 Data format at (3) (6 bits) Code D48 D49 D50 D5 D52 D53 D54 D55 D56 D57 D58 D59 D60 D6 D62 D63 AC0 AC AC2 AC3 AC4 AC5 AC6 AC7 0 X X X 0 0 X: don t care ADRAM data write... <Specifies the ADRAM address and stores data at that address> (Write data to ADRAM) Code D40 D4 D42 D43 D44 D45 D46 D47 D48 D49 D50 D5 D52 D53 D54 D55 D56 D57 D58 D59 D60 D6 D62 D63 AD AD2 AD3 AD4 AD5 X X X RA0 RA RA2 RA3 X X X X M X X X 0 0 X: don t care RA0 to RA3:ADRAM address RA0 RA RA2 RA3 LSB MSB Least significant bit Most significant bit 7

18 AD to AD5: ADATA display data n addition to the 57, 58, or 59 dot matrix display data (MDATA), this C supports direct display of the five accessory display segments provided in each digit as ADATA. This display function does not use CGROM or CGRAM. The figure below shows the correspondence between the data and the display. When ADn = (where n is an integer between and 5) the segment corresponding to that data will be turned on. S5m+ S5m+5 (m is an integer between 0 and 5) ADATA Corresponding output pin AD S5m+ (m is an integer between 0 and 5) AD2 S5m+2 AD3 S5m+3 AD4 S5m+4 AD5 S5m+5 M: Sets the method of writing data to ADRAM M ADRAM data write method 0 Normal ADRAM data write (Specifies the ADRAM address and writes the ADRAM data.) ncrement mode ADRAM data write (ncrements the ADRAM address by + each time data is written to ADRAM.) Notes: *5. ADRAM data write method when M = 0 CCB address D ADRAM (4) 24 bit CCB address (4) 24 bit CCB address (4) 24 bit CCB address (4) 24 bit nstruction execution time nstruction execution time ADRAM data write finishes nstruction execution time ADRAM data write finishes ADRAM data write finishes nstruction execution time ADRAM data write finishes ADRAM data write method when M = (nstructions other than the ADRAM data write instruction cannot be executed.) CCB address D (4) CCB address (5) CCB address (5) CCB address (5) CCB address (5) CCB address (6) ADRAM 24 bit 8 bit 8 bit 8 bit 8 bit 6 bit nstruction execution time nstruction execution time nstruction execution time nstruction execution time nstruction execution time nstruction execution time ADRAM data write finishes ADRAM data write finishes ADRAM data write finishes ADRAM data write finishes ADRAM data write finishes ADRAM data write finishes nstructions other than the ADRAM data write instruction cannot be executed. 8

19 Data format at (4) (24 bits) LC7588PT Code D40 D4 D42 D43 D44 D45 D46 D47 D48 D49 D50 D5 D52 D53 D54 D55 D56 D57 D58 D59 D60 D6 D62 D63 AD AD2 AD3 AD4 AD5 X X X RA0 RA RA2 RA3 X X X X M X X X 0 0 X: don t care Data format at (5) (8 bits) Code D56 D57 D58 D59 D60 D6 D62 D63 AD AD2 AD3 AD4 AD5 X X X X: don t care Data format at (6) (6 bits) Code D48 D49 D50 D5 D52 D53 D54 D55 D56 D57 D58 D59 D60 D6 D62 D63 AD AD2 AD3 AD4 AD5 X X X 0 X X X 0 0 X: don t care CGRAM data write... <Specifies the CGRAM address and stores data at that address> (Write data to CGRAM) Code D0 D D2 D3 D4 D5 D6 D7 D8 D9 D0 D D2 D3 D4 D5 CD CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD0 CD CD2 CD3 CD4 CD5 CD6 Code D6 D7 D8 D9 D20 D2 D22 D23 D24 D25 D26 D27 D28 D29 D30 D3 CD7 CD8 CD9 CD20 CD2 CD22 CD23 CD24 CD25 CD26 CD27 CD28 CD29 CD30 CD3 CD32 Code D32 D33 D34 D35 D36 D37 D38 D39 D40 D4 D42 D43 D44 D45 D46 D47 CD33 CD34 CD35 CD36 CD37 CD38 CD39 CD40 CD4 CD42 CD43 CD44 CD45 X X X Code D48 D49 D50 D5 D52 D53 D54 D55 D56 D57 D58 D59 D60 D6 D62 D63 CA0 CA CA2 CA3 CA4 CA5 CA6 CA7 X X X X 0 X: don t care CA0 to CA7: CGRAM address CA0 CA CA2 CA3 CA4 CA5 CA6 CA7 LSB MSB Least significant bit Most significant bit CD to CD45: CGRAM data (57, 58, or 59 dot matrix display data) The bit CDn (where n is an integer between and 45) corresponds to the 57, 58, or 59 dot matrix display data. The figure below shows that correspondence. When CDn is the dots which correspond to that data will be turned on. CD CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD0 CD CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD20 CD2 CD22 CD23 CD24 CD25 CD26 CD27 CD28 CD29 CD30 CD3 CD32 CD33 CD34 CD35 CD36 CD37 CD38 CD39 CD40 CD4 CD42 CD43 CD44 CD45 Note: *6. CD to CD35: 57 dot matrix display data CD to CD40: 58 dot matrix display data CD to CD45: 59 dot matrix display data 9

20 Set display contrast <Sets the display contrast> (Set display contrast) LC7588PT Code D48 D49 D50 D5 D52 D53 D54 D55 D56 D57 D58 D59 D60 D6 D62 D63 CT0 CT CT2 CT3 X X X X CTC X X X X: don t care CT0 to CT3: Sets the display contrast ( steps) CT0 CT CT2 CT3 LCD drive 4/4 bias voltage supply V LCD 0 level V LCD =V LCD -(0.03V LCD 2) V LCD =V LCD -(0.03V LCD 3) V LCD =V LCD -(0.03V LCD 4) V LCD =V LCD -(0.03V LCD 5) V LCD =V LCD -(0.03V LCD 6) V LCD =V LCD -(0.03V LCD 7) V LCD =V LCD -(0.03V LCD 8) V LCD =V LCD -(0.03V LCD 9) V LCD =V LCD -(0.03V LCD 0) V LCD =V LCD -(0.03V LCD ) V LCD =V LCD -(0.03V LCD 2) CTC: Sets the display contrast adjustment circuit state CTC Display contrast adjustment circuit state 0 The display contrast adjustment circuit is disabled, and the V LCD 0 pin level is forced to the V LCD level. The display contrast adjustment circuit operates, and the display contrast is adjusted. Note that although the display contrast can be adjusted by operating the built-in display contrast adjustment circuit, it is also possible to apply fine adjustments to the contrast by connecting an external variable resistor to the pin and modifying the pin voltage. However, the following conditions must be met: -4.5V, and.5v 0V. Set key scan output port/general-purpose output port state... <Sets the key scan output port and general-purpose output port states> (ey scan output port and General-purpose output port control) Code D48 D49 D50 D5 D52 D53 D54 D55 D56 D57 D58 D59 D60 D6 D62 D63 C C2 C3 C4 C5 C6 PC40 PC4 PC PC2 PC3 X 0 0 X:don t care C to C6: Sets the key scan output pin S to S6 state Output pin S S2 S3 S4 S5 S6 ey scan output state setting data C C2 C3 C4 C5 C6 When C to C3 are set to and C4 to C6 are set to 0, in the key scan standby state, the S to S3 output pins will output the high level (VDD) and S4 to S6 will output the low level (VSS). Note that key scan output signals are not output from output pins that are set to the low level. PC, PC2, PC3: Sets the general-purpose output port P, P2, P3 state Output pin P P2 P3 General-purpose output port state setting PC PC2 PC3 When PC is set to and PC2 to PC3 are set to 0, P output pin will output the high levels (VDD) and P2 to P3 will output the low levels (VSS). 20

21 PC40, PC4: Sets the general-purpose output port P4 state PC40 PC4 Output pin (P4) state 0 0 L (V SS ) 0 H (V DD ) 0 Clock signal output (fosc/2, f C /2) Clock signal output (fosc/8, f C /8) Serial Data Output () When CL is stopped at the low level CL D DO B0 B B2 B3 A0 A A2 A3 X D D2 D27 D28 D29 D30 SA (2) When CL is stopped at the high level Output data X: don t care CL D DO B0 B B2 B3 A0 A A2 A3 X D D2 D3 D28 D29 D30 SA X Output data X: don t care B0 to B3, A0 to A3: CCB address 43H D to D30: ey data SA: Sleep acknowledge data Note: *7. f a key data read operation is executed when DO is high, the read key data (D to D30) and sleep acknowledge data(sa) will be invalid. Output Data () D to D30: ey data When a key matrix of up to 30 keys is formed from the S to S6 output pins and the to 5 input pins and one of those keys is pressed, the key output data corresponding to that key will be set to. The table shows the relationship between those pins and the key data bits S D D2 D3 D4 D5 S2 D6 D7 D8 D9 D0 S3 D D2 D3 D4 D5 S4 D6 D7 D8 D9 D20 S5 D2 D22 D23 D24 D25 S6 D26 D27 D28 D29 D30 (2) SA : Sleep acknowledge data This output data bit is set to the state when the key was pressed. Also, while DO will be low in this case, if serial data is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. SA will be in Sleep mode and 0 in normal mode. 2

22 ey Scan Operation Functions () ey scan timing The key scan period is 2304T(s). To reliably determine the on/off state of the keys, the LC7588PT scans the keys twice and determines that a key has been pressed when the key data agrees. t outputs a key data read request (a low level on DO) 4800T(s) after starting a key scan. f the key data dose not agree and a key was pressed at that point, it scans the keys again. Thus the LC7588PT cannot detect a key press shorter than 4800T(s). S *8 *8 S2 *8 2 2 *8 S3 *8 3 3 *8 T= fosc S4 *8 4 4 *8 T= fc S5 *8 5 5 *8 S6 *8 6 6 *8 ey on 4608T[s] Note: *8. Not that the high/low states of these pins are determined by the "set key scan output port/general-purpose output port state" instruction, and that key scan output signals are not output from pins that are set to low. (2) n normal mode The pins S to S6 are set to high or low with the "set key scan output port/general-purpose output port state" instruction. f a key on one of the lines corresponding to a S to S6 pin which is set high is pressed, a key scan is started and the keys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple key data bits are set. f a key is pressed for longer than 4800T(s) (Where T=/fosc, T=/fC) the LC7588PT outputs a key data read request (a low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if is high during a serial data transfer, DO will be set high. After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC7588PT performs another key scan. Also note that DO, being an open-drain output, requires a pull-up resistor (between k and 0 k). ey input ey input 2 ey scan 4800T[s] 4800T[s] 4800T[s] D Serial data transfer Serial data transfer ey address (43H) Serial data transfer ey address ey address DO ey data read ey data read ey data read ey data read request ey data read request ey data read request T= fosc T= fc 22

23 (3) n sleep mode The pins S to S6 are set to high or low with the "set key scan output port/general-purpose output port state" instruction. f a key on one of the lines corresponding to a S to S6 pin which is set high is pressed in the RC oscillator operating mode, the oscillator on the OSC pin is started (the C starts receiving the external clock in external clock operating mode) and a key scan is performed. eys are scanned until all keys released. Multiple key presses are recognized by determining whether multiple key data bits are set. f a key is pressed for longer than 4800T(s) (Where T=/fosc, T=/fC) the LC7588PT outputs a key data read request (a low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if is high during a serial data transfer, DO will be set high. After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC7588PT performs another key scan. However, this dose not clear sleep mode. Also note that DO, being an open-drain output, requires a pull-up resistor (between k and 0 k). Sleep mode key scan example Example: When a "display on/off control (SP=)" instruction and a "set key scan output port/general-purpose output port state (C to C5= 0, C6=)" instruction are executed. (i.e. sleep mode with only S6 high.) L S L S2 L S3 L S4 L S5 H S *9 When any one of these keys is pressed in RC oscillator operating mode, the oscillator on the OSC pin is started (the C starts receiving the external clock in external clock operating mode) and the keys are scanned. Note: *9. These diodes are required to reliably recognize multiple key presses on the S6 line when sleep mode state with only S6 high, as in the above example. That is, these diodes prevent incorrect operations due to sneak currents in the S6 key scan output signal when keys on the S to S5 lines are pressed at the same time. ey input (S6 line) ey scan 4800T[s] 4800T[s] Serial data transfer Serial data transfer D ey address (43H) Serial data transfer ey address T= T= fosc fc DO ey data read request ey data read ey data read ey data read request Multiple ey Presses Although the LC7588PT is capable of key scanning without inserting diodes for dual key presses, triple key presses on the to 5 input pin lines, or multiple key presses on the S to S6 output pin lines, multiple presses other than these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be inserted in series with each key. Applications that do not recognize multiple key presses of three or more keys should check the key data for three or more bits and ignore such data. 23

24 /8 Duty, /4 Bias Drive Technique COM COM2 VLCD VLCD COM8 VLCD LCD driver output when all LCD segments corresponding to COM to COM8 are turned off LCD driver output when only LCD segments corresponding to COM are turned on LCD driver output when only LCD segments corresponding to COM2 are turned on LCD driver output when all LCD segments corresponding to COM to COM8 are turned on VLCD VLCD VLCD VLCD T8 8 T8 T8= f8 When a "set display technique" instruction with FC = 0 is executed: f8 = fosc, f8 = 3072 fosc When a "set display technique" instruction with FC = is executed: f8 =, f8 = 536 fc 3072 fc

25 /9 Duty, /4 Bias Drive Technique COM COM2 VLCD VLCD COM9 VLCD LCD driver output when all LCD segments corresponding to COM to COM9 are turned off LCD driver output when only LCD segments corresponding to COM are turned on LCD driver output when only LCD segments corresponding to COM2 are turned on LCD driver output when all LCD segments corresponding to COM to COM9 are turned on VLCD VLCD VLCD VLCD T9 9 T9 T9= f9 When a "set display technique" instruction with FC = 0 is executed: f9 = fosc 3456, f9 = fosc When a "set display technique" instruction with FC = is executed: f9 = 728,f9 = fc 3456 fc

26 /0 Duty, /4 Bias Drive Technique COM COM2 VLCD VLCD COM0 VLCD LCD driver output when all LCD segments corresponding to COM to COM0 are turned off LCD driver output when only LCD segments corresponding to COM are turned on LCD driver output when only LCD segments corresponding to COM2 are turned on LCD driver output when all LCD segments corresponding to COM to COM0 are turned on VLCD VLCD VLCD VLCD T0 0 T0 T0= f0 When a "set display technique" instruction with FC = 0 is executed: f0 = fosc, f0 = 3840 fosc When a "set display technique" instruction with FC = is executed: f0 =, f0 = 920 fc 3840 fc

27 Clock Signal Output Waveform P4 Tc Tc/2 Tc= fc "Set ey Scan Output Port/ General-purpose Port State" nstruction Data General-purpose port P4 clock signal frequency PC40 PC4 fc (/Tc) [Hz] 0 Clock signal output (fosc/2, f C /2) Clock signal output (fosc/8, f C /8) Voltage Detection Type Reset Circuit (VDET) This circuit generates an output signal and resets the system when logic block power is first applied and when the voltage drops, i.e., when the logic block power supply voltage is less than or equal to the power down detection voltage VDET,which is 2.2 V, typical. To assure that this function operates reliably, a capacitor must be added to the logic block power supply line so that the logic block power supply voltage VDD rise time when the logic block power is first applied and the logic block power supply voltage VDD fall time when the voltage drops are both at least ms. (See Figure 5.) Power Supply Sequence The following sequences must be observed when power is turned on and off. (See Figure 5.) Power on: Logic block power supply(vdd) on LCD driver block power supply (VLCD) on Power off: LCD driver block power supply(vlcd) off Logic block power supply (VDD) off When 5 V signal is applied to the, CL, D, and NH pins which are to be connected to the controller and if the logic block power supply (VDD) is off, set the input voltage at the, CL, D, and NH pins to 0V and apply the 5 V signal to these pins after turning on the logic block power supply (VDD). System Reset. Reset function The LC7588PT performs a system reset with the VDET. When a system reset is applied, the display is turned off, key scanning is disabled, the key data is reset, and the general-purpose output ports are set to and held at the low level (VSS). These states that are created as a result of the system reset can be cleared by executing the instruction described below. (See Figure 5.) Clearing the display off state Display operation can be enabled by executing a display on/off control instruction. However, since the contents of the DCRAM, ADRAM, and CGRAM are undefined, applications must set the contents of these memories before turning on display with the display on/off control instruction. That is, applications must execute the following instructions. Set display technique (The "set display technique" instruction must be executed first.) DCRAM data write ADRAM data write (f the ADRAM is used.) CGRAM data write (f the CGRAM is used.) Set AC address Set display contrast (f the display contrast adjustment circuit is used.) After executing the above instructions, applications must turn on the display with a display on/off control instruction. Note that when applications turn off in the normal mode, applications must turn off the display with a display on/off control instruction or the NH pin. 27

28 Clearing the key scan disable and key data reset states By executing the following instructions not only create a state in which key scanning can be performed, but also clear the key data reset. "Set display technique" (The "set display technique" instruction must be executed first.) "Set key scan output port / general-purpose output port state" Clearing the general-purpose output ports locked at the low level (VSS) state By executing the following instructions clear the general-purpose output ports locked at the low level (VSS) state and set the states of the general-purpose output ports. "Set display technique" (The "set display technique" instruction must be executed first.) "Set key scan output port / general-purpose output port state" t t2 t3 t4 VDD VDET VDET VLCD nstruction execution nitial state settings ey scan Disabled Execution enabled General-purpose output ports Fixed at the low level (VSS) Can be set to such states as high (VDD), or low (VSS) level Display state Display off Display on Display off "Set display technique" and Set key scan output port/ general-purpose output port state instruction execution Display on/off control instruction execution (Turning the display on) Display on/off control instruction execution (Turning the display off) t [ms] (Logic block power supply voltage VDD rise time) t2 0 t3 0 t4 [ms] (Logic block power supply voltage VDD fall time) nitial state settings Set display technique (The "set display technique" instruction must be executed first.) DCRAM data write ADRAM data write (f the ADRAM is used.) CGRAM data write (f the CGRAM is used.) Set AC address Set display contrast (f the display contrast adjustment circuit is used.) [Figure 5] 28

29 2. Block states during a system reset () CLOC GENERATOR,TMNG GENERATOR When a reset is applied, these circuits are forcibly initialized internally. Then, when the "set display technique" instruction is executed, oscillation of the OSC pin starts in RC oscillator operating mode (the C starts receiving the external clock in external clock operating mode), execution of the instruction is enabled. (2) NSTRUCTON REGSTER, NSTRUCTON DECODER When a reset is applied, these circuits are forcibly initialized internally. Then, when instruction execution starts, the C operates according to those instructions. (3) ADDRESS REGSTER, ADDRESS COUNTER When a reset is applied, these circuits are forcibly initialized internally. Then, the DCRAM and the ADRAM addresses are set when Set AC address instruction is executed. (4) DCRAM, ADRAM, CGRAM Since the contents of the DCRAM, ADRAM, and CGRAM become undefined during a reset, applications must execute DCRAM data write, ADRAM data write (f the ADRAM is used.), and CGRAM data write (f the CGRAM is used.) instructions before executing a display on/off control instruction. (5) CGROM Character patterns are stored in this ROM. (6) LATCH Although the value of the data in the latch is undefined during a reset, the ADRAM, CGROM, and CGRAM data is stored by executing a display on/off control instruction. (7) COMMON DRVER, SEGMENT DRVER These circuits are forced to the display off state when a reset is applied. (8) CONTRAST ADJUSTER Display contrast adjustment circuit operation is disabled when a reset is applied. After that, the display contrast can be set by executing a set display contrast instruction. (9) EY SCAN, EY BUFFER When a reset is applied, these circuits are forcibly initialized internally, and key scan operation is disabled. Also, the key data is all set to 0. After that, key scanning can be performed by executing a "set key scan output port/general-purpose output port state" instruction. (0) GENERAL PORT When a reset is applied, the general-purpose output port state is locked at the low level (VSS). () CCB NTERFA, SHFT REGSTER These circuits go to the serial data input wait state. 29

30 NH S80 S79 COMMON DRVER S E G M E N T D R V E R L A T C H NSTRUCTON DECODER ADRAM 80 bits CGRAM 596 bits CGROM bits CONTRAST ADJUSTER NSTRUCTON REGSTER ADDRESS COUNTER ADDRESS REGSTER DCRAM 648 bits S H F T R E G S T E R VDET TMNG GENERATOR CLOC GENERATOR OSC DO D CL S6 S5 S4 S3 S2 S P P2 P3 P4 COM COM0 S78 S GENERAL PORT VLCD VLCD VDD CCB NTERFA EY BUFFER VSS TEST EY SCAN Blocks that are reset (3) Output pin states during the reset period Output pin S to S80 COM to COM0 S to S6 P to P4 D0 L (V LCD 4) L (V LCD 4) L (V SS ) L (V SS ) H *20 State during reset Note: *20. Since this output pin is an open-drain output, a pull-up resistor (between k and 0 k) is required. This pin is held at the high level even if a key data read operation is performed before executing the "set display technique" or "set key scan output port/general-purpose output port state" instruction. 30

31 OSC Pin Peripheral Circuit () RC oscillator operating mode (when the "set display technique (OC = 0)" instruction is executed) When RC oscillator operating mode is selected, an external resistor Rosc and an external capacitor Cosc must be connected between the OSC pin and GND. OSC Rosc Cosc (2) External clock operating mode (when the "set display technique (OC = )" instruction is executed) When selecting the external clock operating mode, connect a current protection resistor Rg (2.2 to 22 k) between the OSC pin and external clock output pin (external oscillator). Determine the value of the resistance according to the maximum allowable current value at the external clock output pin. Also make sure that the waveform of the external clock is not heavily distorted. External clock output pin External oscillator Rg OSC Note: *2. Allowable current value at external clock output pin > VDD Rg Note when applying a 5V signal to the, CL, D, and NH pins When applying a 5 V signal to the, CL, D, and NH pins which are to be connected to the controller, set the input voltage to the, CL, D, and NH pins to 0V if the logic block power supply (VDD) is off, and apply the 5 V signal to those pins after turning on the logic block power supply (VDD). 3

32 Sample Application Circuit /8 duty, /4 bias drive technique (for use with normal panels) LCD panel +3.3V +8V C0.047F C C *22 C OPEN VDD TEST VSS VLCD VLCD *23 OSC *24 COM COM2 COM3 COM4 COM5 COM6 COM7 COM8 S S2 S3 S4 S5 S6 S7 S8 S9 S0 *27 From the controller To the controller To the controller power supply *26 NH *25 CL D DO S 6 S S S S 2 S S76 S77 S78 S79 S80 P P2 P3 P4 General-purpose output ports used with the backlight controller or other circuit ey matrix (up to 30 keys) Note *22. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least ms, as the LC7588PT is reset by the VDET. *23. f a variable resistor is not used for display contrast fine adjustment, the pin must be connected to ground. *24. n RC oscillator operating mode, an external resistor, Rosc, and an external capacitor, Cosc, must be connected between the OSC pin and ground. When selecting the external clock operating mode, connect a current protection resistor Rg (2.2 to 22 k) between the OSC pin and the external clock output pin (external oscillator). (See the OSC Pin Peripheral Circuit section.) *25. f the function of NH pin is not used, the NH pin must be connected to the logic block power supply VDD. *26. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between k and 0 k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. *27 When applying a 5 V signal to the, CL, D, and NH pins, set the input voltage to 0 V if the logic block power supply (VDD) is off, and apply the 5 V signal to those pins after turning on the logic block power supply (VDD). 32

33 Sample Application Circuit 2 /8 duty, /4 bias drive technique (for use with large panels) LCD panel +3.3V +8V C C0.047F 0kR2.2k C *22 R R R C R VDD TEST VSS VLCD VLCD *23 OSC *24 COM COM2 COM3 COM4 COM5 COM6 COM7 COM8 S S2 S3 S4 S5 S6 S7 S8 S9 S0 From the controller To the controller To the controller power supply *27 *26 NH *25 CL D DO S 6 S 5 S 4 S 3 S S 2 S76 S77 S78 S79 S80 P P2 P3 P4 General-purpose output ports used with the backlight controller or other circuit ey matrix (up to 30 keys) Note *22. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least ms, as the LC7588PT is reset by the VDET. *23. f a variable resistor is not used for display contrast fine adjustment, the pin must be connected to ground. *24. n RC oscillator operating mode, an external resistor, Rosc, and an external capacitor, Cosc, must be connected between the OSC pin and ground. When selecting the external clock operating mode, connect a current protection resistor Rg (2.2 to 22 k) between the OSC pin and the external clock output pin (external oscillator). (See the OSC Pin Peripheral Circuit section.) *25. f the function of NH pin is not used, the NH pin must be connected to the logic block power supply VDD. *26. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between k and 0 k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. *27 When applying a 5 V signal to the, CL, D, and NH pins, set the input voltage to 0 V if the logic block power supply (VDD) is off, and apply the 5 V signal to those pins after turning on the logic block power supply (VDD). 33