MODULE NO.: LPST128064A00-AB DOC.REVISION: 0.0

Transcription

1 MODULE NO: LPST128064A00-AB DOCREVISION: 00 SIGNATURE PREPARED BY Frli 17-Feb-05 APPROVED BY (R&D) APPROVED BY (Marketing) Wayne Zhao Nick Poon 18-Feb Feb-05

2 PRODUCT PREVIEW Product Part#: LPST128064A00-AB Product Name: 128x64 Area Color OLED Module Revision: 00 Date: Feb 2005 This document contains information on a new product Specifications and information herein are subject to change without notice

3 REVISION RECORD Revision Description of Revision Revision date Remark 00 Initial release 17-Feb LPST128064A00-AB i Rev: 00 Feb 2005

4 TABLE OF CONTENTS 1 Functions & features 1 2 Mechanical specifications 1 3 Block diagram 1 4 Dimensional outline 2 5 Pin description 3 6 Absolute maximum ratings 4 7 Optics & electrical characteristics 5 8 Electrical characteristics 5 9 Control and display command 9 10 Reference application circuit Quality specifications 16 LPST128064A00-AB ii Rev: 00 Feb 2005

5 1 FUNCTIONS & FEATURES 11 Format : 128*64 dots 12 Display mode : Passive Matrix 13 Display color : Area Color (Light Blue, Yellow) 14 Duty : 1/64 2 MECHANICAL SPECIFICATIONS 21 Module size : 3000mm(W)*3466mm(H) 22 Panel size : 3000mm(W)*2016mm(H) 23 Viewing area : 2502mm(W)*1386mm(H) 24 Active area : 2302mm(W)*1186mm(H) 25 Dot pitch : 018mm(W)*018mm(H) 26 Dot size : 016mm(W)*016mm(H) 27 Thickness(with polarizer) : 180mm 28 Weight : 20g 3 BLOCK DIAGRAM CS# RES# D/C R/W(WR#) E(RD#) D7~D0 VCC VCOMH IREF BS2 BS1 VDD VBREF RESE FB VDDB GDR VSS SSD1303 COM0~63 SEG0~127 OLED Panel 128 X 64 Dots Figure 1: Block diagram LPST128064A00-AB Page 1 Rev: 00 Feb 2005

6 NC VCC VCOMH IREF D7 D6 D5 D4 D3 D2 D1 D0 E/RD# R/W# D/C# RES# CS# NC BS2 BS1 VDD NC NC NC VBREF RESE FB VDDB GDR VSS NC 4 DIMENSIONAL OUTLINE Active Area 102" 128X64 Pixels 1 Specification: 1) OLED COLOR: Area color(light Blue, Yellow) 2) 1/64 Duty 3) Operating temp: -20~70 C Storage temp: -30~80 C 4) Using IC: SSD1303T6 TCP chip 5) Polarizer tape: transmissive(42%) 31 A00 First ISSUE Feb A Yellow 128X16 Blue 128X48 Detail A Scale (10:1) FIT 1 1 ±020mm mm LPST128064A00-AB FGE-OT128064A0-00 Figure 2: Dimensional outline LPST128064A00-AB Page 2 Rev: 00 Feb 2005

7 5 PIN DESCRIPTION Pin no Symbol Function 21 VDD This is the supply voltage pin to logic circuit It must be connected to the external power source 30 VSS This is the ground pin and is a reference for the logic pins It must be connected to the external ground 2 VCC Supply voltage for OLED This is the supply voltage for OLED system and it is the most positive voltage supply pin of the chip It can be supplied externally or generated internally by using internal DC/DC voltage converter 3 VCOMH This is an input pin and a capacitor should be connected between VCOMH and VSS 4 IREF This is a segment current reference pin A resistor should be connected between IREF and VSS This is a supply voltage pin for internal buffer DC/DC voltage converter It 28 VDDB must be connected to VDD when the converter is used When use external VCC, the pin should be left open 29 GDR This is an output pin to drive the gate of the external NMOS of the booster circuit When use external VCC, the pin should be left open 27 FB This is a feedback resistor input pin for the booster circuit It is used to adjust the booster output voltage VCC When use external VCC, the pin should be left open 26 RESE This is a source current pin of the external NMOS of the booster circuit When use external VCC, the pin should be left open 25 VBREF This is an internal voltage reference pin for booster circuit A stabilization capacitor should be connected to VSS When use external VCC, the pin should be left open 20, 19 BS1, BS2 These pins are for MCU selection BS1=0 and BS2=1 for 6800 parallel interface BS1=1 and BS2=1 for 8080 parallel interface BS1=0 and BS2=0 for SPI 17 CS# This pin is the chip select input Pull Low to enable the chip for MCU communication 16 RES# This pin is reset signal input Pull Low for the initialization of the chip This pin is used for Data/Command selection 15 D/C Pull Low to set the D7~D0 inputs as command to control the chip Pull High to set the D7~D0 inputs as display data This pin is MCU interface input - For 6800-series parallel interface, This pin is used as Read/Write (R/W) selection input Pull High to set Read mode provided that CS# is Low Pull Low to set Write mode provided that CS# is Low 14 R/W(WR#) - For 8080-series parallel interface, This pin is used for receiving the Write (WR#) signal Pull Low to initiate data write operation provided that CS# is Low ; Pull High to stop Write operation - For Serial peripheral interface, This pin must be connected to VSS LPST128064A00-AB Page 3 Rev: 00 Feb 2005

8 Pin no Symbol Function This pin is MCU interface input - For 6800-series parallel interface, 13 E(RD#) This pin is used as the Enable (E) signal Pull High to enable the chip to initiate Read/Write operation provided that CS# is Low Pull Low to disable the Read/Write operation - For 8080-series parallel interface, This pin is used for receiving the Read (RD#) signal Pull Low to initiate data read operation provided that CS# is Low Pull High to stop Read operation - For Serial peripheral interface, This pin must be connected to VSS 5 ~ 12 D7 ~ D0 These pins are 8-bit bi-directional data bus They should be connected to the microprocessor s data bus When serial interface mode is selected, D1 will be the serial data input and D0 will be the serial clock input 1, 18, 22, NC Reserved pins and should not be connected together 23, Table1: Pin Description 6 ABSOLUTE MAXIMUM RATINGS 61 Absolute Maximum Ratings Parameter Symbol Min Max Unit Notes Supply Voltage V DD V 1,2 Driver Supply Voltage V CC V 1,2 Operating Temperature T OP o C -- Storage Temperature T STG Table2: Absolute Maximum Ratings o C -- Note 1: All above voltages are on the basis of VSS = 00V Note 2: When this module is used beyond above absolute maximum ratings, permanent breakage of the module may occur For normal operations, it is desirable to use this module under the conditions according to Section Electrical Characteristics If this module is used beyond these conditions, malfunctioning of the module will occur and the reliability of the module may deteriorate 62 Regarding the Gradation Although this module possesses the gradation function, respective gradation levels will vary depending on the production conditions etc The temperature range where the gradation function can be guaranteed is -10 o C ~ 60 o C LPST128064A00-AB Page 4 Rev: 00 Feb 2005

9 7 OPTICS & ELECTRICAL CHARACTERISTICS Characteristics Symbol Conditions Min Typ Max Unit Brightness L br With polarizer Cd/m 2 CIE (Blue) X Without polarizer Y CIE (Yellow) X Without polarizer Y Dark Room Contrast CR > View Angle A -- > degree Table 3: Optics & electrical characteristics Note: Optical measurement is taken at 1/64 duty,100hz Frame Rate, 0xFF Contrast setting 8 ELECTRICAL CHARACTERISTICS 81 DC Characteristics Symbol Parameter Conditions Min Typ Max Unit V DD Supply Voltage for logic V V CC Operating Voltage for OLED V V IH High Level Input -- 08*V DD -- V DD V V IL Low Level Input *V DD V V OH High Level Output -- 09*V DD -- V DD V V OL Low Level Output *V DD V I DD I CC Operating Current at V DD Operating Current at V CC VDD = 28V, VCC = 90V, Frame rate = 100Hz, Contrast setting = 0xFF, 50% display area turn-on VDD = 28V, VCC = 90V, Frame rate = 100Hz, Contrast setting = 0xFF, 100% display area turn-on VDD = 28V, VCC = 90V, Frame rate = 100Hz, Contrast setting = 0xFF, 50% display area turn-on VDD = 28V, VCC = 90V, Frame rate = 100Hz, Contrast setting = 0xFF, 100% display area turn-on Table 4: DC characteristics -- TBD TBD ma -- TBD TBD ma -- TBD TBD ma -- TBD TBD ma LPST128064A00-AB Page 5 Rev: 00 Feb 2005

10 82 AC Characteristics Series MPU Parallel Interface Timing Characteristics Symbol Parameter Min Max Unit t cycle Clock cycle time ns t AS Address Setup Time 0 -- ns t AH Address Hold Time 0 -- ns t DSW Write Data Setup Time ns t DHW Write Data Hold Time ns t DHR Read Data Hold Time ns t OH Output Disable Time ns t ACC Access Time ns PW CSL Chip Select Low Pulse Width (read) ns Chip Select Low Pulse Width (write) ns PW CSH Chip Select High Pulse Width (read) ns Chip Select High Pulse Width (write) ns t R Rise time ns t F Fall time ns D/C tas tah R/W E PWCSL tcycle PWCSH CS# D0~D7(WRITE) tf tr tdsw Valid Data tdhw D0~D7(READ) tacc Valid Data tdhr toh Figure 3: Timing diagram for 6800-series MPU parallel interface LPST128064A00-AB Page 6 Rev: 00 Feb 2005

11 Series MPU Parallel Interface Timing Characteristics Symbol Parameter Min Max Unit t cycle Clock cycle time ns t AS Address Setup Time 0 -- ns t AH Address Hold Time 0 -- ns t DSW Write Data Setup Time ns t DHW Write Data Hold Time ns t DHR Read Data Hold Time ns t OH Output Disable Time ns t ACC Access Time ns PW CSL Chip Select Low Pulse Width (read) Chip Select Low Pulse Width (write) ns ns PW CSH Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) ns ns t R Rise time ns t F Fall time ns D/C tas tah WR# RD# PWCSL tcycle PWCSH CS# tr D0~D7(WRITE) tf tdsw Valid Data tdhw D0~D7(READ) tacc Valid Data tdhr toh Figure 4: Timing diagram for 8080-series MPU parallel interface LPST128064A00-AB Page 7 Rev: 00 Feb 2005

12 823 Serial Interface Timing Characteristics Symbol Parameter Min Max Unit t cycle Clock cycle time ns t AS Address Setup Time ns t AH Address Hold Time ns t CSS Chip Select Setup Time ns t CSH Chip Select Hold Time ns t DSW Write Data Setup Time ns t DHW Write Data Hold Time ns t CLKL Clock Low Time ns t CLKH Clock High Time ns t R Rise time ns t F Fall time ns D/C tas tah CS# tcss tcsh tcycle tclkl tclkh SCLK(D0) tf tdsw tr tdhw SDIN(D1) Valid Data CS# SCLK(D0) SDIN(D1) D7 D6 D5 D4 D3 D2 D1 D0 Figure 5: Timing diagram for serial interface LPST128064A00-AB Page 8 Rev: 00 Feb 2005

13 9 CONTROL AND DISPLAY COMMAND 91 Command table (D/C = 0, R/W (WR#) = 0, E(RD#) = 1) LPST128064A00-AB Page 9 Rev: 00 Feb 2005

14 LPST128064A00-AB Page 10 Rev: 00 Feb 2005

15 Note: Remark * stands for Don t Care Table 5: Command Table LPST128064A00-AB Page 11 Rev: 00 Feb 2005

16 92 Read command table (D/C = 0, R/W(WR#) = 1, E(RD#) = 1 for 6800 or E(RD#) = 0 for 8080) Note: Patterns other than that given in Command Table are prohibited to enter to the chip as a command; otherwise, unexpected result will occur Table 6: Read Command Table 10 REFERENCE APPLICATION CIRCUIT 1 NC VDD_ANALOG L1 D1 2 VCC AIC1896CE D7 D6 D5 D4 D3 D2 D1 D0 RD WR RS RESET CS VDD or VSS VDD or VSS VDD_LOGIC C1 C5 VDD SHDN SS U1 GND LX FB C4 R1 R2 C2 C3 C7 C6 Ref D7 6 D6 7 D5 8 D4 9 D VCOMH IREF D2 D1 D0 E(RD#) R/W(WR#) D/C RES# CS# NC 19 BS2 20 BS1 21 VDD 22 NC 23 NC 24 NC 25 VBREF 26 RESE 27 FB 28 VDDB 29 GDR 30 VSS 31 NC SSD x64 OLED Panel Figure 6: Reference Application Circuit (using external DC/DC voltage converter) LPST128064A00-AB Page 12 Rev: 00 Feb 2005

17 Notes: MPU interface: 8-bit 6800-series/8080-series parallel interface or Serial interface It is pin selectable by BS1 and BS series parallel interface 8080-series parallel interface Serial interface BS BS U1: AIC1896 DC/DC Converter AIC1896CE can be connected to MCU or VDD for alternative solution VCC = 123 x (R1 + R2)/R2 Below table is the component list for the application circuit Item Description SSD1303 OLED Driver IC (Solomon) U1 DC/DC Converter AIC1896 Step-up(AIC) L1 Inductor 15µH, 2A D1 Schottky Diode 20V, 1A R1 Resistor 820kΩ, 1%, 1/4W R2 Resistor 130kΩ, 1%, 1/4W Ref C1 C2 C3 C4 C5 C6 C7 Resistor 910kΩ, 1% (see remark) Capacitor 10µF, 63V, Low ESR Capacitor 10µF, 16V, Low ESR Capacitor 1µF, 16V, Low ESR Capacitor 15nF, 16V, Low ESR Capacitor 0033µF, 63V, Low ESR Capacitor 47µF, 63V, Low ESR Tantalum Capacitor 10µF~22µF, 16V Table 7: Component list for the external DC-DC voltage converter application circuit LPST128064A00-AB Page 13 Rev: 00 Feb 2005

18 VCC C1 C2 Ref VCC VCOMH IREF D7~D0 E(RD#) R/W(WR#) D/C RES# CS# VDD or VSS VDD or VSS VDD VCC D1 C9 C8 C7 R3 C6 R4 L1 Q1 R2 5~12 D7~D0 13 E(RD#) 14 R/W(WR#) 15 D/C 16 RES# 17 CS# 19 BS2 20 BS1 21 VDD 25 VBREF 26 RESE 27 FB 28 VDDB 29 GDR C5 C4 C3 30 VSS 128x64 OLED Panel SSD1303 Figure 7: Reference Application Circuit (using internal DC/DC voltage converter) Notes: MPU interface: 8-bit 6800-series/8080-series parallel interface or Serial interface It is pin selectable by BS1 and BS series parallel interface 8080-series parallel interface Serial interface BS BS L1, D1, Q1 and C4 should be grouped closed together on PCB layout R2, R3, C5 and C6 should be grouped closed together on PCB layout The VCC output voltage level is adjusted by R2 and R3, the formula is: VCC = 12 x (R2+R3)/R3 The value of (R2+R3) should be between 500k to 1M ohm LPST128064A00-AB Page 14 Rev: 00 Feb 2005

19 Below table is the component list for the application circuit Item Description SSD1303 OLED Driver IC (Solomon) Q1 MOSFET N-FET with low R DS (on) and low Vth voltage, eg, MGSF1N02Lt1 (On Semi) L1 Inductor 10µH, 1A D1 Schottky diode 1A, 25V, eg, 1N5822, BAT54 (Philips Semi) Ref Resistor 1%, 1/2W (see remark) R1 Resistor 12Ω, 1%, 1/2W R2, R3 Resistor 1%, 1/10W C1 Capacitor 47µF, 16V C2 Tantalum Capacitor 10µF~22µF, 16V C3 Capacitor 01 ~ 1µF, 16V C4 Capacitor 1 ~ 10µF, 16V C5 Capacitor 1µF, 16V C6 Capacitor 10nF, 16V C7 Capacitor 15nF, 16V C8 Capacitor 68µF, 25V, Low ESR C9 Capacitor 1µF, 16V Table 8: Component list for the internal DC-DC voltage converter application circuit Remark: Ref = (Voltage at IREF pin VSS)/I REF ; Voltage at I REF pin = VCC - VDD For example, VDD = 30V, VCC = 12V, I REF = 10µA Ref = (12-3)/10-6 = about 910kΩ LPST128064A00-AB Page 15 Rev: 00 Feb 2005

20 11 QUALITY SPECIFICATIONS 111 Inspection Method: 1111 Applicable Standard MIL-STD-105E, Level II, Normal Inspection, single sampling 1112 AQL Partition AQL Definition Major 065 Defects may lead to the failure of display function or the failure of passing the reliability criteria Minor 10 Defects do not affect all of the display functions, and have no impact to the reliability 1113 Inspection Condition Test and measurement were conducted under the following conditions: Temperature: 23±5 Humidity: 55±15%RH Distance between the panel and eyes of the inspector: 30cm 112 Inspection Criterion Check Item Classification Criteria Non operation/display Flicker Miss line or pixel major Not Allowable Wrong display Cross talk * W 005 Ignore Scratches, fiber ** minor W 01, L 2 n 3 2 < L n = 0 Ф 01 Ignore Dirt, Black spot, white spot, 01 < Ф 02 n 3 Greasy dirt, Foreign material, Dent, Bubbles ** 02 < Ф 025 n < Ф n 0 Fingerprint, Flow mark minor Not allowable * In displays which manifests itself has the other shadowing, ghosting or streaking ** Distance between any 2 defects should over 10mm *** Definition of W & L & Ф (unit: mm): Ф=(a+b)/2 L b: Minor Axis W a: Major Axis LPST128064A00-AB Page 16 Rev: 00 Feb 2005

21 Visual check in non-active area Check Item Classification Criteria X 1/6 Panel Length Y 1 Z T X Z T Panel General Chipping Major Y X Z Y Any crack is not allowable Panel Crack minor Terminal cable: twist, Scar, Split, Scratch Minor Not Allowable LPST128064A00-AB Page 17 Rev: 00 Feb 2005

22 113 Reliability 1131 Contents of Reliability Tests Item Condition Criteria High Temperature Operation 70 C, 240 hrs Low Temperature Operation -20 C, 240 hrs High Temperature Storage 80 C, 240 hrs Low Temperature Storage -30 C, 240 hrs High Temperature /Humidity Storage 60 C, 90%RH, 240 hrs Thermal Shock -30 C 80 C, 10 cycles 30 mins dwell No such changes as to obstruct image & function * The samples used for above tests do not include polarizer * No moisture condensation is observed during tests 1132 Lifetime End of lifetime is specified as 50% of initial brightness An average operating lifetime of more than 10,000 hrs at room temperature is approached by C operating 1133 Failure Check Standard After the completion of the described reliability test, the samples were left room temperature for 2 hrs prior to conducting the failure teat at 23±5 ; 55±15% RH LPST128064A00-AB Page 18 Rev: 00 Feb 2005

23 Lite Array reserves the right to make changes without further notice to any products described herein Unless specifically agreed to by Lite Array in writing in a particular instance, Lite Array makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor does Lite Array assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters, including Typicals must be validated for each customer application by customer s technical experts Unless specifically agreed to by Lite Array in writing in a particular instance, Lite Array does not convey any license under its patent rights nor the rights of others Lite Array products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Lite Array product could create a situation where personal injury or death may occur Should Buyer purchase or use Lite Array products for any such unintended or unauthorized application, Buyer shall indemnify and hold Lite Array and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Lite Array was negligent regarding the design or manufacture of the part The purchase of a Lite Array product by a buyer shall, for such product, be deemed an acceptance by the buyer of the terms set forth above LPST128064A00-AB Page 19 Rev: 00 Feb 2005

24 P x32 Yellow/Blue Area Color Application Notes RITDISPLAY CORPORATION REV X /9/28 Design Dept

25 FEATURE - 128x32 dot matrix yellow/blue color passive OLED module - Driver IC is SSD Embedded display buffer - Logic voltage supply: VDD=24~35V - High voltage supply: VCC=10V - 8-bit 6800/8080-series Parallel interface - Vertical/Horizontal scrolling function - Internal oscillator circuit Programmable frame frequency and multiplexing Ratio FUNCTION BLOCK DIAGRAM TAB VCC VDD VCOMH IR EF Row 32~62 D0~D7 SSD1303 D/C# Colum n 0~ X32 RD# W R# CS# Row 33~63 RES# BS1 BS2 VSS O LED Panel R itdisplay 128X 32 O LE D m odule RITDISPLAY CORPORATION REV X /9/28 Design Dept

26 APPLICATION CIRCUIT 128x32 OLED module external application circuit Recommended components C1:47uF/16V, C2:47uF/16V, C3:01uF/16V, Resistor: 2M ohm, 1% This circuit is designed for 8080 interface RITDISPLAY CORPORATION REV X /9/28 Design Dept

27 DC-DC CIRCUIT The R1 & R2 value should be adjust by DC-DC IC vendor RITDISPLAY CORPORATION REV X /9/28 Design Dept

28 Pin Assignments PIN NAME PIN NO TYPE DESCRIPTION NC 1 - No connection VSS 2 I This is a ground pin Test Reserved pin; No connection and left float Test Reserved pin; No connection and left float Test Reserved pin; No connection and left float Test Reserved pin; No connection and left float Test Reserved pin; No connection and left float NC 8 - No connection NC 9 - No connection NC 10 - No connection VDD 11 I Voltage power supply for logic BS1 12 I MCU interface selection input BS2 13 I MCU interface selection input NC 14 - No connection CS# 15 I This is a chip select control pin RES# 16 I Hardware reset signal D/C# 17 I This is a Data/Command control pin WR# 18 I This pin is used to receive the Write Data signal RD# 19 I This pin is used to receive the Read Data signal D0 20 I/O This pin is bi-direction data signal D1 21 I/O This pin is bi-direction data signal D2 22 I/O This pin is bi-direction data signal D3 23 I/O This pin is bi-direction data signal D4 24 I/O This pin is bi-direction data signal D5 25 I/O This pin is bi-direction data signal D6 26 I/O This pin is bi-direction data signal D7 27 I/O This pin is bi-direction data signal IREF 28 I A resistor should be connected between this pin and VSS VCOMH 29 I A capacitor should be connect between this pin and VSS VCC 30 I Positive high voltage power supply NC 31 - No connection RITDISPLAY CORPORATION REV X /9/28 Design Dept

29 Application Software /* 128 x 32 OLED Driver Demo program by Steve */ void init_oled() { comm_out2(0xae); comm_out2(0xad); comm_out2(0x8a); comm_out2(0xa8); comm_out2(0x1f); comm_out2(0xd3); comm_out2(0x20); comm_out2(0x40); comm_out2(0xa1); comm_out2(0xc8); comm_out2(0xa6); comm_out2(0xa4); comm_out2(0x81); comm_out2(0x3f); comm_out2(0xd5); comm_out2(0x61); comm_out2(0xd8); comm_out2(0x00); comm_out2(0xaf); //Display off //Internal DC-DC off // Second byte //MUX Ratio //32 duty //Display offset //Second byte //Start line //Segment remap //COM remap //Set normal/inverse display (0xA6:Normal display) //Set entire display on/off (0xA4:Normal display) //Contrast setting //Second byte //Frame rate // 85 Hz //Mode setting //Mono mode //Display on } void write_data() { int j, i; for(i=0;i<4;i++) { comm_out2(0xb0+i); comm_out2(0x04); comm_out2(0x10); for(j=0;j<128;j++) data_out2(0xff); //set page // Lower col address // Higher col address //out data } } RITDISPLAY CORPORATION REV X /9/28 Design Dept

30 Power Up/Down Sequence To protect OLED panel and extend the panel lifetime, the driver IC power up/down routine should include a delay period between high voltage and low voltage power sources turn on/off Power up Sequence: 1 Power up VDD 2 Hardware RESET 3 Send display off command 4 Power up VCC 5 Delay 100ms (when VCC is stable) 6 Send Display on command Power down Sequence: 1 Send Display off command 2 Power down VCC 3 Delay 100ms (When VCC is reach 0 and panel is completely discharges) 4 Power down VDD On VDD On VCC Display On Display Off Off VCC Off VDD VCC VCC VDD VDD GND GND RITDISPLAY CORPORATION REV X /9/28 Design Dept

31 Graphic Display Data RAM Address Map RITDISPLAY CORPORATION REV X /9/28 Design Dept

32 Thank You RITDISPLAY CORPORATION REV X /9/28 Design Dept

33 SOLOMON SYSTECH SEMICONDUCTOR TECHNICAL DATA SSD1303 Advance Information 132 x 64 Dot Matrix OLED/PLED Segment/Common Driver with Controller This document contains information on a new product Specifications and information herein are subject to change without notice SSD1303 Rev 17 P 1/56 May 2005 Copyright 2005 Solomon Systech Limited

34 TABLE OF CONTENTS 1 GENERAL INFORMATION 5 2 FEATURES 5 3 ORDERING INFORMATION 6 4 BLOCK DIAGRAM 7 5 DIE PAD FLOOR PLAN8 6 PIN DESCRIPTION 12 7 FUNCTIONAL BLOCK DESCRIPTIONS15 71 OSCILLATOR CIRCUIT AND DISPLAY TIME GENERATOR RESET CIRCUIT COMMAND DECODER AND COMMAND INTERFACE MPU PARALLEL 6800-SERIES INTERFACE MPU PARALLEL 8080-SERIES INTERFACE MPU SERIAL INTERFACE17 77 GRAPHIC DISPLAY DATA RAM (GDDRAM) CURRENT CONTROL AND VOLTAGE CONTROL17 79 SEGMENT DRIVERS / COMMON DRIVERS AREA COLOUR DECODER DC-DC VOLTAGE CONVERTER 19 8 COMMAND TABLE DATA READ / WRITE24 9 COMMAND DESCRIPTIONS25 10 MAXIMUM RATINGS DC CHARACTERISTICS AC CHARACTERISTICS APPLICATION EXAMPLE SSD1303T3R1 PACKAGE DETAILS39 SSD1303T3R1 PIN ASSIGNMENT39 15 SSD1303T6R1 PACKAGE DETAILS43 SSD1303T6R1 PIN ASSIGNMENT43 SSD1303T6R1 TAB PACKAGE DIMENSIONS SSD1303T8R1 PACKAGE DETAILS47 SSD1303T8R1 PIN ASSIGNMENT47 SSD1303T8R1 TAB PACKAGE DIMENSIONS SSD1303T9R1 PACKAGE DETAILS51 SSD1303T9R1 PIN ASSIGNMENT51 SSD1303T9R1 TAB PACKAGE DIMENSIONS 53 Solomon Systech May 2005 P 2/56 Rev 17 SSD1303

35 18 SSD1303Z PACKAGE DETAILS 55 SSD1303 Rev 17 P 3/56 May 2005 Solomon Systech

36 TABLE OF FIGURES Figure 1 - Block Diagram7 Figure 2 - SSD1303Z Pin Assignment 8 Figure 3 - SSD1303Z Alignment mark dimensions11 Figure 4 - Oscillator Circuit15 Figure 5 - Display data read back procedure - insertion of dummy read16 Figure 6 Display data write procedure in SPI mode17 Figure 7 - DC-DC voltage converter circuit 19 Figure 8 - Horizontal scroll direction25 Figure 9 - Segment current vs Contrast setting 26 Figure series MPU parallel interface characteristics 35 Figure series MPU parallel interface characteristics 36 Figure 12 - Serial interface characteristics37 Figure 13 - Application Example (Block Diagram of SSD1303T3)38 Figure 14 - SSD1303T3R1 pin assignment (Copper view, Normal TAB design) 39 Figure 15 - SSD1303T6R1 pin assignment (Copper view)43 Figure 16 - SSD1303T9R1 pin assignment (Copper view)51 LIST OF TABLES Table 1 - Ordering Information 6 Table 2 - SSD1303Z Die Pad Coordinates 9 Table 3 - Passive component selection: 20 Table 4 - Command table21 Table 5 - Read command table23 Table 6 - Address increment table (Automatic)24 Table 7 - Maximum Ratings 32 Table 8 - DC Characteristics 33 Table 9 - AC Characteristics 34 Table Series MPU Parallel Interface Timing Characteristics35 Table Series MPU Parallel Interface Timing Characteristics36 Table 12 - Serial Interface Timing Characteristics 37 Table 13 - SSD1303T3R1 pin assignment40 Table 14 - SSD1303T6R1 pin assignment44 Table 15 - SSD1303T8R1 pin assignment48 Table 16 - SSD1303T9R1 pin assignment52 Solomon Systech May 2005 P 4/56 Rev 17 SSD1303

37 1 GENERAL INFORMATION The SSD1303 is a single-chip CMOS OLED/PLED driver with controller for organic/polymer light emitting diode dot-matrix graphic display system It consists of 132 segments, 64 commons that can support a maximum display resolution of 132x64 Besides, there are 4-colour selections to support monochrome or area colour OLED/PLED This IC is designed for Common Cathode type OLED panel The SSD1303 embeds with contrast control, display RAM and oscillator, which reduces the number of external components and power consumption It is suitable for many compact portable applications, such as mobile phone sub-display, calculator and MP3 player, etc 2 FEATURES - Support maximum 132 x 64 dot matrix panel - Area colour support with 4 Colour Selection and 64 steps per colour - Logic voltage supply: V DD = 24V - 35V - High voltage supply: V CC = 70V - 160V - Maximum segment output current: 320uA - Maximum common sink current: 45mA - Embedded 132 x 64 bit SRAM display buffer step Contrast Control on monochrome passive OLED panel - On-Chip Oscillator - Programmable Frame Frequency and Multiplexing Ratio - 8-bit 6800-series Parallel Interface, 8-bit 8080-series Parallel Interface, Serial Peripheral Interface - Row Re-mapping and Column Re-mapping - Vertical Scrolling - Automatic horizontal scrolling function - Low power consumption - Wide range of operating temperatures: -40 to 90 C SSD1303 Rev 17 P 5/56 May 2005 Solomon Systech

38 3 ORDERING INFORMATION Table 1 - Ordering Information Ordering Part Number SEG COM Package Form Reference Remark SSD1303Z Gold Bump Die Page 8 SSD1303T3R TAB Page 39 SSD1303T6R TAB Page 43 SSD1303T8R TAB Page 47 SSD1303T9R TAB Page 51 Die size: 922mm x 155mm Pad pitch: COM 518µm SEG 522µm 35mm film 4 sprocket hole Folding TAB 80 / 68 / SPI interface Output lead pitch mm 35mm film 4 sprocket hole Folding TAB 80 / 68 / SPI interface Output lead pitch mm film 4 sprocket hole Folding TAB 80 / 68 / SPI interface Output lead pitch mm 35mm film 4 sprocket hole Folding TAB 80 / 68 / SPI interface Output lead pitch mm Solomon Systech May 2005 P 6/56 Rev 17 SSD1303

39 4 BLOCK DIAGRAM RES# CS# D/C E (RD#) R/W (WR#) BS2 BS1 BS0 D7 D6 D5 D4 D3 D2 D1 D0 VDD VSS MCU Interface Command Decoder Oscillator Display Timing Generator GDDRAM Voltage Control Current Control Area Colour Decorder Common Drivers (even) Segment Drivers Common Drivers(odd) COM63 COM61 COM3 COM1 SEG131 SEG130 SEG1 SEG0 COM0 COM2 COM60 COM62 CL CLS VDDB VSSB GDR RESE FB VBREF VCC VCOMH VREF IREF VCL VSL Figure 1 - Block Diagram SSD1303 Rev 17 P 7/56 May 2005 Solomon Systech

40 5 DIE PAD FLOOR PLAN Figure 2 - SSD1303Z Pin Assignment DUMMY DUMMY COM30 COM28 COM26 COM24 COM6 COM4 COM2 COM0 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 COM1 COM3 COM5 COM7 COM25 COM27 COM29 COM31 DUMMY DUMMY DUMMY (x2) COM32 COM34 COM60 COM62 VSS (x3) VCL (x3) VSS (x2) VSL (x3) VDD VCC (x2) VREF VCOMH (x2) IREF ICAS VDD CLS M/S VSS D7 D6 D5 D4 D3 D2 D1 D0 VDD E/RD R/W VSS D/C RES# CS# VSS DOF# CL M VSS BS2 VDD BS1 VSS BS0 VDD GPIO1 GPIO0 VCC VSS BGGND SENSE VBREF RESE FB VDD (x2) VDDB (x2) GDR (x2) VSSB (x2) VSS TR0 TR1 TR2 TR3 TR4 TR5 TR6 TR7 TR8 VCOMH (x2) VCC (x2) VDD VSL (x3) VSSB (x2) VSS (x2) VCL (x3) VSS (x3) COM63 COM61 COM35 COM33 DUMMY (x2) Die size Die height SSD1303 Bump height Bump size Pad 1-18, Pad Alignment mark Y Pad 1,2,3,? >130 Gold Bumps face up X 922mm x 155mm 475 +/- 25um Nominal 18um 34um x 84um 54um x 84um T shape (-31329, 795) 75um x 75um + shape (31489, 795) 75um x 75um Circle (34339, -2746) R375um, inner 18um Circle (-34339, -2746) R375um, inner 18um PAD 1 Solomon Systech May 2005 P 8/56 Rev 17 SSD1303

41 Table 2 - SSD1303Z Die Pad Coordinates Pad no Pad Name X-pos Y-pos Pad no Pad Name X-pos Y-pos Pad no Pad Name X-pos Y-pos 1 NC VCC COM NC GPIO COM COM GPIO COM COM VDD COM COM BS COM COM VSS COM COM BS COM COM VDD COM COM BS NC COM VSS NC COM M NC COM CL NC COM DOF# COM COM VSS COM COM CS# COM COM RES# COM COM D/C COM COM VSS COM VSS R/W COM VSS E/RD COM VSS VDD COM VCL D COM VCL D COM VCL D COM VSS D COM VSS D COM VSSB D COM VSSB D COM VSL D SEG VSL VSS SEG VSL M/S SEG VDD CLS SEG VCC VDD SEG VCC ICAS SEG VCOMH IREF SEG VCOMH VCOMH SEG TR VCOMH SEG TR VREF SEG TR VCC SEG TR VCC SEG TR VDD SEG TR VSL SEG TR VSL SEG TR VSL SEG TR VSS SEG VSS VSS SEG VSSB VCL SEG VSSB VCL SEG GDR VCL SEG GDR VSS SEG VDDB VSS SEG VDDB VSS SEG VDD COM SEG VDD COM SEG FB COM SEG RESE COM SEG VBREF COM SEG SENSE COM SEG BGGND COM SEG VSS COM SEG SSD1303 Rev 17 P 9/56 May 2005 Solomon Systech

42 Pad no Pad Name X-pos Y-pos Pad no Pad Name X-pos Y-pos 181 SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG COM SEG COM SEG COM SEG COM SEG COM SEG COM SEG COM SEG COM SEG COM SEG COM SEG COM SEG COM SEG COM SEG COM SEG COM SEG COM SEG NC SEG NC SEG SEG Solomon Systech May 2005 P 10/56 Rev 17 SSD1303

43 Figure 3 - SSD1303Z Alignment mark dimensions T shape + shape Circle Unit in um SSD1303 Rev 17 P 11/56 May 2005 Solomon Systech

44 6 PIN DESCRIPTION CL This pin is the system clock input When internal clock is enabled, this pin should be left open The internal clock is output from this pin When internal oscillator is disabled, this pin receives display clock signal from external clock source CLS This is the internal clock enable pin When it is pulled HIGH, internal clock is enabled When it is pulled LOW, the internal clock is disabled, an external clock source must be connected to the CL pin for normal operation BS0, BS1, BS2 These are MCU interface input selection pins See the following table for selecting different interfaces: 6800-parallel interface 8080-parallel interface Serial interface BS BS BS CS# This pin is the chip select input The chip is enabled for MCU communication only when CS# had been pulled low RES# This is a reset signal input pin When it is pulled LOW, initialization of the chip is executed D/C This is the Data/Command control pin When it is pulled HIGH, the input at D 7 -D 0 is treated as display data When it is pulled LOW, the input at D 7 -D 0 is transferred to the command registers For detail relationship to MCU interface signals, please refer to the Timing Characteristics Diagrams R/W (WR#) This is a MCU interface input pin When 6800-series Parallel Interface mode is selected, this pin is used as Read/Write (R/W) selection input Pull this pin to HIGH for read mode and pull it to LOW for write mode When 8080-series Parallel Interface mode is selected, this pin is used as Write (WR#) selection input Pull this pin to LOW for write mode Data write operation is initiated when this pin is pulled LOW and the CS# is pulled LOW E (RD#) This is a MCU interface input pin When 6800-series Parallel Interface is selected, this pin is used as Enable (E) signal Read/Write operation is initiated when this pin is pulled HIGH and the CS# pin is pulled LOW When 8080-series Parallel Interface is selected, this pin is used to receive the Read Data (RD#) signal Data read operation is initiated when this pin is pulled LOW and CS# pin is pulled LOW D 7 -D 0 These are 8-bit bi-directional data bus to be connected to the microprocessor s data bus When serial interface mode is selected, D 1 will be the serial data input, SDIN, D 0 will be the serial clock input, SCLK, and D 2 should be left opened Solomon Systech May 2005 P 12/56 Rev 17 SSD1303

45 VDD This is a voltage supply pin It must be connected to external source VSS This is a ground pin It also acts as a reference for the logic pins and the OLED driving voltages It must be connected to external ground BGGND This is a ground pin for analog circuits It must be connected to external ground VCC This is the most positive voltage supply pin of the chip It should be supplied externally VREF This is a voltage reference pin for pre-charge voltage in driving OLED device Voltage should be set to match with the OLED driving voltage in current drive phase It can either be supplied externally or by connecting to VCC IREF This is a segment current reference pin A resistor should be connected between this pin and V SS Set the current at 10uA VCOMH This is an input pin for the voltage output high level for COM signals A capacitor should be connected between this pin and VSS VDDB This is a power supply pin for the internal buffer of the DC-DC voltage converter It must be connected to V DD when the converter is used VSSB This is a ground pin for the internal buffer of the DC-DC voltage converter It must be connected to V SS when the converter is used GDR This is an output pin drives the gate of the external NMOS of the booster circuit RESE This is a source current pin of the external NMOS of the booster circuit VB REF This is an internal voltage reference pin for booster circuit A stabilization capacitor, typ 1uF, should be connected to Vss FB This is a feedback resistor input pin for the booster circuit It is used to adjust the booster output voltage level, Vcc COM0-COM63 These are pins provided the Common switch signals to the OLED panel They are in high impedance state when display is OFF SSD1303 Rev 17 P 13/56 May 2005 Solomon Systech

46 SEG0-SEG131 These are pins provided the Segment switch signals to the OLED panal They are in high impedance stage when display is OFF TR0-TR8, GPIO0, GPIO1, ICAS, M and DOF# These are reserved pins No connection necessary and should be left open individually VSL This is a segment voltage reference pin This pin should be connected to VSS externally VCL This is a common voltage reference pin This pin should be connected to VSS externally M/S This pin must be connected to VDD to enable the chip NC Dummy pad Do not group or short NC pins together Solomon Systech May 2005 P 14/56 Rev 17 SSD1303

47 7 FUNCTIONAL BLOCK DESCRIPTIONS 71 Oscillator Circuit and Display Time Generator Internal Oscillator CL M U X CLK Divider DCLK Internal Display Clock Figure 4 - Oscillator Circuit This module is an On-Chip low power RC oscillator circuitry (Figure 4) The oscillator generates the clock for the Display Timing Generator 72 Reset Circuit When RES# pin is pulled LOW, the chip is initialized with the following status: 1 Display is OFF x 64 Display Mode 3 Normal segment and display data column address and row address mapping (SEG0 is mapped to column address 00H and COM0 is mapped to row address 00H) 4 Shift register data clear in serial interface 5 Display start line is set at display RAM address 0 6 Column address counter is set at 0 7 Normal scan direction of the COM outputs 8 Contrast control register is set at 80H 9 DC/DC enable 73 Command Decoder and Command Interface This module determines whether the input data is interpreted as data or command When the D/C# pin is pulled HIGH, the inputs at D 7 -D 0 are interpreted as data and be written to Graphic Display Data RAM (GDDRAM) When it is pulled LOW, the inputs at D 7 -D 0 are interpreted as command, they will be decoded and be written to the corresponding command registers SSD1303 Rev 17 P 15/56 May 2005 Solomon Systech

48 74 MPU Parallel 6800-series Interface The parallel interface consists of 8 bi-directional data pins (D 7 -D 0 ), R/W (WR#), E (RD#), D/C, CS# When the R/W (WR#) pin is pulled HIGH, Read operation from the Graphic Display Data RAM (GDDRAM) or the status register occurs When the R/W (WR#) pin is pulled LOW, Write operation to Display Data RAM or Internal Command Registers occurs, depending on the status of D/C input The E (RD#) input serves as data latch signal (clock) when HIGH provided that CS# is LOW Refer to Parallel Interface Timing Diagram of 6800-series microprocessors In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing is internally performed, which requires the insertion of a dummy read before the first actual display data read This is shown in Figure 5 below R/W# (W/R#) E (RD#) Data bus N n n+1 n+2 Write column address Dummy read Data read1 Data read2 Data read3 Figure 5 - Display data read back procedure - insertion of dummy read 75 MPU Parallel 8080-series Interface The parallel interface consists of 8 bi-directional data pins (D 7 -D 0 ), R/W (WR#), E (RD#), D/C, CS# The E (RD#) input serves as data read latch signal (clock) when it is LOW provided that CS# is LOW Display data or status register read is controlled by D/C signal R/W (WR#) input serves as data write latch signal (clock) when it is HIGH and provided that CS# is LOW Display data or command register write is controlled by D/C Refer to Parallel Interface Timing Diagram of 8080-series microprocessor Similar to 6800-series interface, a dummy read is also required before the first actual display data read Solomon Systech May 2005 P 16/56 Rev 17 SSD1303

49 76 MPU Serial Interface The serial interface consists of serial clock SCLK, serial data SDIN, D/C#, CS# In SPI mode, D0 acts as SCLK, D1 acts as SDIN For the unused data pins, D2 should be left open D3 to D7, E and R/W pins can be connected to external ground SDIN is shifted into an 8-bit shift register on every rising edge of SCLK in the order of D 7, D 6, D 0 D/C# is sampled on every eighth clock and the data byte in the shift register is written to the Display Data RAM or command register in the same clock During data writing, an additional NOP command should be inserted before the CS# goes high (Refer to Figure 6 Figure 6 Display data write procedure in SPI mode CS# D/C SDIN/ SCLK DB1 DB2 DBn NOP COMMAND SCLK(D0) SDIN(D1) D7 D6 D5 D4 D3 D2 D1 D0 77 Graphic Display Data RAM (GDDRAM) The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed The size of the RAM is 132 x 64 bits For mechanical flexibility, re-mapping on both Segment and Common outputs can be selected by software For vertical scrolling of the display, an internal register storing display start line can be set to control the portion of the RAM data to be mapped to the display 78 Current Control and Voltage Control This block is used to derive the incoming power sources into different levels of internal use voltage and current VCC and VDD are external power supplies VREF is reference voltage, which is used to derive the driving voltage for segments and commons IREF is a reference current source for segment current drivers SSD1303 Rev 17 P 17/56 May 2005 Solomon Systech

50 79 Segment Drivers / Common Drivers Segment drivers deliver 132 current sources to drive OLED panel The driving current can be adjusted from 0 to 300uA with 256 steps Common drivers generate voltage scanning pulses 710 Area Colour Decoder Page 0 and Page 1 of the display are divided into 32 banks Bank16 and Bank32 comprise of a display area of 12 x 8 pixels Other banks (0~15 & 17~31) have matrices of 8 x 8 pixels Each bank can be programmed to any one of the four colours (colour A, B, C, D) Detailed operation can be referred to the Command Table Page 0, bank 1 Page 0, bank 16 Page 1, bank 17 Page 1, bank 32 Bank 0 (background) Page 2 Page 7 Solomon Systech May 2005 P 18/56 Rev 17 SSD1303

51 711 DC-DC Voltage Converter It is a switching voltage generator circuit, designed for handheld applications In SSD1303, internal DC-DC voltage converter accompanying with an external application circuit (shown in below figure) can generate a high voltage supply V CC from a low voltage supply input V DD V CC is the voltage supply to the OLED driver block Below application circuit is an example for the input voltage of 3V VDD to generate V CC of ~ 20mA application Figure 7 - DC-DC voltage converter circuit L1 VDD + D1 VCC C5 AGND Q1 + C1 + C6 VDDB VBREF VSSB GDR RESE FB R3 R1 + C7 + C2 + C3 AGND + C4 R2 AGND DGND Remark: 1 VSSB is tied to VSS on SSD1303T3 package 2 L1, D1, Q1, C5 should be grouped closed together on PCB layout 3 R1, R2, C1, C4 should be grouped closed together on PCB layout 4 The VCC output voltage level can be adjusted by R1and R2, the reference formula is: VCC = 12 x (R1+R2) / R2 The value of (R1+R2) should be between 500k to 1M Ohm SSD1303 Rev 17 P 19/56 May 2005 Solomon Systech

52 Table 3 - Passive component selection: Components Typical Value Remark L1 Inductor, 10µH 1A D1 Schottky diode 1A, 25V eg 1N5822, BAT54 [Philips Semiconductors] Q1 MOSFET N-FET with low R DS (on) and low Vth voltage eg MGSF1N02LT1 [ON SEMI] R1, R2 Resistor 1%,1/10W R3 Resistor, 12Ω 1%, 1/2W C1 Capacitor, 1µF 16V C2 Capacitor, 68µF Low ESR, 25V C3 Capacitor, 1µF 16V C4 Capacitor, 10nF 16V C5 Capacitor, 1 ~ 10 µf 16V C6 Capacitor, 01 ~ 1µF 16V C7 Capacitor, 15nF 16V Solomon Systech May 2005 P 20/56 Rev 17 SSD1303

53 8 COMMAND TABLE Table 4 - Command table (D/C =0, R/W (WR#)=0, E (RD#)=1) Note: commands marked with ** are compatible to SSD1301 D/C Hex D7 D6 D5 D4 D3 D2 D1 D0 Command Description 0 00~0F X 3 X 2 X 1 X 0 Set Lower Column Address ** Set the lower nibble of the column address register using X 3X 2X 1X 0 as data bits The initial display line register is reset to 0000b after POR 0 10~1F X 3 X 2 X 1 X 0 Set Higher Column Address ** Set the higher nibble of the column address register using X 3X 2X 1X 0 as data bits The initial display line register is reset to 0000b after POR Horizontal scroll setup A[2:0] Set the number of column scroll per step 0 A[2:0] * * * * * A 2 A 1 A 0 Valid value: 001b, 010b, 011b, 100b 0 B[2:0] * * * * * B 2 B 1 B 0 B[2:0] Define start page address 0 C[1:0] * * * * * * C 1 C 0 C[1:0] Set time interval between each scroll step in terms of frame frequency 0 D[2:0] * * * * * D 2 D 1 D 0 0 2F b 12 frame 01b 64 frames 10b 128 frames 11b 256 frames D[2:0] Define end page address Set the value of D[2:0] larger or equal to B[2:0] Activate horizontal scroll Start horizontal scrolling 0 2E Deactivate horizontal scroll Stop horizontal scrolling F 0 1 X 5 X 4 X 3 X 2 X 1 X 0 Set Display Start Line Set display TAM display start line register from 0-63 using X 5X 3X 2X 1X A[7:0] A 7 A 6 A 5 A 4 A 3 A 2 A 1 A A[7:0] A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 Set Contrast Control Register ** Brightness for color banks Display start line register is reset to during POR Double byte command to select 1 out of 256 contrast steps Contrast increases as the value increases (POR = 80h) Double byte command to select 1 out of 256 brightness steps Brightness increases as the value increases (POR = 80h) Set Look Up Table (LUT) for area colour Set current drive pulse width of Bank 0, Colour A, B and C 0 X[5:0] * * X 5 X 4 X 3 X 2 X 1 X 0 Bank 0: X[5:0] = 0 63; for pulse width set to 1 ~ 64 clocks (POR = b) 0 A[5:0] * * A 5 A 4 A 3 A 2 A 1 A 0 Colour A: A[5:0] same as above (POR = b) 0 B[5:0] * * B 5 B 4 B 3 B 2 B 1 B 0 Colour B: B[5:0] same as above (POR = b) 0 C[5:0] * * C 5 C 4 C 3 C 2 C 1 C 0 Colour C: C[5:0] same as above (POR = b) Note: colour D pulse width is fixed at 64 clocks pulse SSD1303 Rev 17 P 21/56 May 2005 Solomon Systech