EFM-03 Hardware Reference (Hardware Revision: Rev. A)

Transcription

1 EFM0 Hardware Reference (Hardware Revision: Rev. A) Target applications Image processing Video capture Smart cameras Highspeed FPGA coprocessor Custom test equipment UG0 (v.0) August, 0

2 Features Features USB.0 SuperSpeed interface through versatile Cypress TM EZFX controller Up to 0 MByte/s sustained data rate Industrial grade Series XilinxTM FPGA XCA00TFBGI MByte QuadSPI configuration/data memory GByte DDRL,.G Byte/s bandwidth USB.0 Type B connector for highest reliability USB buspowered, no external power supply necessary Optional selfpowered mode available Single V power supply, all necessary power supplies generated onboard by high performance dc/dc converters Mbit I²C EEPROM for FX configuration data I²C interface available on expansion connector to increase available FX configuration memory for standalone applications Two FX GPIO on expansion connector singleended ( differential) IOs on highquality highspeed Samtec TM connectors (QSE000), including several clock capable IO Independent power supply option for selected FPGA banks Two GTP quad columns available on highquality highspeed Samtec TM connector (QSE000), including TX, RX and CLK pairs High performance 00 MHz LVDS clock oscillator FPGA configuration from SPI memory, JTAG or USB 0 MHz EMCCLK clock oscillator for highest FPGA configuration speeds from flash One user, three status leds USB.0 UART (FTDI FT0X) on USB.0 minib connector for debugging JTAG for FPGA and FX controller available on expansion connectors Small sized PCB only measures. mm x. mm Pinout and connector positioning compatible to EFM0/B Additional space on main boards might be required due to additional GTP quad and USB.0 minib connectors on EFM0. UG0 (v.0) August, 0

3 EFM0 block diagram EFM0 block diagram IO expansion connectors USB.0 SuperSpeed connector Cypress FX USB.0 MiniB connector USB UART controller FPGA Artix Flash memory Mb DDRLSDRAM Gb GTP Quad expansion connector Figure : EFM0 functional block diagram UG0 (v.0) August, 0

4 Specification Specification Parameter Min. Dimensions (B x W) Units mm Maximum part height on top side besides USB Type B connector. mm Maximum part height on bottom side.0 mm Operating temperature range Max.. x. Module stacking height Typ mm C Depends on mating QTE connector height. Please refer to chapter Digital IO expansion connectors and the SamtecTM website for details. Natural convection cooling. FPGA configured with efm0_wrapper design, USB.0 transmission to onboard Gbyte DDRL memory at maximum speed. Depending on the actual power requirements of the user fpga design, heatsink and/or forced cooling might be required. UG0 (v.0) August, 0

5 FPGA density FPGA density Offtheshelf EFM0 comes with the XilinxTM Artix FPGA XCA00TFBGI. See the following table for some details on this FPGA. For more detailed information please consult XilinxTM Series overview ds0 and Artix FPGAs data sheet ds. Feature XCA00TFBGI Logic Cells 0 Slices 0 Distributed RAM (Kbit) DSPE Slices 0 Block RAM (Kbit) 0 Clock Management Tiles 0 Speed Grade Temperatur Range Industrial (I): 0 to +00 C Bitstream Length (bit) UG0 (v.0) August, 0

6 FPGA Configuration FPGA Configuration The FPGA on EFM0 modules can be loaded with a valid configuration file in one of several ways. SPI Flash The onboard QuadSPI serial flash device Micron NQA is the default source for configuration bitstreams at startup. At least two configuration files can be stored inside the Mbyte flash device and MultiBoot is supported. To store an appropriate configuration file in flash, several ways exist. Loading SPI Flash via USB The easiest way to write configuration data into the onboard SPI flash is to use CESYS UDK Board Manager. It uses the USB.0 interface of the board to write raw binary FPGA configuration bitstreams (*.bin) into the onboard SPI flash. You can find details about the UDK Board Manager in our user guide UG0. Loading SPI flash via JTAG Another way to program the SPI flash is by using the XilinxTM Platform Cable (not included in the EFM0 scope of delivery) and the XilinxTM VIVADO suite. Select nq.vspix_x_x when adding a configuration memory device. To speed up FPGA configuration from serial flash, user designs can use QuadSPI and EMCCLK option. EFM0 comes with an onboard 0 MHz clock oscillator for highest FPGA configuration speeds from SPI flash. Prevent SPI configuration at startup Default configuration at startup is from the serial SPI flash device. To prevent starting from SPI flash, set Flash_Inhibit_n to a logic low level prior to enabling FPGA power supplies. After configuration using a different programming interface, Flash_Inhibit_n has to be released before access to the SPI flash is possible again. Pinnumber J, pin Signal name Comment Flash_Inhibit_n Activelow input to prevent programming of FPGA from SPI flash device at startup. EFM0 SPI programming via USB requires at least UDK Board Manager v.. UG0 (v.0) August, 0

7 FPGA Configuration USB EFM0 also supports direct reprogramming of the Artix FPGA via USB without altering the SPI flash content. USB configuration is available at all times, as long as FPGA power supplies are enabled. Use CESYS UDK Board Manager or the suitable function call from the CESYS UDK API to download the *.bin configuration file. Configuring the FPGA via USB.0 is the fastest of all supported configuration modes for the EFM0. JTAG The FPGA JTAG interface is routed to the expansion connector J. All necessary pullup resistors are already installed on the EFM0 module. Configuration through the JTAG interface is available at all times, as long as FPGA power supplies are enabled. The JTAG programming voltage is fixed to the. Volt VCCO_0 power supply voltage, which is available at connector J as well. JTAG J FPGA signal name pinnumber direction Comment TDO 0 Out TMS In Test mode select TCK In Test clock TDI In Test data in VCCO_0,. Volt JTAG programming voltage UG0 (v.0) August, 0 Test data out

8 Power supply options Power supply options The EFM0 can be operated from a single.0 V power source supplied at pins and of the expansion connector J. onboard highefficiency switching regulators provide all necessary power supplies:. V,. V,. V,. V,.0 V. A lowdropout regulator is used to derive the DDRL termination voltage from. V. The.0 V USB.0 VBUS power supply is available at pin of the expansion connector J, the.v power supply is connected to pins and of J. The EFM0 is designed to support both USB power supply schemes: buspowered and selfpowered mode. Buspowered mode In buspowered mode pins and of the expansion connector J MUST be connected to the.0 V USB.0 VBUS power supply, which is provided at pin of J. Either install jumper J or plug EFM0 module into an adequate board. Please be sure to remove jumper J in case an external power supply should be used. Otherwise EFM0 or connected devices may be damaged. According to the USB specifications, the FPGA power supplies are only switched on, when an USB connection has been established and FX firmware has been downloaded successfully. PWR_ENA_EXT on pin of J MUST be left open for buspowered mode to work properly. Selfpowered mode In selfpowered mode, connect an adequate external.0 V power supply to J pins and. Pin of J, which connects to USB.0 VBUS power supply, should be left open. Please make sure that jumper J is not installed. Otherwise EFM0 or attached devices may be damaged. NEVER connect an external power supply to J, pin, as this may damage the host computers USB peripheral interface. Similar to buspowered mode, internal logic controls the generation of FPGA power supplies and only activates these, when an USB connection has been established and FX firmware has been UG0 (v.0) August, 0

9 Power supply options downloaded successfully. If FPGA power supplies shall be enabled regardless of the USB connection state, PWR_ENA_EXT on pin of J must be driven to a logic HIGH level or connected to the external.0 V power supply. Then all necessary onboard power supplies are enabled as soon as the external.0 V power supply becomes available. Power supply mode J, Pins, Buspowered Either install jumper J or plug EFM0 into an adequate breakout board which connects these pins. open USB controlled Connect to external.0 V power supply. open open Instant on Connect to external.0 V power supply. open Connect to external.0 V power supply or drive to a logic HIGH level. Selfpowered J, Pin External power supply input requirements Power supply input range at J, Pins + Minimum current requirement J, Pin Min. Typ. Max Units V ma FPGA configured with EFM0 SoC design, USB.0 transmission to onboard Gbyte DDRL memory at maximum speed. UG0 (v.0) August, 0

10 Onboard peripherals Onboard peripherals With plenty of FPGA I/O available at the expansion connectors the EFM0 supports a vast number of applications. To help the system designer to successfully implement a Artix design some crucial peripherals are installed onboard, with a VHDL reference design 'efm0_wrapper' readily available. QuadSPI configuration/data memory The onboard serial flash device Micron NQA provides MByte of nonvolatile storage. The flash is connected to the configuration interface of the FPGA and serves as default configuration medium. At least two FPGA configuration files can be stored in flash allowing MultiBoot operation. Remaining free storage can be used in user designs. The NQA device supports standard Serial Peripheral Interface as well as the faster DualSPI and QuadSPI modes. The flash device supports clock frequencies of up to 0 MHz, allowing data rates up to MByte/s in QuadSPI mode. SPI Flash DQ0 FPGA Pin Comment R Serial data IO0 DQ R Serial data IO C H Serial clock S# P Chip select W#/DQ P Write protect/serial data IO HOLD#/DQ N Hold/Serial data IO Connected only when FPGA configuration via USB is disabled (default mode).. kohm pullup resistor connected onboard EFM0. UG0 (v.0) August, 0 0

11 Onboard peripherals DDRL memory The EFM0 module provides GByte of highspeed lowpower DDRL memory connected to FPGA banks and, which are supplied by an onboard. V switching power supply. The following table gives detailed information about the connections. DDR FPGA Pin FPGA Direction DQ0 G data bus bit 0 DQ G data bus bit DQ H data bus bit DQ H data bus bit DQ F data bus bit DQ E data bus bit DQ F data bus bit DQ D data bus bit DM0 H Data mask signal for byte 0 H, G Differential data strobe signal for byte 0 DQ K data bus bit DQ J data bus bit DQ0 L data bus bit 0 DQ F data bus bit DQ J data bus bit DQ G data bus bit DQ K data bus bit DQ G data bus bit DM K Data mask signal for byte J, H Differential data strobe signal for byte DQ B data bus bit DQ D data bus bit DQ D data bus bit DQ F data bus bit DQ0 C data bus bit 0 DQ D data bus bit DQ A data bus bit DQ E data bus bit Data mask signal for byte DQS0_P, DQS0_N DQS_P, DQS_N DM DQS_P, DQS_N DQ Comment C B, A Differential data strobe signal for byte A data bus bit Type of the DDRL devices: Alliance Inc. ASCMDLBCN UG0 (v.0) August, 0

12 Onboard peripherals DDR FPGA Pin FPGA Direction DQ E data bus bit DQ E data bus bit DQ A data bus bit DQ D data bus bit DQ F data bus bit DQ0 G data bus bit 0 DQ C data bus bit DM G Data mask signal for byte C, B A0 M Address input bit 0 A T Address input bit A U Address input bit A N Address input bit A R Address input bit A P Address input bit A M Address input bit A R Address input bit A U Address input bit A L Address input bit A0 L Address input bit 0 A T Address input bit A M Address input bit A N Address input bit A K Address input bit A L Address input bit BA0 T Bank address input BA P Bank address input BA T Bank address input RAS# H Command input CAS# N Command input WE# N Command input ODT H Ondie termination DQS_P, DQS_N CK_P, CK_N Comment Differential data strobe signal for byte N, N Differential memory clock CKE J Clock enable CS# P Chip select RESET# N ZQ0, ZQ UG0 (v.0) August, 0 Connected to via 0 Ohm resistor for ODT calibration

13 Onboard peripherals USB.0UART For in design debug purposes of your FPGA design you can use the serial UART interface provided onboard by one FTDI FT0X device. The USB to BASIC UART interface is available at the USB.0 MiniB connector. Device connections are summarized in the following table. For more details about the FTDI FT0X please refer to the datasheet available at USBtoUART Signal Name FPGA Pin FPGA Direction Comment USBDM, USBDP RxD T Out Receiving Asynchronous Data Input. TxD R In Transmit Asynchronous Data. RTS# T In Request to Send Control / Handshake Signal. CTS# R Out CBUS0 Not connected. CBUS RXLED#. Pulses low when receiving data via USB. Lights up led D0. CBUS TXLED#. Pulses low when transmitting data via USB. Lights up led D. CBUS SLEEP#. Goes low during USB suspend mode. Availabe at test pad TP. RESET# FTDI reset input (active low). Connected to MicroB VBUS power supply through resistor network. Differential USB data signal pair. Clear To Send Control Input / Handshake Signal. Status leds Three leds give basic information about power and configuration status of the EFM0 module. Led Color D Green DONE Lights up, when FPGA is configured. D Red ERROR Lights up, when some error occurs during FPGA initialization. Green OK D UG0 (v.0) August, 0 Function Comment Lights up, when FPGA initialization was successful.

14 Onboard peripherals LED D connects to the FPGA DONE output signal. Whenever a valid configuration file is stored within FPGA SRAM this led will light up green. Leds D and D are connected to the FPGA INIT_B pin, signaling information about FPGA initialization status. User led In addtion to the three status leds mentioned above, EFM0 provides one user accessible led. D is controllable through FPGA pin N. Use it for additional user specific status information. A HIGH level output will turn the blue led on. Led D Color FPGA Pin Blue N Comment Set HIGH to light up led. Figure : EFM0: User and status leds UG0 (v.0) August, 0

15 Onboard clocks Onboard clocks EFM0 offers two onboard clock oscillators. One, a high performance 00 MHz LVDS clock oscillator, is used to provide a high stability system clock. The other, a 0 MHz low power CMOS oscillator, is connected to the EMCCLK input pin of the Xilinx TM Artix device. Highstability LVDS system clock oscillator EFM0 provides a highstability 00 MHz differential system clock on FPGA balls R and P. FPGA internal PLL / DCM can be used to generate a multitude of clock signals. See the following table for some specifications. Parameter Value Frequency 00 MHz Frequency stability +/0 ppm RMS phase jitter (typ.) 0. ps RMS period jitter (max.). ps rise/fall time (typ.) 0 ps Differential output voltage (typ.) 0 mv FPGA balls for SYSCLK_P, SYSCLK_N R, P Low power CMOS oscillator To enable the highest possible configuration speeds from SPI flash with predictable configuration times, EFM0 provides a 0 MHz low power CMOS oscillator on the EMCCLK input pin. For further information about Master SPI configuration mode and the usage of the EMCCLK clock input with your design, please consult the Xilinx TM Series FPGAs Configuration guide ug0. Parameter Value Frequency 0 MHz Frequency stability +/0 ppm RMS phase jitter (typ.). ps RMS period jitter (max.) ps rise/fall time (typ.) ns FPGA ball for EMCCLK P UG0 (v.0) August, 0

16 SuperSpeed USB.0 SuperSpeed USB.0 EFM0 provides a SuperSpeed USB.0 interface using the versatile controller CYUSB0BZ from Cypress Semiconductor. To keep up with the enormously high USB.0 data rates, a bit Slave FIFO interface running at 00 MHz is used for communication between FPGA and the EZUSB FX. See CESYS UG0 UDKPerformanceMonitor for benchmarks and CESYS UG axifxinterface for a close description of a slavefifo interface reference design. I²C EEPROM EFM0 includes the Mbit AtmelTM ATCM0XHM I²C EEPROM to store VID/PID data for the USB enumeration process. In case you decide to develop your own FX firmware and store it inside nonvolatile memory rather than downloading Figure : EZUSB FX I²C EEPROM it via USB, it may be required to increase the available memory due to the size of FX firmware images. To increase available storage EZUSB FX supports multiple EEPROM devices of the same size and type sharing the I²C bus. The firmware image then should be stored across the EEPROMs as a contiguous image as in a single I²C device. On more information about EZFX boot options using the I²C interface please consult the application note AN0 from CypressTM. EZUSB FX's I²C interface is available at the expansion connector J. FX Exp. FX Direction FX_SDA J, (Open drain) FX_SCL J, 0 (Open drain) VIO J, J, Comment I²C interface data line I²C interface clock signal I²C power supply output power terminal Please note, that EZUSB FX boot loader works in USB.0 mode. With EFM0 the default boot mode is via USB, therefore USB.0 D+/D lines are still required, even if user applications would only use SuperSpeed USB.0 mode. UG0 (v.0) August, 0

17 SuperSpeed USB.0 Slave FIFO interface The synchronous Slave FIFO interface uses a bit parallel data bus and several status/control I/O to perform data read/write accesses to EZUSB FX's internal FIFO buffers. Register accesses are not done using the Slave FIFO interface. See the following table for a list of connections between FPGA and EZUSB FX used for the host interface. For more information about how you can use EFM0's USB.0 interface please consult CESYS ug0udkapispecification and the EFM0SoC reference design. FX FPGA Pin FPGA Direction PCLK N, M /Input Slave FIFO interface clock DQ0 T data bus bit 0 DQ L data bus bit DQ L data bus bit DQ L data bus bit DQ N data bus bit DQ N data bus bit DQ R data bus bit DQ R data bus bit DQ N data bus bit DQ K data bus bit DQ0 K data bus bit 0 DQ M0 data bus bit DQ L0 data bus bit DQ L data bus bit DQ M data bus bit DQ M data bus bit DQ R data bus bit DQ T data bus bit DQ R data bus bit DQ T data bus bit DQ0 P data bus bit 0 DQ R data bus bit DQ T data bus bit DQ M data bus bit DQ N data bus bit DQ P data bus bit DQ R data bus bit DQ R data bus bit UG0 (v.0) August, 0 Comment

18 SuperSpeed USB.0 FX FPGA Pin FPGA Direction Comment DQ R0 data bus bit DQ P data bus bit DQ0 P data bus bit 0 DQ N data bus bit SLCS# M Chip select for Slave FIFO interface SLWR# M Write strobe for Slave FIFO interface SLRD# K Read strobe for Slave FIFO interface SLOE# K enable PKTEND L Short packet signal FLAGA P Input Flag output from FX FLAGB N Input Flag output from FX GPIO / CTL[] J Input EZFX GPIO or control output GPIO / CTL[] J Input EZFX GPIO or control output0 GPIO / CTL[] R Input EZFX GPIO or control output GPIO / CTL[0] J Input EZFX GPIO or control output CTL[] K Input EZFX control output (Bit modes only) A0 P0 Address input of Slave FIFO interface A N Address input of Slave FIFO interface GPIO K Input FPGA RESET 0 Connected to FPGA CCLK during configuration via USB. Software settable activehigh reset signal. Used during configuration via USB for synchronization purposes. Pullup resistor connected onboard EFM0. UG0 (v.0) August, 0

19 SuperSpeed USB.0 FX additional connections For configuration purposes some additional connections between Xilinx TM FPGA and CypressTM EZUSB FX are necessary. The following chart gives some information about these and where to find them on the expansion connector J. Additionally GPIO and GPIO of CypressTM EZUSB FX are routed to the expansion connector J. However with EFM0 default firmware those GPIO signals are not implemented. Please refer to the EZUSB FX's data sheet on CypressTM website for more information about usability of GPIO signals. FX Expansion Connector FPGA Direction GPIO GPIO0 P Input GPIO J, Pin0 W0 Comment USB_CONFIGn FPGA_CSI_B Input/ Done GPIO J, Pin V Init_B GPIO J, Pin AE Input Program_B GPIO J, Pin K Input FPGA RESET GPIO J, Pin FX GPIO GPIO J, Pin FX GPIO GPIO FPGA power enable A logic HIGH level enables FGPA configuration via USB. SPI flash clock MUST be set to tristate mode prior to enabling USB configuration mode, for example by pulling Program_B low. Open drain. Software settable activehigh reset signal. Used during configuration via USB for synchronization purposes. Pullup resistor connected onboard EFM0. A logic HIGH level enables FPGA power supplies. See EFM0 power supply options for more details. UG0 (v.0) August, 0

20 Digital IO expansion connectors Digital IO expansion connectors Two 0,0mm 0pin Q Strip highspeed ground plane expansion connectors (SamtecTM: QSE000LDA) on the bottomside of the EFM0 offer access to up to FPGA I/O, two FX GPIO, FX I²C interface, FX and FPGA JTAG signals, some configuration I/O and selected power rails. Optionally USB signals are available. As default all I/O are configured for. V LVTTL signaling levels. Optionally VCCO power supplies for selected banks of the Artix FPGA can be accessed independently. Then an adequate power supply has to be connected to the corresponding expansion pins to set the required signaling level. Additionally one 0.0 mm 0pin Q Strip highspeed ground plane expansion connector (SamtecTM: QSE000LDA) offers access to all receiver, transmitter and reference clock pairs of the Artix FPGA GTP blocks MGT and MGT. SamtecTM offers mating connectors in several variations resulting in different total mating heights. See the following table for some information. Please refer to the SamtecTM website for details. SamtecTM part number UG0 (v.0) August, 0 Mated height QTE000LD.00 mm QTE000LD.00 mm QTE000LD.00 mm QTE000LD.00 mm QTE000LD.00 mm QTE000LD.00 mm 0

21 Digital IO expansion connectors Pinout expansion connector J J FPGA F J FPGA PG, ION IO_LN_T_ FX khz clock in G PG, IOP IO_LP_T_ FPGA Init_B G PG, ION IO_LN_T_ Flash_Inhibit_N H PG, IOP IO_LP_T_ FPGA Program_B H PG, ION IO_LN_T_ 0 FPGA Done J PG, IOP IO_LP_T_ J PG, IO0 IO_LP_T_.V power output L PG, ION IO_LN_T0_ADN_.V power output M PG, IOP IO_LP_T0_ADP_ L PG, ION IO_LN_T_AD0N_ Y PG0, ION IO_LN_T0_ W PG0, IOP IO_LP_T0_ 0 L PG, IOP IO_LP_T_AD0P_ Y PG0, ION IO_LN_T_SRCC_ M PG, IO0N IO_LN_T0_ Y PG0, IOP IO_LP_T_SRCC_ M PG, IO0P IO_LP_T0_ V PG0, IOP IO_LP_T0_ L PG, IO0N IO_LN_T0_ W PG0, ION IO_LN_T0_VREF_ M PG, IO0P IO_LP_T0_ AA PG0, ION IO_LN_T_ 0 V PG0, IOP IO_L0P_T_ AA PG0, IOP IO_LP_T_ W PG0, ION IO_L0N_T_ AB PG0, ION IO_LN_T_ Y PG0, IOP IO_LP_T0_ AA PG0, IOP IO_LP_T_ AA PG0, ION IO_LN_T0_ U PG0, IOP IO_LP_T_MRCC_ W PG0, IOP IO_LP_T_MRCC_ V PG0, ION IO_LN_T_MRCC_ 0 Y PG0, ION IO_LN_T_MRCC_ FPGA IO within the same pin group (PG0, PG, PG) are powered via the same power supply. PG0 and PG power supplies are routed independently and optionally can be powered via the respective expansion pins to support IO signaling levels other than the default. Volt LVTTL. Flash_Inhibit_N: Default FPGA configuration at startup is from SPI flash. To prevent SPI configuration, drive this pin to a logic LOW level, prior to enabling FPGA power supplies. Onboard A switching power supply output. Also supplies FPGA auxiliary voltage VCCAUX. UG0 (v.0) August, 0

22 Digital IO expansion connectors J FPGA J FPGA AA0 PG0, IOP IO_LP_T_MRCC_ V PG0, IOP IO_LP_T0_ AB0 PG0, ION IO_LN_T_MRCC_ W PG0, ION IO_LN_T0_ AD PG0, IOP IO_LP_T_ U PG0, IO0N IO_LN_T0_ AE PG0, ION IO_LN_T_ U PG0, IO0P IO_LP_T0_ AE PG0, IO0P IO_LP_T_DQS_ 0 AC PG0, ION IO_LN_T0_DQS_ AF PG0, IO0N IO_LN_T_DQS_ AB PG0, IOP IO_LP_T0_DQS_ AD0 PG0, IOP IO_L0P_T_ AB PG0, IO0P IO_LP_T_DQS_ AE0 PG0, ION IO_L0N_T_ AC PG0, IO0N IO_LN_T_DQS_ AF0 PG0, ION IO_LN_T_ AB PG0, IOP IO_LP_T_SRCC_ AF PG0, IOP IO_LP_T_ 0 AC PG0, ION IO_LN_T_SRCC_ AE PG0, IOP IO_LP_T_ Y0 PG0, ION IO_LN_T_ AF PG0, ION IO_LN_T_ W0 PG0, IOP IO_LP_T_ AB PG0, ION IO_LN_T_MRCC_ J PG, IOP IO_L0P_T_ADP_ AA PG0, IOP IO_LP_T_MRCC_ H PG, ION IO_L0N_T_ADN_ T0 PG0, IOP IO_LP_T_DQS_ 0 AD PG0, ION IO_LN_T_SRCC_ U0 PG0, ION IO_LN_T_DQS_ AC PG0, IOP IO_LP_T_SRCC_ T PG0, IOP IO_LP_T_ AD PG0, ION IO_LN_T_DQS_ U PG0, ION IO_LN_T_ AC PG0, IOP IO_LP_T_DQS_ W PG0, ION IO_LN_T_ T PG0, ION IO_LN_T_DQS_ V PG0, IOP IO_LP_T_ 0 T PG0, IOP IO_LP_T_DQS_ FPGA IO within the same pin group (PG0, PG, PG) are powered via the same power supply. PG0 and PG power supplies are routed independently and optionally can be powered via the respective expansion pins to support IO signaling levels other than the default. Volt LVTTL. UG0 (v.0) August, 0

23 Digital IO expansion connectors J FPGA 0 J FPGA W PG0, ION IO_LN_T_VREF_ PG0 Optional power supply input for FPGA pin group PG0 V PG0, IOP IO_LP_T_ PG0 Optional power supply input for FPGA pin group PG0 AE PG, ION IO_LN_T_DQS_ V PG0, ION IO_LN_T_ AD PG, IOP IO_LP_T_DQS_ U PG0, IOP IO_LP_T_ V PG0, ION IO_LN_T_ 0 T PG0, ION IO_L0N_T_ V PG0, IOP IO_LP_T_ T PG0, IOP IO_L0P_T_ AD PG, ION IO_LN_T_ U PG0, IOP IO_LP_T_MRCC_ AC PG, IOP IO_LP_T_ V PG0, ION IO_LN_T_MRCC_ AC PG, ION IO_LN_T_ AC PG, IOP IO_LP_T_SRCC_ AB PG, IOP IO_LP_T_ 00 AD PG, ION IO_LN_T_SRCC_ 0 U PG0, IO0N IO_LN_T_ 0 AF PG, ION IO_LN_T_ 0 U PG0, IO0P IO_LP_T_ 0 AE PG, IOP IO_LP_T_ 0 AF PG, IOP IO_LP_T_ 0 AB PG, IO0P IO_LP_T_SRCC_ 0 AF PG, ION IO_LN_T_ 0 AC PG, IO0N IO_LN_T_SRCC_ 0 FPGA TDO 0 AE PG, ION IO_LN_T_DQS_ FPGA TMS AD PG, IOP IO_LP_T_DQS_ FPGA TCK PG.V power output FPGA TDI PG.V power output Not connected AE PG, IOP IO_L0P_T_ 0 AF PG, ION IO_L0N_T_ FPGA power enable input 0 FPGA IO within the same pin group (PG0, PG, PG) are powered via the same power supply. PG0 and PG power supplies are routed independently and optionally can be powered via the respective expansion pins to support IO signaling levels other than the default. Volt LVTTL. With the default assembly option pin group PG0 is supplied by the onboard. Volt power supply through a 0 Ohm series resistor. Optionally PG0 can be powered externally to support signaling levels other than the default. Volt LVTTL. For details about signal levels supported by Xilinx TM Series FPGAs, please refer to guide ug. CAUTION: Resistor R0 MUST not be set in this case. Onboard A switching power supply output. Also supplies FPGA pin group PG, JTAG and FX VIO. Internal logic controls FPGA power supplies. If FPGA power supplies need to be enabled regardless of USB connection status, drive this pin to a logic HIGH level (LVTTL.V) or connect to VBUS_IO. UG0 (v.0) August, 0

24 Digital IO expansion connectors Pinout expansion connector J J FPGA J FPGA.0 V input (VBUS_IO) USB.0 D.0 V input (VBUS_IO) USB.0 D+.0 V output (USB VBUS) USB OTG ID USB.0 TX FX TRSTn 0 FX TDO FX TMS USB.0 TX+ USB.0 RX+ USB.0 RX FX TDI FX I²C power supply output. FX RESET# input FX TCK FX SDA: I²C data IO FX GPIO 0 FX SCL: I²C clock output FX GPIO Not connected Not connected K PG FPGA RESET E PG, IOP IO_LP_T_DQS_ K0 PG, IOP IO_L0P_T_DQS_ADP_ D PG, ION IO_LN_T_DQS_ J0 PG, ION IO_L0N_T_DQS_ADN_ E PG, IOP IO_L0P_T_ 0 F PG, IOP IO_LP_T_ D PG, ION IO_L0N_T_ E PG, ION IO_LN_T_ K PG, ION IO_LN_T_ H PG, ION IO_LN_T_MRCC_ K PG, IOP IO_LP_T_ H PG, IOP IO_LP_T_MRCC_ J PG, IOP IO_LP_T_SRCC_ J PG, IOP IO_LP_T_ADP_ H PG, ION IO_LN_T_SRCC_ 0 H PG, ION IO_LN_T_ADN_ FPGA IO within the same pin group (PG0, PG, PG) are powered via the same power supply. PG0 and PG power supplies are routed independently and optionally can be powered via the respective expansion pins to support IO signaling levels other than the default. Volt LVTTL. EFM0 power supply input. Either connect USB VBUS or an adequate.0 Volt power supply. Directly connected to USB.0 VBUS power supply through a ferrite bead. Reserved. Requires special assembly option. See ordering information for more details. Onboard A switching power supply output. Also supplies FPGA pin group PG, JTAG and FX VIO. Software settable activehigh reset signal. Used during configuration via USB for synchronization purposes. Pullup resistor connected onboard EFM0. UG0 (v.0) August, 0

25 Digital IO expansion connectors J FPGA 0 J FPGA K PG, IOP IO_LP_T_MRCC_ C PG, IOP IO_LP_T_ J PG, ION IO_LN_T_MRCC_ B PG, ION IO_LN_T_ G PG, IOP IO_LP_T_ B PG, IOP IO_L0P_T_ F PG, ION IO_LN_T_ A PG, ION IO_L0N_T_ D PG, ION IO_LN_T_ 0 A PG, IO0N IO_LN_T_DQS_ D PG, IOP IO_LP_T_ A PG, IO0P IO_LP_T_DQS_ C PG, ION IO_LN_T_VREF_ B PG, IOP IO_LP_T_ C PG, IOP IO_LP_T_ A PG, ION IO_LN_T_ G PG, IOP IO_LP_T_DQS_ C PG, IOP IO_LP_T_ F PG, ION IO_LN_T_DQS_ 0 B PG, ION IO_LN_T_.V power output G PG, ION IO_LN_T_SRCC_.V power output G0 PG, IOP IO_LP_T_SRCC_ D PG, ION IO_LN_T_ D0 PG, IO0N IO_LN_T_SRCC_ E PG, IOP IO_LP_T_ E0 PG, IO0P IO_LP_T_SRCC_ A PG, ION IO_LN_T_DQS_ 0 B PG, ION IO_LN_T_ A PG, IOP IO_LP_T_DQS_ C PG, IOP IO_LP_T_ G PG, ION IO_LN_T0_VREF_ F0 PG, ION IO_LN_T0_ H PG, IOP IO_LP_T0_ G PG, IOP IO_LP_T0_ C PG, ION IO_LN_T_MRCC_ C PG, ION IO_LN_T_MRCC_ D PG, IOP IO_LP_T_MRCC_ 0 D PG, IOP IO_LP_T_MRCC_ 0 FPGA IO within the same pin group (PG0, PG, PG) are powered via the same power supply. PG0 and PG power supplies are routed independently and optionally can be powered via the respective expansion pins to support IO signaling levels other than the default. Volt LVTTL. Onboard A switching power supply output. Also supplies FPGA GTP blocks and FX core. UG0 (v.0) August, 0

26 Digital IO expansion connectors J FPGA P PG G J FPGA Optional EMCCLK output F PG, ION IO_LN_T0_DQS_ FPGA VCCBATT input F PG, IOP IO_LP_T0_DQS_ G PG, IOP IO_LP_T0_ IO_LN_T_ J PG Not connected F PG, ION IO_LN_T0_ U PG, IOP IO_LP_T0_ 0 C PG, IOP IO_LP_T_ V PG, ION IO_LN_T0_VREF_ B PG, ION IO_LN_T_ AA PG, IO0N IO_LN_T_ D PG, ION IO_LN_T_ Y PG, IO0P IO_LP_T_ E PG, IOP IO_LP_T_ E PG, IOP IO_LP_T_SRCC_ A0 PG, ION IO_LN_T_DQS_ E PG, ION IO_LN_T_SRCC_ 00 B0 PG, IOP IO_LP_T_DQS_ 0 AA PG, IOP IO_LP_T_MRCC_ 0 F PG, ION IO_LN_T0_ 0 AB PG, ION IO_LN_T_MRCC_ 0 G PG, IOP IO_LP_T0_ 0 V PG, IOP IO_LP_T0_ 0 AA PG, IOP IO_LP_T_MRCC_ 0 W PG, ION IO_LN_T0_ 0 AA PG, ION IO_LN_T_MRCC_ 0 Y PG, IOP IO_LP_T_ 0 H PG, IO0N IO_LN_T0_ AA PG, ION IO_LN_T_VREF_ H PG, IO0P IO_LP_T0_ V PG, IOP IO_LP_T0_DQS_ A PG, ION IO_L0N_T_ V PG, ION IO_LN_T0_DQS_ B PG, IOP IO_L0P_T_ Y PG, ION IO_LN_T0_ PG Optional power supply input for FPGA pin group PG W PG, IOP IO_LP_T0_ 0 PG Optional power supply input for FPGA pin group PG FPGA IO within the same pin group (PG0, PG, PG) are powered via the same power supply. PG0 and PG power supplies are routed independently and optionally can be powered via the respective expansion pins to support IO signaling levels other than the default. Volt LVTTL. As default this pin is not connected. When series resistor R on EFM0 is set, this pin connects to the 0 MHz clock oscillator used for EMCCLK generation. On EFM0/B this pin was connected to the optional clock oscillator which could be used as USERCCLK input. On EFM0/B the 00 MHz system clock was available at this pin. To provide compatibility to older hardware, user designs might be required to provide an equivalent clock output here. With the default assembly option pin group PG is supplied by the onboard. Volt power supply through a 0 Ohm series resistor. Optionally PG can be powered externally to support signaling levels other than the default. Volt LVTTL. For details about signal levels supported by Xilinx TM Series FPGAs, please refer to guide ug. CAUTION: Resistor R0 MUST not be set in this case. UG0 (v.0) August, 0

27 Nondefault signal levels on PG0 and PG Nondefault signal levels on PG0 and PG To support signal levels other than the default. V LVTTL, VCCO power supplies for the EFM0 pin groups PG0 and PG optionally can be sourced externally. Both pin group power supplies are routed independently from all other power supplies onboard the EFM0 and only connected to the. V power rail by series resistors R0 and R0 respectively. Once one or both resistors are removed, VCCO power for the corresponding pin group has to be supplied on the respective input pins on the IO expansion connectors J and J. Figure : Series resistors for VCCO of PG0 / PG on EFM0. Figure : EFM0: Series resistors for VCCO_PGO and VCCO_PG For details about signal levels supported by XilinxTM Series FPGAs, please refer to guide ug. UG0 (v.0) August, 0

28 GTP Quad expansion connector GTP Quad expansion connector Additionally to the two 0pin IO connectors, EFM0 provides one 0.0 mm 0pin Q Strip highspeed ground plane expansion connector (Samtec TM: QSE000LDA). Connector J offers access to all differential receiver, transmitter and reference clock pairs of the Artix FPGA GTP blocks MGT and MGT. For more details about GTP Quad Transceivers in Series FPGAs please refer to XilinxTM UG. SamtecTM offers mating connectors in several variations resulting in different total mating heights. Please refer to the SamtecTM website for details. SamtecTM part number Mated height QTE000LD J FPGA.00 mm QTE000LD.00 mm QTE000LD.00 mm QTE000LD.00 mm QTE000LD.00 mm QTE000LD.00 mm J FPGA A MGT MGTPTXN D MGT MGTPRXP B MGT MGTPTXP C MGT MGTPRXN C0 MGT MGTPTXN B MGT MGTPRXP D0 MGT MGTPTXP A MGT MGTPRXN A MGT MGTPTXN0 0 B MGT MGTPRXP0 B MGT MGTPTXP0 A MGT MGTPRXN0 C MGT MGTPTXN D MGT MGTPRXP D MGT MGTPTXP C MGT MGTPRXN E MGT MGTREFCLKN F MGT MGTREFCLK0P F MGT MGTREFCLKP 0 E MGT MGTREFCLK0N AA MGT MGTREFCLK0P AB MGT MGTREFCLKN AB MGT MGTREFCLK0N AA MGT MGTREFCLKP AC MGT MGTPTXP AF MGT MGTPRXN AD MGT MGTPTXN AE MGT MGTPRXP AE MGT MGTPTXP 0 AF MGT MGTPRXN AF MGT MGTPTXN AE MGT MGTPRXP AE MGT MGTPTXP AD MGT MGTPRXN0 AF MGT MGTPTXN AC MGT MGTPRXP0 AC0 MGT MGTPTXP0 AF MGT MGTPRXN AD0 MGT MGTPTXN0 0 AC MGT MGTPRXP UG0 (v.0) August, 0

29 Evaluation Evaluation EFM0 on EFM0 Breakout Board Figure : EFM0 breakout board connectors UG0 (v.0) August, 0

30 Evaluation Power supply options The EFM0 breakout board supports all power supply options of the EFM0 modules. Jumpers J, J and J are used to select the appropriate power scheme. J0 serves as input for an optional external.0 V power supply. J FPGA power on sequence select Jumper Position Power on sequence USB controlled Instant on Comment Requires external power supply J Power source select EFM0 or Breakout Board Jumper Position Power scheme Power supply Buspowered USB.0 Connector on EFM0 Self or Buspowered Selection with J J Power source select on Breakout Board Jumper Position Power scheme Power supply Buspowered USB.0 Connector J on Breakout Board Selfpowered External.0 V at J0 J0 External power supply input Pin Signal V_EXT Comment Negative terminal for external power supply Positive terminal for external.0 V power supply External power supply input requirements Power supply input range Minimum current requirement Min. Typ. Max. Units.. V 0 ma FPGA configured with efm0_wrapper design, USB.0 transmission to onboard Gbyte DDRL memory at maximum speed. UG0 (v.0) August, 0 0

31 Evaluation JTAG and pushbuttons Figure : SW FPGA Program_B Figure : J FPGA JTAG Figure : SW EZFX Reset With the pin mm connector J the EFM0 breakout board supports standard XilinxTM JTAG download cables. With the help of the free XilinxTM Vivado WebPack the FPGA and the attached SPI flash can be programmed. Once the SPI flash is programmed with a valid bitstream, reprogramming of the FPGA can be initiated by pressing the pushbutton SW. Figure 0: EZUSB FX JTAG Additionally, the EZUSB FX JTAG interface is routed to J, a standard. mm 0pin shrouded header. This allows direct connection of the JTAG/SWD Emulator with USB interface from Segger, which is recommended by Cypress TM. For more details please refer to the FX Programmers Manual within EZUSB FX Software Development Kit. To hard reset EZUSB FX press the pushbutton SW. UG0 (v.0) August, 0

32 Evaluation EZUSB FX GPIO and I²C The general purpose inputs/outputs GPIO and GPIO of the Cypress TM EZUSB FX controller are available at the shrouded header J. The optionally usable watchdog timer inside FX may be optionally supplied by an external khz clock source. The associated CLKIN input is accessible at pin three of connector J. EFM0 uses the I²C EEPROM ATCM0XHM from Atmel to store VID/PID data. To increase available storage for larger firmware files EZUSB FX supports multiple devices of the same size and type sharing the I²C bus. On more information about boot options using the I²C interface please consult AN0 from CypressTM. Figure : FX GPIO signals Figure : EZUSB FX I²C connector Figure : EZUSB FX I²C EEPROM on EFM0 module UG0 (v.0) August, 0

33 Evaluation FPGA inputoutputsignals Except 'IO_LP_T_' (FPGA ball J) located at pin of the EFM0 expansion connector J, which is connected to the green led LED onboard the EFM0 breakout board, all other FPGA digital IO signals are routed to standard. mm throughhole shrouded headers for easy access. To prevent FPGA bootup from flash you can assert Flash_Inhibit_n by applying jumper J, while test pins are available for the FPGA bank supplies VCCO_PG0, VCCO_PG, VCCO_V and FPGA status signals Init_B and Done. Figure : Green user led on EFM0 breakout board. Figure : Jumper for Flash_Inhibit_n Figure : J0 with signals FPGA_VFS, SYSCLK, FPGA_VCCBAT, USERCLK Figure : J Figure : FPGA: Init_B and Done signals Figure : VCCO_PG To support signal levels other than the default. V LVTTL, EFM0 pin groups PG0 and PG can optionally be supplied by an external voltage of the required level. BE SURE to remove resistors R0 and/or R0 on EFM0 before applying any voltages to VCCO_PG0 or VCCO_PG. For details about signal levels supported by XilinxTM Series FPGAs, please refer to guide ug. J,Pin for VCCO_V is for the purpose of measuring the supply voltage of pin group PG only. DO NOT connect external power supplies. UG0 (v.0) August, 0

34 Evaluation J odd 0 C PG, ION AA PG, ION H B Y PG, ION V Y J, J even J, LP_T_ C PG, IOP J, 0 LN_T_MRCC_ AA PG, IOP J, 0 LP_T_MRCC_ PG, IO0P J, LP_T0_ H PG, IO0N J, 0 LN_T0_ PG, IOP J, L0P_T_ A PG, ION J, L0N_T_ J, LP_T0_ 0 W PG, IOP J, LN_T0_ PG, IOP J, LP_T0_DQS_ V PG, ION J, LN_T0_DQS_ PG, IOP J, 0 LP_T_ AA PG, ION J, LN_T_VREF_ J odd LN_T_VREF_ Pin Group0 J even G PG, ION J, IO_LN_T0_VREF_ H PG, IOP J, IO_LP_T0_ F PG, IOP J, IO_LP_T0_DQS_ F PG,ION J, IO_LN_T0_DQS_ F PG, ION J, IO_LN_T0_ G PG, IOP J, IO_LP_T0_ B PG, ION J, IO_LN_T_ C PG, IOP J, 0 IO_LP_T_ E PG, IOP J, IO_LP_T_ 0 D PG, ION J, IO_LN_T_ B0 PG, IOP J, 00 IO_LP_T_DQS_ A0 PG, ION J, IO_LN_T_DQS_ G PG, IOP J, 0 IO_LP_T0_ F PG, ION J odd J, 0 IO_LN_T0_ J even D PG, ION J, IO_LN_T_ E PG, IOP J, IO_LP_T_ C PG, IOP J, IO_LP_T_ B PG, ION J, 0 IO_LN_T_ A PG, ION J, IO_LN_T_DQS_ A PG, IOP C D PG, IOP PG, ION J, IO_LN_T_MRCC_ J,. Volt 0 D PG, IP J, 0 IO_LP_T_MRCC_ C PG, ION G PG, IOP J, IO_LP_T0_ F0 PG, ION J, IO_LP_T_MRCC_ J,. Volt J, IO_LP_T_DQS_ J, IO_LN_T_MRCC_ J, IO_LN_T0_ 0 FPGA IO within one specific pin group are powered via the same power supply. PG0 and PG power supplies are routed independently and optionally can be powered via the respective expansion pins to support IO signaling levels other than the default. Volt LVTTL. UG0 (v.0) August, 0

35 Evaluation J odd J even A PG, ION J, IO_L0N_T_ B PG, IOP J, IO_L0P_T_ A PG, IO0P A PG, IO0N J, 0 IO_LN_T_DQS_ A PG, ION J, IO_LN_T_ B PG, IOP J, IO_LP_T_ B PG, ION J, 0 IO_LN_T_ C PG, IOP J, IO_LP_T_ G0 PG, IOP J, IO_LP_T_SRCC_ 0 G PG, ION J, IO_LN_T_SRCC_ E0 PG, IO0P J, IO_LP_T_SRCC_ D0 PG, IO0N J, IO_LN_T_SRCC_ D PG, IOP J, IO_LP_T_ D PG, ION J, IO_LN_T_ J, IO_LP_T_DQS_ J odd K PG, IOP F J even J, IO_LP_T_ K PG, ION J, IO_LN_T_ PG, ION J, IO_LN_T_DQS_ G PG, IOP J, IO_LP_T_DQS_ F PG, ION J, IO_LN_T_ G PG, IOP J PG, IOP J, IO_LP_T_SRCC_ H PG, ION J, IO_LN_T_SRCC_ M PG, IOP J, IO_LP_T0_ADP_ 0 L PG, ION J, IO_LN_T0_ADN_ L PG, IOP J, 0 IO_LP_T_AD0P_ L PG, ION J, IO_LN_T_AD0N_ J PG, ION J, IO_LN_T_MRCC_ K PG, IOP J, IO_LP_T_MRCC_ J odd J, IO_LP_T_ J even J0 PG, ION J, IO_L0N_T_DQS_ ADN_ E PG, ION H PG, IOP H PG, ION J, 0 IO_LN_T_ADN_ D PG, ION J, IO_LN_T_DQS_ D PG, ION J, IO_L0N_T_ B PG, ION J, IO_LN_T_ K0 PG, IOP J, IO_LN_T_ F PG, IOP J, IO_LP_T_MRCC_ H PG, ION J, IO_LN_T_MRCC_ J PG, IOP J, IO_LP_T_ADP_ 0 E PG, IOP J, IO_LP_T_DQS_ E PG, IOP J, IO_L0P_T_ C PG, IOP J, IO_LP_T_ UG0 (v.0) August, 0 J, IO_L0P_T_DQS_ ADP_ J, 0 IO_LP_T_

36 Evaluation J odd J even AC PG, IO0N J, 0 IO_LN_T_SRCC_ AB PG, IO0P J, 0 IO_LP_T_SRCC_ AD PG, ION J, 00 IO_LN_T_SRCC_ AC PG, ION PG, IOP J, 0 IO_LP_T0_ W PG, ION J, 0 IO_LN_T0_ PG, IOP J, 0 IO_LP_T_MRCC_ AB PG, ION J, 0 IO_LN_T_MRCC_ Not connected 0 AC PG, IOP J, IO_LP_T_SRCC_ V AA J, IO_LN_T_ AA PG, IO0N J, IO_LN_T_ Y PG, IO0P J, IO_LP_T_ E PG, IOP J, IO_LP_T_SRCC_ E PG, ION J, IO_LN_T_SRCC_ J odd J even AD PG, IOP J, IO_LP_T_DQS_ AE PG, ION AC PG, IOP IO_LP_T_ AD PG, ION U PG0, IO0N J, 0 IO_LN_T_ U PG0, IO0P J, 0 IO_LP_T_ AF PG, IOP J, 0 IO_LP_T_ AF PG, ION J, 0 IO_LN_T_ 0 AB PG, IOP J, Not connected AE PG, IOP J, IO_L0P_T_ AF PG, ION U PG, IOP IO_LP_T0_ V PG, ION J, J, J, IO_LN_T_ IO_LP_T_ J, 0 IO_L0N_T_ J, IO_LN_T0_VREF_ J0 odd J, 0 IO_LN_T_DQS_ J0 even J PG, IOP J, IO_L0P_T_ ADP_ T PG0, IOP J, 0 IO_LP_T_DQS_ AE PG, ION J, IO_LN_T_DQS_ AD PG, IOP J, IO_LP_T_DQS_ V PG0, ION J, IO_LN_T_ V PG0, IOP J, IO_LP_T_ V PG0, ION J IO_LN_T_ U PG0, IOP J, IO_LP_T_ T PG0, ION J, 0 IO_L0N_T_ 0 T PG0, IOP J, IO_L0P_T_ U PG0, IOP J, IO_LP_T_ MRCC_ V PG0, ION J, IO_LN_T_ MRCC_ AF PG, N AE PG, IOP J, 0 IO_LN_T_ UG0 (v.0) August, 0 J, 0 IO_LP_T_

37 Evaluation J odd J even H PG, ION J, IO_L0N_T_ADN_ T PG0, ION J, IO_LN_T_DQS_ T PG0, IOP J, IO_LP_T_ U PG0, ION J, IO_LN_T_ W PG0, ION J, IO_LN_T_ V AC PG0, IOP J, IO_LP_T_DQS_ AD PG0, ION J, IO_LN_T_DQS_ AC PG0, IOP J, IO_LP_T_SRCC_ 0 AD PG0, ION J, 0 IO_LN_T_SRCC_ AB AC W V PG0, IOP J, IO_LP_T0_DQS_ PG0, ION J, IO_LN_T_VREF_ PG0, ION J, 0 IO_LN_T0_DQS_ PG0, IOP J, IO_LP_T_ J odd PG0, IOP J, IO_LP_T_ J even T0 PG0, IOP J, IO_LP_T_DQS_ U0 PG0, ION J, IO_LN_T_DQS_ AB PG0, IO0P J, IO_LP_T_DQS_ AC PG0, IO0N J, IO_LN_T_DQS_ AB PG0, IOP J, IO_LP_T_SRCC_ Y0 AC PG0, ION J, 0 IO_LN_T_SRCC_ PG0, ION J, IO_LN_T_ W0 PG0, IOP J, IO_LP_T_ AB PG0, ION J, IO_LN_T_MRCC_ 0 AA PG0, IOP J, IO_LP_T_MRCC_ AE PG0, IOP AF PG0, ION J, IO_LN_T_ AF0 PG0, ION J, IO_LN_T_ AF PG0, IOP J, IO_LP_T_ J, IO_LP_T_ J odd J even AD0 PG0, IOP J, IO_L0P_T_ AE PG0, IO0P J, IO_LP_T_DQS_ AD PG0, IOP J, IO_LP_T_ Y U PG0, IO0P W AA0 AE0 PG0, ION J, IO_L0N_T_ AF PG0, IO0N J, IO_LN_T_DQS_ AE PG0, ION J, IO_LN_T_ W PG0, IOP J, IO_LP_T_MRCC_ J, IO_LP_T0_ 0 U PG0, IO0N J, IO_LN_T0_ PG0, ION J, IO_LN_T0_ V PG0, IOP J, IO_LP_T0_ PG0, IOP J, IO_LP_T_MRCC_ AB0 PG0, ION PG0, ION J, 0 IO_LN_T_MRCC_ UG0 (v.0) August, 0 J, IO_LN_T_MRCC_

38 Evaluation J odd J even G PG, IOP J, IO_LP_T_ F PG, ION J, IO_LN_T_ H PG, IOP J, IO_LP_T_ G PG, ION J, IO_LN_T_ L PG, IO0N J, IO_LN_T0_ M PG, IOP V PG0, IOP J, 0 IO_L0P_T_ W PG0, ION Y PG0, IOP J, IO_LP_T0_ 0 AA PG0, ION J, IO_LN_T0_ U PG0, IOP J, IO_LP_T_MRCC_ V PG0, ION J, IO_LN_T_MRCC_ AB PG0, ION J, IO_LN_T_ AA PG0, IOP J, IO_LP_T_ H J even PG, ION J, IO_LN_T_ J, IO_L0N_T_ J odd J, IO_LP_T0_ J,. Volt J PG, IOP PG, IO0N J, IO_LN_T0_ J, IO_LP_T_ J,. Volt M M PG, IO0P J, IO_LP_T0_ AA PG0, ION J, IO_LN_T_ AA PG0, IOP J, IO_LP_T_ V PG0, IOP J, IO_LP_T0_ 0 W PG0, ION J, IO_LN_T0_VREF_ Y PG0, ION J, IO_LN_T_SRCC_ Y PG0, IOP J, IO_LP_T_SRCC_ Y PG0, ION J, IO_LN_T0_ W PG0, IOP J, IO_LP_T0_ UG0 (v.0) August, 0

39 Evaluation FPGA GTP data signals All GTP datapins of quad transceivers MGT and MGT are routed to HDMI connectors J, J, J and J. All four diffpairs of a directiongroup are routed to the same HDMI connector. Optionally the signals MGTPRX_N, MGTPRX_P, MGTPTX_N and MGTPTX_P of MGT can be wired to SMA connectors, which aren't fitted by default. All RX signals can be fitted with a passive network to adapt to HDMI voltage levels (see XAPP0, Passive Network ). J MGT RX J MGT TX Pin Signal FPGA Pin Signal FPGA MGTRX_P J D MGTTX_P J D MGTRX_N J C MGTTX_N J C MGTRX0_P J0 B MGTTX0_P J B MGTRX0_N J A MGTTX0_N J A MGTRX_P J B MGTTX_P J D0 MGTRX_N J A MGTTX_N J C0 0 MGTRX_P J D 0 MGTTX_P J B MGTRX_N J C MGTTX_N J A NC NC NC NC MGTRX_SCL J F MGTTX_SCL J J MGTRX_SDA J G MGTTX_SDA J K NET_R_ NC NET_R_ UG0 (v.0) August, 0

40 Evaluation J MGT RX J MGT TX Pin Signal FPGA Pin Signal FPGA MGTRX_P J0 AC MGTTX0_P J AC0 MGTRX_N J AD MGTTX0_N J AD0 MGTRX0_P J AC MGTTX_P J AE MGTRX0_N J AD MGTTX_N J AF MGTRX_P J AE MGTTX_P J AE MGTRX_N J0 AF MGTTX_N J AF 0 MGTRX_P J AE 0 MGTTX_P J AC MGTRX_N J AF MGTTX_N J AD NC NC NC NC MGTRX_SCL J L MGTTX_SCL J M MGTRX_SDA J M MGTTX_SDA J M NET_R_ NC NET_R_ FPGA GTP reference clock signals All reference clock input signals are routed to footprints to place SMA connectors. By default these SMA connectors are not fitted. Reference clock signals from J Pin J Signal FPGA SMA connector MGTCLK0_P F J 0 MGTCLK0_N E J MGTCLK_P F J MGTCLK_N E J MGTCLK0_P AA J MGTCLK0_N AB J MGTCLK_P AA J MGTCLK_N AB J UG0 (v.0) August, 0 0

41 Evaluation Selection between HDMI and SMAconnectors One RX and one TX diffpair of MGT can be routed to SMA connectors. The selection is done with a 00 sized jumperresistor. Figure 0: Select HDMI or SMA connector with jumperresistor Figure 0 illustrates the wiring from J over the resistors to the HDMI and SMAconnectors for signal MGTTX_P. The footprints of R and R share the pad on the Jnet, so only one position can be fitted at once. Resistors for connector selection Pin J FPGA Signal Select HDMI (default) Select SMA C MGTRX_N R R D MGTRX_P R R A MGTTX_N R0 R B MGTTX_P R R UG0 (v.0) August, 0

42 Evaluation SCL and SDA routing to GPIOs Alike the selection between HDMI and SMA connectors, some GPIO signals can be connected to the SCL and SDA pins of the HDMI connectors or to the shrouded headers. By default the GPIOs are connected to the shrouded headers. Figure : Connect GPIO to shrouded header or SDA/SCL As an example for all I²C signals, the wiring for MGTRX_SDA to PG_IO_P is shown in Figure. Net PG_IO_P is wired to the expansion connector J, pin. Net J_ is connected to the shrouded header J, pin. The footprints of R and R share the pad on net PG_IO_P. R is a pullup resistor to.v. By default only R is fitted. Resistors for GPIO pin wiring to HDMI or shrouded header pin FPGA GPIO signal HDMI signal Select HDMI Select Header (default) Header pin Optional pullup J G PG_IO_P MGTRX_SDA R R J R J F PG_IO_N MGTRX_SCL R R J R J K PG_IO_P MGTTX_SDA R R J R0 J J PG_IO_N MGTTX_SCL R R J R J M PG_IO0_P MGTTX_SDA R R J R J M PG_IO0_N MGTTX_SCL R R0 J R J M PG_IO0_P MGTRX_SDA R R J R J L PG_IO0_N MGTRX_SCL R R J R UG0 (v.0) August, 0

43 Evaluation EFM0 on EFM0/B Breakout Board Figure : EFM0/B breakout board connectors UG0 (v.0) August, 0

44 Evaluation Power supply options The EFM0B breakout board supports all power supply options of the EFM0 modules. Connectors J and J are used to select the appropriate power scheme. J0 serves as input for an optional external.0 V power supply. J FPGA power on sequence select Jumper Position Power on sequence USB controlled Instant on Comment Requires selfpowered mode J Power source select Jumper Position Power scheme Power supply Buspowered USB.0 V VBUS Selfpowered External.0 V at J0 J0 External power supply input Pin Signal V_EXT Comment Negative terminal for external power supply Positive terminal for external.0 V power supply External power supply input requirements Power supply input range Minimum current requirement Min. Typ. Max. Units.. V 0 ma FPGA configured with efm0_wrapper design, USB.0 transmission to onboard Gbyte DDRL memory at maximum speed. UG0 (v.0) August, 0

45 Evaluation JTAG and pushbuttons With the pin mm connector J the EFM0B breakout board supports standard XilinxTM JTAG download cables. With the help of the free XilinxTM Vivado WebPack the FPGA and the attached SPI flash can be programmed. Once the SPI flash is programmed with a valid bitstream, reprogramming of the FPGA can be initiated by pressing the pushbutton SW. Figure : SW FPGA Program_B Figure : J FPGA JTAG Figure : SW EZFX Reset Figure : EZUSB FX JTAG Additionally, the EZUSB FX JTAG interface is routed to J, a standard. mm 0pin shrouded header. This allows direct connection of the JTAG/SWD Emulator with USB interface from Segger, which is recommended by Cypress TM. For more details please refer to the FX Programmers Manual within EZUSB FX Software Development Kit. To hard reset EZUSB FX press the pushbutton SW. UG0 (v.0) August, 0

46 Evaluation EZUSB FX GPIO and I²C The general purpose inputs/outputs GPIO and GPIO of the Cypress TM EZUSB FX controller are available at the shrouded header J. The optionally usable watchdog timer inside FX may be optionally supplied by an external khz clock source. The associated CLKIN input is accessible at pin three of connector J. EFM0 uses the I²C EEPROM ATCM0XHM from Atmel to store VID/PID data. To increase available storage for larger firmware files EZUSB FX supports multiple devices of the same size and type sharing the I²C bus. On more information about boot options using the I²C interface please consult AN0 from CypressTM. Figure : FX GPIO signals Figure : EZUSB FX I²C connector Figure : EZUSB FX I²C EEPROM on EFM0 module UG0 (v.0) August, 0

47 Evaluation FPGA inputoutputsignals Except 'IO_LP_T_' (FPGA ball J) located at pin of the EFM0 expansion connector J, which is connected to the green led LED onboard the EFM0/B breakout board, all other FPGA digital IO signals are routed to standard. mm throughhole shrouded headers for easy access. To prevent FPGA bootup from flash you can assert Flash_Inhibit_n by applying jumper J, while test pins are available for the FPGA bank supplies VCCO_PG0, VCCO_PG, VCCO_PG and FPGA status signals Init_B or Done. Figure 0: Green user led on EFM0/B breakout board. Figure : Jumper for Flash_Inhibit_n Figure : FPGA: Init_B and Done signals Figure : FPGA_VCCBAT Figure : VCCO_PG0 Figure : VCCO_PG Figure : VCCO_PG To support signal levels other than the default. V LVTTL, EFM0 pin groups PG0 and PG can optionally be supplied by an external voltage of the required level. BE SURE to remove resistors R0 and/or R0 on EFM0 before applying any voltages to VCCO_PG0 or VCCO_PG. For details about signal levels supported by XilinxTM Series FPGAs, please refer to guide ug. TP for VCCO_PG is for the purpose of measuring VCCO_PG only. DO NOT connect external power supplies. UG0 (v.0) August, 0

48 Evaluation J odd C PG, ION AA PG, ION H B Y PG, ION V Y J, J even J, LP_T_ C PG, IOP J, 0 LN_T_MRCC_ AA PG, IOP J, 0 LP_T_MRCC_ PG, IO0P J, LP_T0_ H PG, IO0N J, 0 LN_T0_ PG, IOP J, L0P_T_ A PG, ION J, L0N_T_ J, LP_T0_ 0 W PG, IOP J, LN_T0_ PG, IOP J, LP_T0_DQS_ V PG, ION J, LN_T0_DQS_ PG, IOP J, 0 LP_T_ AA PG, ION J, LN_T_VREF_ J odd LN_T_VREF_ Pin Group J even G PG, ION J, IO_LN_T0_VREF_ H PG, IOP J, IO_LP_T0_ F PG, IOP J, IO_LP_T0_DQS_ F PG,ION J, IO_LN_T0_DQS_ F PG, ION J, IO_LN_T0_ G PG, IOP J, IO_LP_T0_ B PG, ION J, IO_LN_T_ C PG, IOP J, 0 IO_LP_T_ E PG, IOP J, IO_LP_T_ 0 D PG, ION J, IO_LN_T_ B0 PG, IOP J, 00 IO_LP_T_DQS_ A0 PG, ION J, IO_LN_T_DQS_ G PG, IOP J, 0 IO_LP_T0_ F PG, ION J odd J, 0 IO_LN_T0_ J even D PG, ION J, IO_LN_T_ E PG, IOP J, IO_LP_T_ C PG, IOP J, IO_LP_T_ B PG, ION J, 0 IO_LN_T_ A PG, ION J, IO_LN_T_DQS_ A PG, IOP C D PG, IOP PG, ION J, IO_LN_T_MRCC_ J,. Volt 0 D PG, IP J, 0 IO_LP_T_MRCC_ C PG, ION G PG, IOP J, IO_LP_T0_ F0 PG, ION J, IO_LP_T_MRCC_ J,. Volt J, IO_LP_T_DQS_ J, IO_LN_T_MRCC_ J, IO_LN_T0_ FPGA IO within one specific pin group are powered via the same power supply. PG0 and PG power supplies are routed independently and optionally can be powered via the respective expansion pins to support IO signaling levels other than the default. Volt LVTTL. UG0 (v.0) August, 0

49 Evaluation J odd J even A PG, ION J, IO_L0N_T_ B PG, IOP J, IO_L0P_T_ A PG, IO0P A PG, IO0N J, 0 IO_LN_T_DQS_ A PG, ION J, IO_LN_T_ B PG, IOP J, IO_LP_T_ B PG, ION J, 0 IO_LN_T_ C PG, IOP J, IO_LP_T_ G0 PG, IOP J, IO_LP_T_SRCC_ 0 G PG, ION J, IO_LN_T_SRCC_ E0 PG, IO0P J, IO_LP_T_SRCC_ D0 PG, IO0N J, IO_LN_T_SRCC_ D PG, IOP J, IO_LP_T_ D PG, ION J, IO_LN_T_ J, IO_LP_T_DQS_ J odd K PG, IOP F J even J, IO_LP_T_ K PG, ION J, IO_LN_T_ PG, ION J, IO_LN_T_DQS_ G PG, IOP J, IO_LP_T_DQS_ F PG, ION J, IO_LN_T_ G PG, IOP J PG, IOP J, IO_LP_T_SRCC_ H PG, ION J, IO_LN_T_SRCC_ M PG, IOP J, IO_LP_T0_ADP_ 0 L PG, ION J, IO_LN_T0_ADN_ L PG, IOP J, 0 IO_LP_T_AD0P_ L PG, ION J, IO_LN_T_AD0N_ J PG, ION J, IO_LN_T_MRCC_ K PG, IOP J, IO_LP_T_MRCC_ J odd J, IO_LP_T_ J even J0 PG, ION J, IO_L0N_T_DQS_ ADN_ E PG, ION H PG, IOP H PG, ION J, 0 IO_LN_T_ADN_ D PG, ION J, IO_LN_T_DQS_ D PG, ION J, IO_L0N_T_ B PG, ION J, IO_LN_T_ K0 PG, IOP J, IO_LN_T_ F PG, IOP J, IO_LP_T_MRCC_ H PG, ION J, IO_LN_T_MRCC_ J PG, IOP J, IO_LP_T_ADP_ 0 E PG, IOP J, IO_LP_T_DQS_ E PG, IOP J, IO_L0P_T_ C PG, IOP J, IO_LP_T_ UG0 (v.0) August, 0 J, IO_L0P_T_DQS_ ADP_ J, 0 IO_LP_T_

50 Evaluation J odd J even AC PG, IO0N J, 0 IO_LN_T_SRCC_ AB PG, IO0P J, 0 IO_LP_T_SRCC_ AD PG, ION J, 00 IO_LN_T_SRCC_ AC PG, ION PG, IOP J, 0 IO_LP_T0_ W PG, ION J, 0 IO_LN_T0_ PG, IOP J, 0 IO_LP_T_MRCC_ AB PG, ION J, 0 IO_LN_T_MRCC_ Not connected 0 AC PG, IOP J, IO_LP_T_SRCC_ V AA J, IO_LN_T_ AA PG, IO0N J, IO_LN_T_ Y PG, IO0P J, IO_LP_T_ E PG, IOP J, IO_LP_T_SRCC_ E PG, ION J, IO_LN_T_SRCC_ J odd J even AD PG, IOP J, IO_LP_T_DQS_ AE PG, ION AC PG, IOP IO_LP_T_ AD PG, ION U PG0, IO0N J, 0 IO_LN_T_ U PG0, IO0P J, 0 IO_LP_T_ AF PG, IOP J, 0 IO_LP_T_ AF PG, ION J, 0 IO_LN_T_ 0 AB PG, IOP J, Not connected AE PG, IOP J, IO_L0P_T_ AF PG, ION U PG, IOP IO_LP_T0_ V PG, ION J, J, J, IO_LN_T_ IO_LP_T_ J, 0 IO_L0N_T_ J, IO_LN_T0_VREF_ J0 odd J, 0 IO_LN_T_DQS_ J0 even J PG, IOP J, IO_L0P_T_ ADP_ T PG0, IOP J, 0 IO_LP_T_DQS_ AE PG, ION J, IO_LN_T_DQS_ AD PG, IOP J, IO_LP_T_DQS_ V PG0, ION J, IO_LN_T_ V PG0, IOP J, IO_LP_T_ V PG0, ION J IO_LN_T_ U PG0, IOP J, IO_LP_T_ T PG0, ION J, 0 IO_L0N_T_ 0 T PG0, IOP J, IO_L0P_T_ U PG0, IOP J, IO_LP_T_ MRCC_ V PG0, ION J, IO_LN_T_ MRCC_ AF PG, N AE PG, IOP J, 0 IO_LN_T_ UG0 (v.0) August, 0 J, 0 IO_LP_T_ 0

51 Evaluation J odd J even H PG, ION J, IO_L0N_T_ADN_ T PG0, ION J, IO_LN_T_DQS_ T PG0, IOP J, IO_LP_T_ U PG0, ION J, IO_LN_T_ W PG0, ION J, IO_LN_T_ V AC PG0, IOP J, IO_LP_T_DQS_ AD PG0, ION J, IO_LN_T_DQS_ AC PG0, IOP J, IO_LP_T_SRCC_ 0 AD PG0, ION J, 0 IO_LN_T_SRCC_ AB AC W V PG0, IOP J, IO_LP_T0_DQS_ PG0, ION J, IO_LN_T_VREF_ PG0, ION J, 0 IO_LN_T0_DQS_ PG0, IOP J, IO_LP_T_ J odd PG0, IOP J, IO_LP_T_ J even T0 PG0, IOP J, IO_LP_T_DQS_ U0 PG0, ION J, IO_LN_T_DQS_ AB PG0, IO0P J, IO_LP_T_DQS_ AC PG0, IO0N J, IO_LN_T_DQS_ AB PG0, IOP J, IO_LP_T_SRCC_ Y0 AC PG0, ION J, 0 IO_LN_T_SRCC_ PG0, ION J, IO_LN_T_ W0 PG0, IOP J, IO_LP_T_ AB PG0, ION J, IO_LN_T_MRCC_ 0 AA PG0, IOP J, IO_LP_T_MRCC_ AE PG0, IOP AF PG0, ION J, IO_LN_T_ AF0 PG0, ION J, IO_LN_T_ AF PG0, IOP J, IO_LP_T_ J, IO_LP_T_ J odd J even AD0 PG0, IOP J, IO_L0P_T_ AE PG0, IO0P J, IO_LP_T_DQS_ AD PG0, IOP J, IO_LP_T_ Y U PG0, IO0P W AA0 AE0 PG0, ION J, IO_L0N_T_ AF PG0, IO0N J, IO_LN_T_DQS_ AE PG0, ION J, IO_LN_T_ W PG0, IOP J, IO_LP_T_MRCC_ J, IO_LP_T0_ 0 U PG0, IO0N J, IO_LN_T0_ PG0, ION J, IO_LN_T0_ V PG0, IOP J, IO_LP_T0_ PG0, IOP J, IO_LP_T_MRCC_ AB0 PG0, ION PG0, ION J, 0 IO_LN_T_MRCC_ UG0 (v.0) August, 0 J, IO_LN_T_MRCC_

52 Evaluation J odd J even G PG, IOP J, IO_LP_T_ F PG, ION J, IO_LN_T_ H PG, IOP J, IO_LP_T_ G PG, ION J, IO_LN_T_ L PG, IO0N J, IO_LN_T0_ M PG, IOP V PG0, IOP J, 0 IO_L0P_T_ W PG0, ION Y PG0, IOP J, IO_LP_T0_ 0 AA PG0, ION J, IO_LN_T0_ U PG0, IOP J, IO_LP_T_MRCC_ V PG0, ION J, IO_LN_T_MRCC_ AB PG0, ION J, IO_LN_T_ AA PG0, IOP J, IO_LP_T_ H J even PG, ION J, IO_LN_T_ J, IO_L0N_T_ J odd J, IO_LP_T0_ J,. Volt J PG, IOP PG, IO0N J, IO_LN_T0_ J, IO_LP_T_ J,. Volt M M PG, IO0P J, IO_LP_T0_ AA PG0, ION J, IO_LN_T_ AA PG0, IOP J, IO_LP_T_ V PG0, IOP J, IO_LP_T0_ 0 W PG0, ION J, IO_LN_T0_VREF_ Y PG0, ION J, IO_LN_T_SRCC_ Y PG0, IOP J, IO_LP_T_SRCC_ Y PG0, ION J, IO_LN_T0_ W PG0, IOP J, IO_LP_T0_ UG0 (v.0) August, 0

53 Mechanical drawings Mechanical drawings EFM0 Figure : EFM0 mechanical drawings The four mounting holes of size Mfine located in the corners of the PCB are electrically isolated. The fifth mounting hole located next to the USB.0 type B connector provides access to the USB shielding. UG0 (v.0) August, 0

54 Mechanical drawings EFM0 connector placement Figure : EFM0 connectors on top Figure : EFM0 connectors on bottom UG0 (v.0) August, 0

55 Mechanical drawings EFM0 footprint example Figure 0: EFM0 footprint example Mating connectors SamtecTM part number J & J SamtecTM part number J Mated height QTE000LD QTE000LD.00 mm QTE000LD QTE000LD.00 mm QTE000LD QTE000LD.00 mm QTE000LD QTE000LD.00 mm QTE000LD QTE000LD.00 mm QTE000LD QTE000LD.00 mm UG0 (v.0) August, 0