D2N533B-2G PDRB X DATA SHEET. Memory Module Part Number D2N533B-2G BUFFALO INC. (1/8)

Transcription

1 DATA SHEET Memory Module Part Number D2N533B-2G (1/8)

2 1. Description DDR pin Unbuffered SO-DIMM PC2-4200/CL=4,tRCD=4,tRP=4 2. Module Specification Item Specification Capacity 2GByte Physical Rank(s) 2 Module Organization 256M x 64bit Module Type Unbuffered NonECC Speed Grade PC2-4200/CL=4, trcd=4, trp=4 (266MHz Double Data Rate) PC2-3200/CL=3, trcd=3, trp=3 (200MHz Double Data Rate) Interface SSTL_18 Power Supply Voltage 1.8V±0.1V Burst Lengths 4,8 DRAM Organization 128M x 8bit DDR2 SDRAM PCB Part No. 2SUF28F-A (Qimonda,Nanya DRAM) 2SUE28F-B (others) PCB Layer 8 Layers Contact Tab 200pin GOLD Flash Plating Ni : min 2.00µm / Au : min 0.05µm Serial PD Support 3. Mechanical Design Item Mechanical Design Reference standard Mechanical Design and Pinout DDR2 200Pin SO-DIMM (PDRB X026-xx) Y(PCB Height) Z1 Z2 : ± 0.15mm : Undefined : 3.85mm 4. Block Diagram Item Block Diagram Reference standard Block Diagram DDR2 Unbuffered SO-DIMM(x8bitDRAM 2Rank) (PDRB X056-xx) (2/8)

3 5. Electrical Specifications 5.1 Absolute Maximum Ratings D2N533B-2G Parameter Symbol Value Unit Power supply voltage V CC -0.5~2.3 V Power supply voltage for Output V CCQ -0.5~2.3 V Input and output voltage V IN,V OUT -0.5~2.3 V Operating case surface temperature T C 0~85 C Storage temperature T STG -55~100 C 5.2 Recommended Operating Conditions Parameter Symbol MIN MAX Unit Power supply voltage V CC,V CCQ V Power supply voltage for SPD V CCSPD V Reference Voltage V REF 0.49x V CCQ 0.51x V CCQ V Termination Voltage V TT V REF V REF V DC input logic high voltage V IH (dc) V REF V CCQ +0.3 V DC input logic low voltage V IL (dc) -0.3 V REF V AC input logic high voltage V IH (ac) V REF V AC input logic low voltage V IL (ac) V REF V AC differential input voltage V ID (ac) 0.5 V CCQ +0.6 V AC differential cross point voltage (input) V IX (ac) 0.5*V CCQ *V CCQ V AC differential cross point voltage (output) V OX (ac) 0.5*V CCQ *V CCQ V 5.3 Pin Capacitances CK Input Pin Capacitance /S Input Pin Capacitance CKE Input Pin Capacitance ODT Input Pin Capacitance DQS,/DQS Input,Output Pin Capacitance Parameter Symbol Maximum Pin Capacitance Unit CK0, /CK0 C ICK pf CK1, /CK1 C ICK pf /S0 C IS0 16 pf /S1 C IS1 16 pf CKE0 C ICKE0 16 pf CKE1 C ICKE1 16 pf ODT0 C IODT0 16 pf ODT1 C IODT1 16 pf DQS0~DQS7 C IDQS 8 pf /DQS0~/DQS7 C IDQSN 8 pf DM0~DM7 C IDM 8 pf DQ Input,Output Pin Capacitance DQ0~DQ63 C OUT 8 pf Other Input Pin Capacitance A,BA,/RAS,/CAS,/WE C IN 32 pf (3/8)

4 5.4 D.C. Characters D2N533B-2G Parameter Symbol Value Unit Test Condition Operationg Current for One Bank Active-precharge I CC0 MAX 1440 * ma Operating one bank active precharge current : CKE=high Operationg Current for One Bank Operation I CC1 MAX 1600 * ma Operating one bank active read-precharge current : CKE=high, BL4, AL0 Precharge power-down current : Precharge Power-down Standby Current I CC2P MAX 208 * ma All banks idle, CKE=low Precharge quiet standby current : Precharge Quiet Standby Current I CC2Q MAX 720 * ma All banks idle, CKE=high Precharge standby current : Precharge Standby Current I CC2N MAX 736 * ma All banks idle, CKE=high Active power down current I CC3P-F MAX 480 * ma (Fast PDN Exit) : All banks open, CKE=low, MRS(12)=0 Active Power-down Standby Current Active power down current I CC3P-S MAX 400 * ma (Slow PDN Exit) : All banks open, CKE=low, MRS(12)=1 Active standby current : Active Standby Current I CC3N MAX 1040 * ma All bank open, CKE=high Operating burst write current : Operating Current for Burst Write I CC4W MAX 2320 * ma All banks open, Continuous burst writes, CKE=high, BL4, AL0 Operating Current for Burst Read I CC4R MAX 2280 * ma Operating burst read current : All banks open, Continuous burst reads, CKE=high, BL4, AL0 Auto Refresh Current I CC5 MAX 5120 * ma Burst refresh current : CKE=high Self Refresh Current I CC6 MAX 160 * ma Self refresh current : CK=0V, /CK=0V, CKE 0.2V Operating Current for Four Bank Operation I CC7 MAX 3240 * ma Operating bank interleave read current : All bank interleaving reads, BL4, AL=tRCD-1tCK Input Leakage Current I LI MIN -80 * µa MAX 80 * µa VSS VIN VCC Output High Current I OH MIN * ma V OH = 1,420mV Output Low Current I OL MIN 13.4 * ma V OL = 280mV * : No guarantee against this value. (4/8)

5 5.5 A.C. Timing Characters Parameter Symbol MIN MAX Unit Clock cycle time /CAS Latency = 3 5,000 8,000 /CAS Latency = 4 t CK 3,750 8,000 ps Clock high level width t CH ck Clock low level width t CL ck DQ output access time from CK /CAS Latency = t /CAS Latency = 4 AC ps DQ DM input setup time relative to DQS t DS 100 ps DQ DM input hold time relative to DQS t DH 225 ps Data hold skew factor t QHS 400 ps DQS output access time from CK, /CK t DQSCK ps DQS input high pulse width t DQSH 0.35 ck DQS input low pulse width t DQSL 0.35 ck DQS falling edge to CK setup time t DSS 0.2 ck DQS falling edge to CK hold time t DSH 0.2 ck DQS-DQ skew for DQS and associated DQ signals t DQSQ 300 ps Read preamble t RPRE ck Read postamble t RPST ck Write preamble t WPRE 0.35 ck Write postamble t WPST ck Write command to first DQS latching transition t DQSS WL-0.25 (*1) WL+0.25 (*1) ck Address,command input setup time t IS 250 ps Address,command input hold time t IH 375 ps Active to read or write delay t RCD 15 ns Precharge command period t RP 15 ns Active to precharge command (tck<5,000ps) 45 70k t (tck>=5,000ps) RAS 40 70k ns Active-active/auto refresh clock period (tck<5,000ps) 60 t (tck>=5,000ps) RC 55 ns Active to active command period t RRD 7.5 ns Cas to cas command delay t CCD 2 ck Write recovery time t WR 15 ns Mode register set command cycle time t MRD 2 ck Minimum time clocks remains ON after CKE asynchronously drops low t DELAY t IS +t CK +t IH ns Average periodic refresh interval t REFI 7.8 µs Refresh to active/refresh command time t RFC k ns Exit self refresh to a non-read command t XSNR t RFC +10 ns Exit self refresh to a read command t XSRD 200 ck Exit prechatge power down to any non-read command t XP 2 ck Exit active power down to read command t XARD 2 ck Exit active power down to read command (Slow exit, Lower power) t XARDS 6-AL (*2) ck CKE minimum pulse width (high and low pulse width) t CKE 3 ck ODT turn-on delay t AOND 2 ck ODT turn-on t AON t AC (Min) t AC (Max)+1 ns ODT turn-on (Power-Down mode) t AONPD t AC (Min)+2 +t AC (Max)+1 ns ODT turn-off delay t AOFD 2.5 ck ODT turn-off t AOF t AC (Min) t AC (Max)+0.6 ns ODT turn-off (Power-Down mode) t AOFPD t AC (Min)+2 2.5t CK +t AC (Max)+1 ns ODT to power down entry latency t ANPD 3 ck ODT power down exit latency t AXPD 8 ck *1 : WL=Write Latency *2 : AL=Additive Latency 2t CK (5/8)

6 6. Serial Presence Detect (SPD) Data Structure Byte No. Function Hex Value Function Supported 0 Defines # of bytes written into serial memory at module manufacturer Bytes 1 Total # of bytes of SPD memory device Bytes 2 Fundamental memory type (FPM, EDO, SDRAM..) 08 DDR2-SDRAM 3 # of row addresses on this assembly 0E 14 4 # Column Addresses on this assembly 0A 10 5 # Module Ranks on this assembly 61 2Rank 6 Data Width of this assembly 40 64bits 7 Reserved 00 Undefined 8 Voltage interface standard of this assembly 05 SSTL-18 9 SDRAM Cycle time (highest CAS latency) 3D 3,750ps (CL=4) 10 SDRAM Access from Clock (highest CAS latency) ps (CL=4) 11 DIMM Configuration type (non-parity, ECC) 00 NON-ECC 12 Refresh Rate/Type µs 13 Primary SDRAM Width 08 x8 bit 14 Error Checking SDRAM width 00 Non Use 15 Reserved 00 Reserved 16 Burst Lengths Supported 0C Burst Lengths (4,8) 17 # of Banks on Each SDRAM Device 08 8Bank 18 CAS# Latency 18 CAS Latency =4,3 19 Reserved 00 Undefined 20 DIMM Type Information 04 SO-DIMM 21 SDRAM Module Attributes 00 Normal 22 SDRAM Device Attributes: General 01 Weak drive support 23 SDRAM Cycle time (2nd highest CAS latency) 50 5,000ps(CL=3) 24 SDRAM Access from Clock (2nd highest CAS latency) ps(CL=3) 25 SDRAM Cycle time (3rd highest CAS latency) 00 N/A (CL=2) 26 SDRAM Access from Clock (3rd highest CAS latency) 00 N/A (CL=2) 27 Minimum Row Precharge Time (trp) 3C 15 ns 28 Row Activate to Row Activate Min. (trrd) 1E 7.5 ns 29 RAS to CAS Delay Min (trcd) 3C 15 ns 30 Minimum RAS Pulse Width (trasmin) 2D 45ns 31 Density of each rank on module 01 1GB 32 Command and Address signal input setup time ps 33 Command and Address signal input hold time ps 34 Data signal input setup time ps 35 Data signal input hold time ps 36 Write recovery time (twr) 3C 15ns 37 Internal Write to Read command delay (twtr) 1E 7.5ns 38 Internal Read to Precharge command delay (trtp) 1E 7.5ns 39 Memory Analysis Probe charactristics 00 TBD 40 Extension of Byte41 trc and Byte42 trfc 06 Extension of Byte41,42 41 SDRAM Device Minimum Active to Active/Auto Refresh Time(tRC) 3C 60ns 42 SDRAM Device Minimum Auto-Refresh to Active/Auto-Refresh(tRFC) 7F 127.5ns 43 SDRAM Device Maximum device cycle time(tckmax) 80 8,000ps 44 SDRAM Device Maximum skew between DQS and DQ signals(tdqsq) 1E 300ps 45 DDR SDRAM Device Maximum Read DataHold Skew Factor(tQHS) ps 46 PLL Relock Time 00 Undefined Superset Information (may be used in future) 00 Reserved 62 SPD Data Revision Code 10 Rev Checksum for bytes 0-62 A7 Checksum Manufacturer s JEDEC ID code per JEP-106 7F BUFFALO 72 Manufacturing Location Manufacturer s Part Number 20 BLANK Revision Code 00 Undefined Manufacturing Date Undefined Assembly Serial Number Undefined Manufacturer Specific Data Undefined 128+ Unused storage locations Undefined (6/8)

7 7. Packing/Label Specification Item Packing/Label Specification Reference standard Packing/Label Specification for SO-DIMM (PDRB X063-xx) (7/8)

8 8. Revision History Rev. Date Changes Issued 01 Mar D.Hamatake (D03) Changed D.C. Characters 02 Jul I CC5(MAX) : (ma) Added approved PCB M.Goto (D05) 2SUF28F-A (8/8)