V436632S24VD 3.3 VOLT 32M x 64 HIGH PERFORMANCE PC133 UNBUFFERED SDRAM MODULE

Transcription

1 3.3 VOLT 32M x 64 HIGH PERFORMAE PC133 UNBUFFERED SDRAM MOLE Features JEDEC-standard 168 pin, Dual Inline Memory Module (DIMM) Serial Presence Detect (SPD) with E 2 PROM Nonbuffered Fully PC Board Layout Compatible to INTEL S Rev 1.0 Module Specification Single +3.3V (± 0.3V) Power Supply All Device Pins are LVTTL Compatible 8192 Refresh Cycles every 64 ms Self-Refresh Mode Internal Pipelined Operation; Column Address can be changed every System Clock Programmable Burst Lengths: 1, 2, 4, 8 Auto Precharge and Precharge all Banks by A Data Mask Function by Mode Register Set Programming Programmable (CAS Latency: 2, 3 Clocks) 54-Pin TSOPII component packaging Description The memory module is organized 33,554,432 x 64 bits in a 168 pin dual in line memory module (DIMM). The 32M x 64 unbuffered DIMM uses 8 ProMOS 32M x 8 SDRAM. The x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. Part Number V436632S24VXXX-75PC V436632S24VXXX-75 V436632S24VXXX-PC Speed Grade -75PC, CL=2,3 (133 MHz) -75, CL=3 (133 MHz) -PC, CL=2,3 (0 MHz) Configuration 32M x 64 32M x 64 32M x 64 1

2 Part Number Information V S 2 4 V D I W DATA WIDTH DATA PCB TYPE ProMOS & COMP DENSITY DEPTH REFRESH G : GOLD_LEAD PLATING 65 X64 using 128M 16 : 16Mb RATE W : GOLD_RoHS OTHER 66 X64 using 256M 32 : 32 Mb 0: 4K COMPONENT Y : GOLD_GREEN PC: CL2 67 X64 using 512M 64 : 64 Mb 1: 2K REV LEVEL L : LOW PROFILE_LEAD PLATING BLANK: CL3 TYPE 68 X64 using 1G 2: 8K X : LOW PROFILE_RoHS 4 : SDRAM 69 X64 using 2G 3: 1K Z : LOW PROFILE_GREEN 72 X72 using 64M I/O INTERFACE 73 X72 using 128M BANKS V: LVTTL SPEED 74 X72 using 256M BLANK4 Banks : 0MHz VOLTAGE 75 X72 using 512M 2 : 2 Banks COMPONENT PKG 75 : 133MHz 3 : 3.3V 76 X72 using 1G 4 : 4 Banks LEAD RoHS GREEN PACKAGE 77 X72 using 2G 8 : 8 Banks PLATING DESCRIPTION T E I TSOP MOLE TYPE & COMP WIDTH S F J 60-Ball FBGA BASED ON X4 X16 X8 C G K 54-Ball FBGA 168PIN DIMM D N Die-stacked TSOP H L M BUFFERED Z R P Die-stacked FBGA 168PIN DIMM Q R S * RoHS: Restriction of Hazardous Substances UNBUFFERED * Green: RoHS-compliant and Halogen-free 144PIN SO-DIMM X Y Z 144PIN Micro-DIMM 168PIN REGISTERED C A D E 2

3 Pin Configurations (Front Side/Back Side) Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 CBO* CB1* A0 A2 A4 A6 A8 A(AP) BA1 CLK CB2* CB3* I/O17 I/O I/O19 I/O20 I/O21 CKE1 I/O22 I/O23 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I/O32 CLK2 WP SDA SCL I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 I/O48 CB4* CB5* CAS RAS A1 A3 A5 A7 A9 BA0 A11 CLK1 A12 CKE CB6* CB7* I/O49 I/O I/O51 I/O52 I/O53 I/O54 I/O55 I/O56 I/O57 I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 I/O64 CLK3 SA0 SA1 SA2 Notes: * These pins are not used in this module. Pin Names A0A12 I/O1I/O64 RAS CAS BA0, BA1 CKE0, CKE1 03 CLK0CLK3 07 SCL Address Inputs Data Inputs/Outputs Row Address Strobe Column Address Strobe Read/Write Input Bank Selects Clock Enable Chip Select Clock Input Data Mask Power (+3.3 Volts) Ground Clock for Presence Detect SDA SA0A2 CB0CB7 Serial Data OUT for Presence Detect Serial Data IN for Presence Detect Check Bits (x72 Organization) No Connection Don t Use 3

4 Block Diagram 0 0 I/O1I/O8 1 I/O9I/O16 I/O1I/O8 I/O1I/O8 D0 D1 4 I/O40I/O33 5 I/O48I/O41 I/O1I/O8 I/O1I/O8 D4 D5 2 2 I/O17I/O24 3 I/O25I/O32 I/O1I/O8 I/O1I/O8 D2 D3 6 I/O49I/O56 7 I/O57I/O64 I/O1I/O8 I/O1I/O8 D6 D7 E 2 PROM SPD (256 WORD X 8 BITS) SCL0 SA2 SA1 SA0 47K SDA WP CKE0 RAS CAS A(11:0) BA0, BA1 CKE: SDRAM D0-D7 RAS: SDRAM D0-D7 CAS: SDRAM D0-D7 : SDRAM D0-D7 A(11:0): SDRAM D0-D7 BA0, BA1: SDRAM D0-D7 CLOCK WIRING CLOCK INPUT LOAD CLK0 5 SDRAM CLK1 Termination CLK2 4 SDRAMS +3.3pF Cap CLK3 Termination V CC V SS C0-C17 D0-D7 D0-D7 4

5 Serial Presence Detect Information A serial presence detect storage device E 2 PROM is assembled onto the module. Information about the module configuration, speed, etc. is SPD-Table written into the E 2 PROM device during module production using a serial presence detect protocol (I 2 C synchronous 2-wire bus) Byte Number Function Described SPD Entry Value Hex Value -75PC -75 -PC 0 Number of SPD bytes Total bytes in Serial PD Memory Type SDRAM Number of Row Addresses (without BS bits) 13 0D 0D 0D 4 Number of Column Addresses (for x8 SDRAM) 0A 0A 09 5 Number of DIMM Banks Module Data Width Module Data Width (continued) Module Interface Levels LVTTL SDRAM Cycle Time at CL=3 7.5 ns/.0 ns A0 SDRAM Access Time from Clock at CL=3 5.4 ns/6.0 ns Dimm Config (Error Det/Corr.) none Refresh Rate/Type Self-Refresh, 7.8µs SDRAM width, Primary x Error Checking SDRAM Data Width n/a / x Minimum Clock Delay from Back to Back Random Column Address t ccd = 1 CLK Burst Length Supported 1, 2, 4, 8 0F 0F 0F 17 Number of SDRAM Banks Supported CAS Latencies CL = 2, Latencies Latency = Latencies WL = SDRAM DIMM Module Attributes Non Buffered/Non Reg SDRAM Device Attributes: General Vcc tol ± % 0E 0E 0E 23 Minimum Clock Cycle Time at CAS Latency = ns /.0 ns 75 A0 A0 24 Maximum Data Access Time from Clock for CL = ns/ 6.0 ns Minimum Clock Cycle Time at CL = 1 Not Supported Maximum Data Access Time from Clock at CL = 1 Not Supported Minimum Row Precharge Time 15 ns/20 ns 0F Minimum Row Active to Row Active Delay t RRD 14 ns/15 ns/16 ns 0E 0F 29 Minimum RAS to CAS Delay t RCD 15 ns/20 ns 0F Minimum RAS Pulse Width t RAS 42 ns/45 ns 2A 2D 2D 5

6 SPD-Table Byte Number Function Described SPD Entry Value Hex Value -75PC -75 -PC 31 Module Bank Density (Per Bank) 256 MByte SDRAM Input Setup Time 1.5 ns/2.0 ns SDRAM Input Hold Time 0.8 ns/1.0 ns SDRAM Data Input Setup Time 1.5 ns SDRAM Data Input Hold Time 0.8 ns Superset Information (May be used in Future) SPD Revision Revision 2/ Checksum for Bytes 0-62 FD 42 9D 64 Manufacturer s JEDEC ID Code ProMOS Manufacturer s JEDEC ID Code (cont.) Manufacturing Location 01 = US, 02 = Taiwan, 05 = China, 0A = S-CH Module Part Number (ASCII) PCB Identification Code Current PCB Revision 93 Assembly Manufacturing Date (Year) Binary Coded year (BCD) 94 Assembly Manufacturing Date (Week) Binary Coded week (BCD) Assembly Serial Number byte 95 = LSB byte 98 = MSB Reserved Intel Specification for Frequency 133MHz Supported frequency 128+ Unused Storage Location

7 DC Characteristics T A = 0 C to 70 C; V SS = 0 V; V DD, V DDQ = 3.3V ± 0.3V Limit Values Symbol Parameter Min. Max. Unit V IH Input High Voltage 2.0 V CC +0.3 V V IL Input Low Voltage V V OH Output High Voltage (I OUT = 4.0 ma) 2.4 V V OL Output Low Voltage (I OUT = 4.0 ma) 0.4 V I I(L) I O(L) Input Leakage Current, any input (0 V < V IN < 3.6 V, all other inputs = 0V) Output leakage current (DQ is disabled, 0V < V OUT < V CC ) µa µa Capacitance T A = 0 C to 70 C; V DD = 3.3V ± 0.3V, f = 1 MHz Symbol Parameter Limit Values Unit C I1 Input Capacitance (A0 to A11, RAS, CAS, ) 85 pf C I2 Input Capacitance (0-3) 30 pf C ICL Input Capacitance (CLK0-CLK3) 22 pf C I3 Input Capacitance (CKE0, CKE1) 50 pf C I4 Input Capacitance (0-7) 20 pf C IO Input/Output Capacitance (I/O1-I/064) 20 pf C SC Input Capacitance (SCL, SA0-2) 8 pf C SD Input/Output Capacitance 18 pf Absolute Maximum Ratings Parameter Max. Units Voltage on VDD Supply Relative to V SS -1 to 4.6 V Voltage on Input Relative to V SS -1 to 4.6 V Operating Temperature 0 to +70 C Storage Temperature -55 to 125 C Power Dissipation 6.5 W 7

8 Standby and Refresh Currents 1 T A = 0 C to 70 C, V CC = 3.3V ± 0.3V Symbol Parameter Test Conditions -75PC/75 -PC Unit Note I CC 1 Operating Current Burst length = 4, CL = 3 t RC > = t RC (min), t CK > = t CK (min), IO = 0 ma 2 Bank Interleave Operation ma 1,2 I CC 2P Precharged Standby Current in PowerDown Mode CKE< = V IL (max), t CK > = t CK (min) ma I CC 2N Precharged Standby Current in Non-Power Down Mode CKE> = V IH (min), t CK > = t CK (min), Input changed once in 3 cycles ma = High I CC 3P Active Standby Current in Power Down Mode CKE< = V IL (max), t CK > = t CK (min) ma I CC 3N Active Standby Current in Non-Power Down Mode CKE> = V IH (min), t CK > = t CK (min), Input changed one time ma = High I CC 4 Burst Operating Current t RC = Infinite, CL = 3, t CK > = t CK (min), IO = 0 ma 2 Banks Activated ma 1, 2 I CC 5 Auto Refresh Current t RC >= t RC (min) ma 1,2 I CC 6 Self Refresh Current CKE = <0,2 V Standard ma 1,2 L-version

9 AC Characteristics 3,4 T A = 0 to 70 C; V SS = 0V; V CC = 3.3V ± 0.3V, t T = 1 ns Limit Values -75PC -75 -PC # Symbol Parameter MIN MAX MIN MAX MIN MAX Unit Note Clock and Clock Enable 1 t CK Clock Cycle Time CAS Latency = 3 CAS Latency = ns ns 2 f CK System frequency CAS Latency = 3 CAS Latency = MHz MHz 3 t AC Clock Access Time CAS Latency = 3 CAS Latency = ns ns 4,5 4 t CH Clock High Pulse Width ns 6 5 t CL Clock Low Pulse Width ns 6 6 t Input Setup time ns 7 7 t CH Input Hold Time ns 7 8 t CKSP CKE Setup Time (Power down mode) ns 8 9 t CKSR CKE Setup Time (Self Refresh Exit) ns 9 t T Transition time (rise and fall) ns Common Parameters 11 t RCD RAS to CAS delay ns 12 t RC Cycle Time k k k ns 13 t RAS Active Command Period ns 14 t RP Precharge Time ns 15 t RRD Bank to Bank Delay Time ns 16 t CCD CAS to CAS delay time (same bank) CLK Refresh Cycle 17 t SREX Self Refresh Exit Time ns 9 18 t REF Refresh Period (8192 cycles) ms 8 Read Cycle 19 t OH Data Out Hold Time ns 4 20 t LZ Data Out to Low Impedance Time ns 21 t HZ Data Out to High Impedance Time ns 22 t DQZ Data Out Disable Latency CLK Write Cycle 23 t DPL Data input to Precharge (write recovery) CLK 24 t DAL Data In to Active/refresh CLK t DQW Write Mask Latency CLK 9

10 Notes: 1. The specified values are valid when addresses are changed no more than once during t CK (min.) and when No Operation commands are registered on every rising clock edge during t RC (min). Values are shown per module bank. 2. The specified values are valid when data inputs (DQ s) are stable during t RC (min.). 3. All AC characteristics are shown for device level. An initial pause of 0 µs is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have V IL = 0.4V and V IH = 2.4V with the timing referenced to the 1.4V crossover point. The transition time is measured between V IH and V IL. All AC measurements assume t T = 1 ns with the AC output load circuit shown. Specific tac and toh parameters are measured with a 50 pf only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0V. tch V CLOCK tsetup thold tcl t T 2.4V 0.4V I/O Z=50 Ohm 50 Ohm 50 pf INPUT 1.4V tlz tac toh tac I/O 50 pf OUTPUT 1.4V Measurement conditions for tac and toh thz 5. If clock rising time is longer than 1 ns, a time (t T /2-0.5) ns has to be added to this parameter. 6. Rated at 1.5V 7. If t T is longer than 1 ns, a time (t T -1) ns has to be added to this parameter. 8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to wake-up the device. 9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to t RC is satisfied once the Self Refresh Exit command is registered.. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 11. t DAL is equivalent to t DPL + t RP.

11 Package Diagram L-DIM SDRAM 168-Pin DIMMModule Package All measurements in mm (2.54 max) ± A B D ± ± Detail A Detail B Detail C RADIUS Tolerances: ± (0.13) unless otherwise specified. 11

12 Label Information Module Density Part Number ProMOS TECHNOLOGIES V436632S24VXXX-XX 256MB SDR-XXXMHz - CLX PCXXXU-XXX-542-A XXXX-XXXXXXX Assembly in Taiwan CAS Latency Criteria of PC0 or PC133 DIMM manufacture date code PCXXX U UNBUFFERED DIMM XXX 54 2 A Gerber file Intel PC0 x8 Based C L = 3 or 2 (CLK) t RCD = 3 or 2 (CLK) t RP = 3 or 2 (CLK) t AC = 5.4ns JEDEC SPD Revision 2 12

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