256MB 144-PIN UNBUFFERED SDRAM SODIMM 32M X VOLT

Transcription

1 256MB 144-PIN UNBUFFERED SDRAM SODIMM 32M X VOLT Features JEDEC-standard 144 pin, Small-Outline, Dual in line Memory Module (SODIMM) Serial Presence Detect with E 2 PROM Fully Synchronous, All Signals Registered on Positive Edge of System Clock Single +3.3V (± 0.3V) Power Supply All Device Pins are LVTTL Compatible 8192 Refresh Cycles every 64 ms Self-Refresh Mode Internal Pipelined Operation; Column Address can be changed every System Clock Programmable Burst Lengths: 1, 2, 4, 8 Auto Precharge and Piecharge all Banks by A10 Data Mask Function by DQM Mode Register Set Programming Programmable (CAS Latency: 2, 3 Clocks) TSOP component package Description The memory module is organized 33,554,432 x 64 bits in a 144 pin SODIMM. The 32M x 64 memory module uses 8 ProMOS 16M x 16 SDRAM. The x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. Part Number XX-75PC XX-75 XX-10PC Speed Grade -75PC, CL=2,3 (133 MHz) -75, CL=3 (133 MHz) -10PC, CL=2,3 (100 MHz) Configuration 32M x 64 32M x 64 32M x 64 32M x 8 32M x 8 32M x 8 32M x Pin 2 on Backside Pin 144 on Backside Rev.1.2 June

2 Part Number Information V Y 2 4 V D I W DATA WIDTH DATA PCB TYPE ProMOS & COMP DENSITY DEPTH REFRESH G : GOLD_LEAD PLATING 65 X64 using 128M 16 : 16Mb RATE W : GOLD_RoHS OTHER 66 X64 using 256M 32 : 32 Mb 0: 4K COMPONENT Y : GOLD_GREEN PC: CL2 67 X64 using 512M 64 : 64 Mb 1: 2K REV LEVEL L : LOW PROFILE_LEAD PLATING BLANK: CL3 TYPE 68 X64 using 1G 2: 8K X : LOW PROFILE_RoHS 4 : SDRAM 69 X64 using 2G 3: 1K Z : LOW PROFILE_GREEN 72 X72 using 64M I/O INTERFACE 73 X72 using 128M BANKS V: LVTTL SPEED 74 X72 using 256M BLANK4 Banks 10 : 100MHz VOLTAGE 75 X72 using 512M 2 : 2 Banks COMPONENT PKG 75 : 133MHz 3 : 3.3V 76 X72 using 1G 4 : 4 Banks LEAD RoHS GREEN PACKAGE 77 X72 using 2G 8 : 8 Banks PLATING DESCRIPTION T E I TSOP MODULE TYPE & COMP WIDTH S F J 60-Ball FBGA BASED ON X4 X16 X8 C G K 54-Ball FBGA 168PIN DIMM D N Die-stacked TSOP H L M BUFFERED Z R P Die-stacked FBGA 168PIN DIMM Q R S * RoHS: Restriction of Hazardous Substances UNBUFFERED * Green: RoHS-compliant and Halogen-free 144PIN SO-DIMM X Y Z 144PIN Micro-DIMM 168PIN REGISTERED C A D E Rev. 1.2 June

3 Pin Configurations (Front Side/Back Side) Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back DQ0 DQ32 DQ1 DQ33 DQ2 DQ34 DQ3 DQ35 DQ4 DQ36 DQ5 DQ37 DQ6 DQ38 DQ7 DQ39 DQMB0 DQMB DQMB1 DQMB5 A0 A3 A1 A4 A2 A5 DQ8 DQ40 DQ9 DQ41 DQ10 DQ42 DQ11 DQ43 DQ12 DQ DQ13 DQ45 DQ14 DQ46 DQ15 DQ47 CLK0 CKE0 RAS CAS CKE1 0 A CLK1 DQ16 DQ48 DQ17 DQ49 DQ18 DQ50 DQ19 DQ51 DQ20 DQ52 DQ21 DQ DQ22 DQ54 DQ23 DQ55 A6 A7 A8 BA0 A9 BA1 A10 A11 DQMB2 DQMB6 DQMB3 DQMB DQ24 DQ56 DQ25 DQ57 DQ26 DQ58 DQ27 DQ59 DQ28 DQ60 DQ29 DQ61 DQ30 DQ62 DQ31 DQ63 SDA SCL Note: 1. RAS, CAS, CASx, x are active low signals. Pin Names A0A12, BA0, BA1 DQ0DQ63 RAS CAS 0, 1 DQMB0DQMB7 CKE0, CKE1 CLK0, CLK1 SDA SCL Address, Bank Select Data Inputs/Outputs Row Address Strobes Column Address Strobes Write Enable Chip Select Output Enable Clock Enable Clock Serial Input/Output Serial Clock Power Supply Ground No Connect (Open) Rev. 1.2 June

4 Block Diagram 0 DQMB0 DQ07 DQMB4 DQ3239 U0 U2 DQMB1 DQ815 DQMB5 DQ4047 DQMB2 DQ1623 DQMB6 DQ4855 U1 U3 DQMB3 DQ2431 DQMB7 DQ DQMB0 DQ07 DQMB4 DQ3239 U4 U6 DQMB1 DQ815 DQMB5 DQ4047 DQMB2 DQ1623 DQMB6 DQ4855 U5 U7 DQMB3 DQ2431 DQMB7 DQ5663 A0A12, BA0, BA1 CKE0 CKEI RAS CAS U0U7 U0U7 U0U3 U4U7 U0U7 U0U7 CLK0 CLKI 0Ω 0Ω SPD U0, U1 U2, U3 U4, U5 U6, U7 SCL A0 A1 A2 SDA Note: All resistors are 10 Ohms Rev. 1.2 June

5 Serial Presence Detect Information A serial presence detect storage device - E 2 PROM - is assembled onto the module. Information about the module configuration, speed, etc. is written into the SPD-Table for modules: E 2 PROM device during module production using a serial presence detect protocol (I 2 C synchronous 2-wire bus) Byte Number Function Described SPD Entry Value Hex Value -75PC PC 0 Number of SPD bytes Total bytes in Serial PD Memory Type SDRAM Number of Row Addresses (without BS bits) 13 0D 0D 0D 4 Number of Column Addresses ( x16 SDRAM) Number of DIMM Banks Module Data Width Module Data Width (continued) Module Interface Levels LVTTL SDRAM Cycle Time at CL=3 7.5 ns/10.0 ns A0 10 SDRAM Access Time from Clock at CL=3 5.4 ns/10.0ns Dimm Config (Error Det/Corr.) none Refresh Rate/Type Self-Refresh, 7.8 µs SDRAM width, Primary x Error Checking SDRAM Data Width n/a / x Minimum Clock Delay from Back to Back Random Column Address t ccd = 1 CLK Burst Length Supported 1, 2, 4, 8, page 8F 8F 8F 17 Number of SDRAM Banks Supported CAS Latencies CL = 2 / Latencies Latency = Latencies WL = SDRAM DIMM Module Attributes Non Buffered/Non Reg SDRAM Device Attributes: General Vcc tol ± 10% 0E 0E 0E 23 Minimum Clock Cycle Time at CAS Latency = ns/10.0ns 75 A0 A0 24 Maximum Data Access Time from Clock for CL = 2 5.4ns/6.0ns Minimum Clock Cycle Time at CL = 1 Not Supported Maximum Data Access Time from Clock at CL = 1 Not Supported Minimum Row Precharge Time 15 ns / 20 ns 0F Minimum Row Active to Row Active Delay t RRD 14 ns/15 ns/16 ns 0E 0F Minimum RAS to CAS Delay t RCD 15 ns/20 ns 0F Rev. 1.2 June

6 SPD-Table for modules: (Continued) Byte Number Function Described SPD Entry Value Hex Value -75PC PC 30 Minimum RAS Pulse Width t RAS 42 ns/45 ns 2A 2D 2D 31 Module Bank Density (Per Bank) 128 Mbyte SDRAM Input Setup Time 1.5 ns/2.0 ns SDRAM Input Hold Time 0.8 ns/ 1.0 ns SDRAM Data Input Setup Time 1.5 ns/2.0 ns SDRAM Data Input Hold Time 0.8 ns/1.0 ns Superset Information (May be used in Future) Minimum Active to Auto-Refresh Time t RC 60 ns 3C 3C 3C Reserved SPD Revision Revision 2 / Checksum for Bytes 0-62 A1 E Manufacturer s JEDEC ID Code ProMOS Manufacturer s JEDEC ID Code (cont.) Manufacturing Location Taiwan / China / S-CH / Malaysia 02 / 05 / 0A / Module Part Number (ASCII) PCB Identification Code Current PCB Revision 93 Assembly Manufacturing Date (Year) Binary Coded year (BCD) 94 Assembly Manufacturing Date (Week) Binary Coded week (BCD) Assembly Serial Number byte 95 = LSB, byte 98 = MSB Reserved Intel Specification for Frequency 100MHz SDRAM Component & Clock Detail CF CF CF 128+ Unused Storage Location Rev. 1.2 June

7 DC Characteristics T A = 0 C to 70 C; V SS = 0 V; V DD, V DDQ = 3.3V ± 0.3V Limit Values Symbol Parameter Min. Max. Unit V IH Input High Voltage 2.0 V CC +0.3 V V IL Input Low Voltage V V OH Output High Voltage (I OUT = 4.0 ma) 2.4 V V OL Output Low Voltage (I OUT = 4.0 ma) 0.4 V I I(L) I O(L) Input Leakage Current, any input (0 V < V IN < 3.6 V, all other inputs = 0V) Output leakage current (DQ is disabled, 0V < V OUT < V CC ) µa µa Capacitance T A = 0 C to 70 C; V DD = 3.3V ± 0.3V, f = 1 MHz Symbol Parameter Limit Values (Max.) Unit C I1 Input Capacitance (A0 to A11, RAS, CAS, ) 40 pf C I2 Input Capacitance (0, I) 25 pf C ICL Input Capacitance (CLK0-CLK1) 28 pf C I3 Input Capacitance (CKE0, CKEI) 20 pf C I4 Input Capacitance (DQMB0-DQMB7) 10 pf C SC Input Capacitance (SCL, SA0-2) 8 pf C IO Input/Output Capacitance 18 pf Absolute Maximum Ratings Parameter Max. Units Voltage on Supply Relative to V SS -1 to 4.6 V Voltage on Input Relative to V SS -1 to 4.6 V Operating Temperature -40 to +85 C Storage Temperature -55 to 125 C Power Dissipation 5.3 W Rev. 1.2 June

8 Standby and Refresh Currents 1 T A =0 C to 70 C, V CC = 3.3V ± 0.3V Symbol Parameter Test Conditions 75PC/75 10PC Unit Note I CC 1 Operating Current Burst length = 4, CL = 3 t RC > = t RC (min), t CK > = t CK (min), IO = 0 ma 2 Bank Interleave Operation ma 1,2 I CC 2P Precharged Standby Current in Power Down Mode CKE< = V IL (max), t CK > = t CK (min) ma I CC 2N Precharged Standby Current in Non-Power Down Mode CKE> = V IH (min), t CK > = t CK (min), Input changed once in 3 cycles ma = High I CC 3P Active Standby Current in Power Down Mode CKE< = V IL (max), t CK > = t CK (min) ma I CC 3N Active Standby Current in Non-Power Down Mode CKE> = V IH (min), t CK > = t CK (min), Input changed one time ma = High I CC 4 Burst Operating Current Burst length = Full Page, t RC = Infinite, CL = 3, t CK > = t CK (min), IO = 0 ma 2 Banks Activated ma 1, 2 I CC 5 Auto Refresh Current t RC >= t RC (min) ma 1,2 I CC 6 Self Refresh Current CKE = <0.2 V Standard ma 1,2 L-Version Rev. 1.2 June

9 AC Characteristics 3,4 T A = 0 to 70 C; V SS = 0V; V CC = 3.3V ± 0.3V, t T = 1 ns Limit Values -75PC PC # Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Note Clock and Clock Enable 1 t CK Clock Cycle Time CAS Latency = 3 CAS Latency = ns ns 2 f CK System frequency CAS Latency = 3 CAS Latency = MHz MHz 3 t AC Clock Access Time CAS Latency = 3 CAS Latency = ns ns 4,5 4 t CH Clock High Pulse Width ns 6 5 t CL Clock Low Pulse Width ns 6 6 t Input Setup time ns 7 7 t CH Input Hold Time ns 7 8 t CKSP CKE Setup Time (Power down mode) ns 8 9 t CKSR CKE Setup Time (Self Refresh Exit) ns 9 10 t T Transition time (rise and fall) ns Common Parameters 11 t RCD RAS to CAS delay ns 12 t RC Cycle Time ns 13 t RAS Active Command Period k k k ns 14 t RP Precharge Time ns 15 t RRD Bank to Bank Delay Time ns 16 t CCD CAS to CAS delay time (same bank) CLK Refresh Cycle 17 t SREX Self Refresh Exit Time ns 9 18 t REF Refresh Period (8192 cycles) ms 8 Read Cycle 19 t OH Data Out Hold Time ns 4 20 t LZ Data Out to Low Impedance Time ns 21 t HZ Data Out to High Impedance Time ns t DQZ DQM Data Out Disable Latency CLK Write Cycle 23 t DPL Data input to Precharge (write recovery) CLK 24 t DAL Data In to Active/refresh CLK t DQW DQM Write Mask Latency CLK Rev. 1.2 June

10 Notes: 1. The specified values are valid when addresses are changed no more than once during t CK (min.) and when No Operation commands are registered on every rising clock edge during t RC (min). Values are shown per module bank. 2. The specified values are valid when data inputs (DQ s) are stable during t RC (min.). 3. All AC characteristics are shown for device level. An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have V IL = 0.4V and V IH = 2.4V with the timing referenced to the 1.4V crossover point. The transition time is measured between V IH and V IL. All AC measurements assume t T = 1 ns with the AC output load circuit shown. Specific tac and toh parameters are measured with a 50 pf only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0V. tch V CLOCK tsetup thold tcl t T 2.4V 0.4V I/O Z=50 Ohm 50 Ohm 50 pf INPUT 1.4V tlz tac toh tac I/O 50 pf OUTPUT 1.4V Measurement conditions for tac and toh thz 5. If clock rising time is longer than 1 ns, a time (t T /2-0.5) ns has to be added to this parameter. 6. Rated at 1.5V 7. If t T is longer than 1 ns, a time (t T -1) ns has to be added to this parameter. 8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to wake-up the device. 9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to t RC is satisfied once the Self Refresh Exit command is registered. 10. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 11. t DAL is equivalent to t DPL + t RP. Rev. 1.2 June

11 Package Diagram Units : Inches (Millimeters) Tolerances :.006(.15) unless otherwise specified ( ) 0.24 (6.0) 2.66 (67.56) 2.50 (63.60) (20.00) 1.25 (31.75) 2-R Min (2.00 Min) 0.13 (3.30) 0.91 (23.20) 0.10 (2.50) 0.18 (4.60) (2.10) 1.29 (32.80) (1.80) 0.15 (3.70) A B Min (3.20 Min) Max (3.80 Max) Min (4.00 Min) ( ) Min (2.540 Min) ( ) ( ) ( ) Detail A ( ) 0.03 TYP (0.80 TYP) Detail B Rev. 1.2 June

12 Label Information Module Density Part Number ProMOS TECHNOLOGIES V436632Y24VXXX-XX 256MB SDR-XXXMHz - CLX PCXXXU-XXX-542-A XXXX-XXXXXXX Assembly in Taiwan CAS Latency Criteria of PC100 or PC133 DIMM manufacture date code PCXXX U UNBUFFERED DIMM XXX 54 2 A Gerber file Intel PC100 x16 Based C L = 3 or 2 (CLK) t RCD = 3 or 2 (CLK) t RP = 3 or 2 (CLK) t AC = 5.4ns JEDEC SPD Revision 2 Rev. 1.2 June

13 WORLDWIDE OFFICES SALES OFFICES: TAIWAN(Hsinchu) NO. 19 LI HSIN ROAD SCIEE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: FAX: USA(West) 3910 NORTH FIRST STREET SAN JOSE, CA PHONE: FAX: JAPAN ONZE 1852 BUILDING 6F SHINTOMI, CHUO-KU TOKYO PHONE: FAX: TAIWAN(Taipei) 7F, NO. 102 MIN-CHUAN E. ROAD SEC. 3, Taipei, Taiwan, R.O.C PHONE: FAX: USA(East) 25 Creekside Road Hopewell Jct, NY PHONE: FAX: Copyright,ProMOS TECHNOLOGY. Printed in U.S.A. The information in this document is subject to change without notice. ProMOS TECH makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of ProMOS TECH. ProMOS TECH subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. ProMOS TECH does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. Rev. 1.2 June