VNR133-D128 PDRB X DATA SHEET. Memory Module Part Number VNR133-D128 BUFFALO INC. (1/7)

Transcription

1 DATA SHEET Memory Module Part Number VNR133-D128 (1/7)

2 1. Description 144pin Unbuffered SO-DIMM PC133/CL=3 2. Module Specification Specification Capacity 128MByte Physical Bank(s) 2 Module Organization 16M x 64bit Module Type Unbuffered NonECC Speed Grade PC133/CL=3 PC100/CL=2 Interface LVTTL Power Supply Voltage 3.3V±0.3V Burst Lengths 1,2,4,8,Full DRAM Organization 8M x 16bit SDR SDRAM PCB Part No. X2XGVS8-B PCB Layer 6 Layers Contact Tab 144pin GOLD Flash Plating Ni : min 2.00µm / Au : min 0.05µm Serial PD Support 3. Mechanical Design and Module Pinout Mechanical Design and Pinout Reference standard Mechanical Design and Pinout SDR 144Pin SO-DIMM (PDRB X060-xx) Y(PCB Height) Z1 Z2 : mm : Undefined : 3.75mm MAX(Double Sided) 4. Block Diagram Block Diagram Reference standard Block Diagram PC133/PC100 SO-DIMM(x16bitDRAM 2Bank) (PDRB X202-xx) (2/7)

3 5. Electrical Specifications 5.1 Absolute Maximum Ratings Parameter Symbol Value Unit Voltage Any Pin Relative to Vss V T -0.3~Vcc+0.3 (max 4.6) V Supply Voltage Relative to Vss V CC -0.3~4.6 V Power Dissipation P D 8 W Short Circuit Output Current I O 50 ma 5.2 Recommended Operating Conditions Parameter Symbol MIN MAX Unit Supply Voltage V CC V High Level Input Voltage V IH 2.0 Vcc+0.3 V Low Level Input Voltage V IL V Operating Ambient Temperature T A 0 70 C 5.3 Pin Capacitance CK Input Pin Capacitance /S Input Pin Capacitance CKE Input Pin Capacitance Parameter Symbol Maximum Pin Capacitance Unit CK0 C ICK1 20 pf CK1 C ICK2 20 pf S0 C IS1 20 pf S1 C IS2 20 pf CKE0 C ICKE1 20 pf CKE1 C ICKE2 20 pf DQM Input Pin Capacitance DQMB0-7 C IDQM1 10 pf DQ Input / Output Pin Capacitance DQ0-DQ63 C OUT1 13 pf Other Input Pin Capacitance A,BA,/RAS,/CAS,/WE C IN 40 pf (3/7)

4 5.4 D.C. Characters Parameter Symbol Value Unit Test Condition Burst length=1, Operating current I CC1 MAX 860 * ma t RC t RC (min), I O =0mA, One bank active Precharge Standby current in power down mode I CC2P MAX 24 * ma CKE V IL(max), I CC2PS MAX 16 * ma CKE V IL(max), I CC2N MAX 360 * ma CKE, /S V IH(min), Precharge Standby current in non power down mode Active standby current in power down mode Active standby current in non power down mode I CC2NS MAX 120 * ma CKE V IH (min), I CC3P MAX 80 * ma CKE V IL(max), I CC3PS MAX 40 * ma CKE V IL(max), I CC3N MAX 440 * ma CKE, /S V IH(min), I CC3NS MAX 280 * ma CKE V IH (min), Operating current (Burst mode) I CC4 MAX 960 * ma t CK t CK (min) Io=0mA, One bank active Auto refresh current I CC5 MAX 2480 * ma t RC t RC (min) Self refresh current I CC6 MAX 16 * ma CKE 0.2V All other pins are MIN -80 * µa Input leakage current I IL MAX 80 * µa not under test=0v 0V V IN V CC Output High Voltage V OH MIN 2.4 * V I OH = -2mA Output Low Voltage V OL MAX 0.4 * V I OL = 2mA 5.5 A.C. Timing Characters * : No guarantee against this value. Parameter Symbol MIN MAX Unit Clock Period /CAS Latency = t /CAS Latency = 3 CLK ns Clock High Pulse Width t CH 2.5 ns Clock Low Pulse Width t CL 2.5 ns Input Setup Time t SI 1.5 ns Input Hold Time t HI 0.8 ns Output Valid From Clock /CAS Latency = 2 6 t /CAS Latency = 3 AC 5.4 ns Output Hold From Clock t OH 2.7 ns /RAS to /CAS Delay t RCD 20 ns /RAS Active Time t RAS ,000 ns /RAS Precharge Time t RP 20 ns Act to Act Command Period t RRD 15 ns Row Cycle Time t RC 67.5 ns Average Periodic Refresh Interval t REF 15.6 µs Mode Register cycle time t MRC 15 ns (4/7)

5 6. Serial Presence Detect (SPD) Data Structure Byte No. Function Hex Value VNR133-D128 Function Supported 0 Defines # of bytes written into serial memory at module manufacturer Bytes 1 Total # of bytes of SPD memory device Bytes 2 Fundamental memory type (FPM, EDO, SDRAM..) 04 SDR SDRAM 3 # of row addresses on this assembly 0C 12 4 # Column Addresses on this assembly # Module Banks on this assembly 02 2Banks 6 Data Width of this assembly Data Width continuation 00 64bits 8 Voltage interface standard of this assembly 01 LVTTL 9 SDRAM Cycle time (highest CAS latency) ns (CL=3) 10 SDRAM Access from Clock (highest CAS latency) ns (CL =3) 11 DIMM Configuration type (non-parity, ECC) 00 NonECC 12 Refresh Rate/Type µs 13 Primary SDRAM Width 10 x16bit 14 Error Checking SDRAM width 00 Non-USE 15 Minimum Clock Delay Back to Back Random Column Address 01 1CLK 16 Burst Lengths Supported 8F Burst Lengths (1,2,4,8,FULL) 17 # of Banks on Each SDRAM Device 04 4Banks 18 CAS# Latency 06 CAS Latency =2,3 19 CS# Latency 01 CS Latency =0 20 Write Latency 01 WE Latency =0 21 SDRAM Module Attributes 00 UnBuffered 22 SDRAM Device Attributes: General 0E Supports Write1/Read Burst Supports Precharge All Supports Auto-Precharge 23 SDRAM Cycle time (2nd highest CAS latency) A0 10ns (CL=2) 24 SDRAM Access from Clock (2nd highest CAS latency) 60 6ns (CL=2) 25 SDRAM Cycle time (3rd highest CAS latency) 00 Non Support 26 SDRAM Access from Clock (3rd highest CAS latency) 00 Non Support 27 Minimum Row Precharge Time 14 20ns 28 Row Activate to Row Activate Min. 0F 15ns 29 RAS to CAS Delay Min 14 20ns 30 Minimum RAS Pulse Width 2D 45ns 31 Density of each bank on module 10 64MB 32 Command and Address signal input setup time ns 33 Command and Address signal input hold time ns 34 Data signal input setup time ns 35 Data signal input hold time ns Superset Information (may be used in future) 00 Undefined 62 SPD Data Revision Code 12 Rev Checksum for bytes 0-62 A7 Checksum F 67 Manufacturer s JEDEC ID code per JEP BUFFALO 72 Manufacturing Location Manufacturer s Part Number 20 Blank Revision Code 00 Undefined Manufacturing Date Undefined Assembly Serial Number Undefined Manufacturer Specific Data Undefined 126 Intel specification frequency MHz Compatible 127 Intel Specification CAS# Latency support C7 Clock=0,1 CL =2, Unused storage locations Undefined (5/7)

6 7. Packing/Label Specification Packing/Label Specification Reference standard Packing/Label Specification for SO-DIMM (PDRB X063-xx) (6/7)

7 8. Revision History Rev. Date Changes Issued 01 Dec S.Fukui Change D.C. Characters 02 Apr (I CC2NS :80mA 120mA) Change SPD Data Structure (No Manufacturing Data:00 Undefined Value) (No Assembly Serial Number:00 Undefined Value) (No Manufacturer Specific Data:00 Undefined Value) S.Fukui(A10) (No.128+ Unused storage locations:00 Undefined Value) Change Mechanical Design and Module Pinout (SDR 144pin SO-DIMM PDRB X PDRB X060-02) 03 Jul Changed Reference Drawing No. Mechanical Design and Pinout (PDRB X PDRB X060-xx) Block Diagram (PDRB X PDRB X202-xx) S.Fukui(A11) Packing/Label Specification (PDRB X PDRB X063-xx) (xx : Latest Version) Added Information about PCB Layer 04 Dec Changed D.C. Characters (I CC1 :820mA 860mA) S.Fukui(A13) Changed Pin Capacitance (C IS1 : (C IS2 : (C ICKE1 : 05 Jul (C ICKE2 : (C IDQM1 : 8pF 10 pf) M.Goto(A19) (C IN : 32pF 40 pf) Changed D.C. Characters (I CC2p MAX :16mA 24mA) (I CC3ns MAX :200mA 280mA) (7/7)