Cobalt Performance Features

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2 The Cobalt Architecture Features and Implementation Cobalt Architectural Features Xilinx Virtex-6 Configurable memory resources On-board clocking and synchronization Modular I/O design support a wide range of signal types I/O Module The I/O module is a separate printedcircuit board that caries all of the Cobalt s analog interface circuitry providing excellent isolation noise. Typical front panel signals include analog in and out, clocking, sync and triggering. Cobalt Performance Features sampling rates 10 MHz 3 GHz sampling rates up 1.25 GHz Powerful linked-list DMA engines PCI Express as the primary control and data transfer interface Secondary serial gigabit interface Available in XMC, PCI Express, OpenVPX and CompactPCI formats Available in commercial and in several ruggedization levels up and including conduction cooling y Resources These two smaller boards are used for the memory resources allowing for cusmization of two types of memory. Main Board The main board serves as the foundation of all Cobalt products. It houses the, FLASH memory, XMC interfaces, user programmable interfaces and hosts the memory and I/O modules. Flexible Architecture The modularity of this assembly offers an unprecedented degree of flexibility for creating modules with completely different features by just incorporating different I/O modules. As shown in the diagram, the front panel allows for a maximum of six SSMC signal connecrs. The external clocking, trigger and synchronization connecr is a multipin flat cable connecr and is the same on all models. Copyright 2011 Pentek, Inc. All rights reserved. Contents of this publication may not be reproduced without written permission. Specifications and prices are subject change without notice. Pentek, ReadyFlow, GateFlow, SystemFlow, RTS, and Cobalt are registered trademarks of Pentek, Inc. Other trademarks are properties of their respective owners. Printed in U.S.A. Worldwide distribution and support T-Cobalt

3 The Cobalt Architecture Components and Circuitry Cobalt I/O Module Shown here is a typical Cobalt I/O module. The input analog ports are transformer-coupled two high-speed converters. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. Besides the two s, the typical module could include one DUC (Digital Upconverter), and two s which are transformer-coupled the output analog ports. In addition the input and output ports, the module includes a multiport connecr for clocking and synchronization. All connecrs are on the front panel. Clocking and Synchronization The internal timing buses provide either a single clock or two different clock rates the and signal paths. The timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generar receives an external sample clock which can be used directly for either the or sections or can be divided by a built-in clock synthesizer circuit provide different and clocks. In an alternate mode, the sample clock can be sourced an onboard programmable VCXO (Voltage-Controlled Crystal Oscillar). In this mode, the synthesizer locks the VCXO an external system reference, typically 10 MHz. A front panel 26-pin LVPECL Clock/ Sync connecr allows multiple boards be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate Gate Sync / PPS Sync / PPS Timing Bus VCXO Sample Clk / Reference Clk In TIMING BUS Clock / Sync /Gate / PPS y Resources Clock/Sync Bus Clock/Sync Bus Up four independent memory banks can be configured with all,, or as combination of two banks of each memory type. Each bank can be up 8 MB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, banks can each be up deep. Built-in memory functions include an data transient capture mode and waveform playback mode. In In VIRTEX-6 LX130T, LX240T, LX365T, SX315T or SX475T Optional Configurations Config FLASH 64 MB FLASH LVDS Out Out DIGITAL UPCONVERTER 40 8X Optional P14 PMC PCIe P15 XMC The -bit wide 64 MB FLASH provides non-volatile memory for facry boot code, self-test, and user-defined parameters. Optional Serial I/O P XMC Xilinx Virtex-6 The Virtex-6 can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, LX365T, SX315T, or SX475T. The SXT parts feature up 20 DSP48E slices and are ideal for modulation/demodulation, encoding/ decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT s can be installed. Board Interfaces The Virtex-6 is also used implement the primary board interfaces. The basic XMC module shown here is also available in different formats, such as PCI Express and OpenVPX. All formats feature a built-in x8 PCIe interface as the main control and data transfer interface. 3

4 The Cobalt Architecture Dataflow All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the board s analog interfaces. Depending on model, the facry-installed functions may include acquisition and waveform playback IP modules. IP modules for either or memories, a controller for all data clocking and synchronization functions, a test signal generar, and a PCIe interface complete the facry-installed functions and enable the Cobalt module operate as a complete turnkey solution without the need develop any IP. For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits (described later in this catalog) include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow Design Kit completely replace the Pentek IP with their own. Acquisition IP Modules This typical Cobalt module includes two Acquisition IP Modules for easy capture and data moving. Each IP module can receive data either of the two s, a test signal generar or the Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for moving data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. Bank 1 DATA PACKING & FLOW IP MODULE 1 Ch 1 Ch 2 INPUT MULTIPLEXER Bank 2 DATA PACKING & FLOW IP MODULE 2 Waveform Playback IP Module Facry-installed functions for this typical Cobalt module include a sophisticated Waveform Playback IP module. A linked-list controller allows users easily play back waveforms sred in either on-board memory or offboard host memory the dual s. Parameters including length of waveform, delay playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. loopback TEST SIGNAL Bank 3 DATA UNPACKING & FLOW WAVEFORM PLAYBACK IP MODULE VIRTEX-6 DATAFLOW DETAIL PCIe INTEACE (supports user installed IP) Bank 1 Bank 2 Bank 3 Bank 4 PCIe 8X 40 Gigabit Serial I/O 4

5 Cobalt Formats & Interfaces XMC Format Here is a phograph of the typical board reviewed in detail in the previous section. In its XMC configuration, each Cobalt module complies with the VITA 42.0 XMC specification and is suitable for mounting on motherboards with PMC/XMC connecrs. All XMC modules are available in commercial and in several ruggedization levels up and including conduction cooling. Sample Clk / Reference Clk In In In Out Out TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate Gate Sync / PPS Sync / PPS Timing Bus Clock/Sync Bus Clock/Sync Bus DIGITAL UPCONVERTER VCXO TIMING BUS Clock / Sync /Gate / PPS VIRTEX-6 LX130T, LX240T, LX365T, SX315T or SX475T LVDS Config FLASH 64 MB 40 8X Optional P14 PMC PCIe P15 XMC Optional Serial I/O P XMC Banks 1&2 Banks 3&4 XMC Interface The Cobalt XMC product complies with the VITA 42.0 XMC specification. Each of the two connecrs provides dual links or a single 8X link with up a 6 GHz bit clock. With dual XMC connecrs, the Cobalt XMC supports both x4 and x8 PCIe on the first XMC connecr leaving the second connecr free support user-installed transfer procols specific the target application. PCI Express Interface The Cobalt XMC includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The PCIe interface includes multiple DMA controllers for efficient transfers and the module. Optional Interfaces Option -104 installs the P14 PMC connecr with 20 pairs of LVDS connections the for cusm I/O. Option -105 installs the P XMC connecr with a single 8X or dual gigabit links the support serial procols. 5

6 Cobalt Formats & Interfaces PCI Express Format The PCI Express format shown here is suitable for mounting in PCs with PCIe connecrs and interfaces. Physically, the XMC module reviewed in the previous page is mounted on a PCI Express carrier board with x8 PCIe motherboard connecrs. Other connecrs on this board provide additional interfaces as described below. The unique design of the PCIe carrier includes an integrated fan that keeps the module cool even in demanding situations while still requiring a single PCIe slot. Sample Clk / Reference Clk In In In Out Out TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate Gate Sync / PPS Sync / PPS Timing Bus Clock/Sync Bus Clock/Sync Bus DIGITAL UPCONVERTER VCXO TIMING BUS Clock / Sync /Gate / PPS VIRTEX-6 LX130T, LX240T, LX365T, SX315T or SX475T LVDS Banks 1&2 Banks 3&4 Config FLASH 64 MB 40 8X Optional 68-pin Header x8 PCIe x8 PCI Express Optional Serial I/O Dual Serial Conn PCI Express Interface The PCIe board includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x4 or x8 lane interface includes multiple DMA controllers for efficient transfers and the module. Optional Interfaces Option -104 connects 20 pairs of LVDS signals the on PMC P14 a 68-pin DIL ribbon-cable header on the PCIe board for cusm I/O. Option -105 connects two gigabit serial links the on XMC P two gigabit serial connecrs along the p edge of the PCIe board. 6

7 Cobalt Formats & Interfaces 3U OpenVPX Format The OpenVPX format is compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPX TM System Specification) Shown here is the 3U VPX COTS version (left) and the rugged version which is available in several ruggedization levels up and including conduction cooling. Sample Clk / Reference Clk In In In Out Out TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate Gate Sync / PPS Sync / PPS Timing Bus Clock/Sync Bus Clock/Sync Bus DIGITAL UPCONVERTER VCXO TIMING BUS Clock / Sync /Gate / PPS VIRTEX-6 LX130T, LX240T, LX365T, SX315T or SX475T LVDS Optional Serial I/O 40 8X Config FLASH 64 MB Optional I/O x8 PCIe Banks 1&2 Banks 3&4 VPX BACKPLANE VPX-P2 CROSSBAR SWITCH Gbit Gbit Serial Serial VPX-P1 Gbit Serial Gbit Serial PCI Express Interface The 3U VPX Cobalt board includes an industry-standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Available over the VPX P1 connecr the VPX backplane, the x4 or x8 lane interface includes multiple DMA controllers for efficient transfers and the board. Fabric-Transparent ransparent Crossbar Switch The 3U VPX Cobalt board features a unique high-speed switching configuration. A fabric-transparent crossbar switch bridges numerous interfaces and components on the board using gigabit serial data paths with no latency. Programmable signal input equalization and output pre-emphasis settings enable optimization. Data paths can be selected as single (1X) lanes, or groups of four lanes (). 7 Optional Interfaces Option -104 provides 20 pairs of LVDS connections between the and the VPX P2 connecr for cusm I/O. Option -105 connects two gigabit serial links the on XMC P the crossbar switch for routing VPX P1.

8 Cobalt Formats & Interfaces CompactPCI Formats As shown here, the CompactPCI format is available in three configurations: 6U cpci with double density; this configuration mounts two XMC modules on a 6U carrier board. 6U cpci with single density; this configuration mounts only one XMC module on a 6U carrier board. 3U cpci mounts one XMC module on a 3U carrier board In order describe these three configurations in more detail, we have omitted the components and circuitry shown in the previous three formats; we just show the Virtex-6 s with the external connections that define the standard and optional interfaces. LVDS VIRTEX-6 1st XMC MODULE VIRTEX-6 2nd XMC MODULE LVDS 6U cpci Double Density Two PCIe--PCI Bridges connect the x4 PCIe interfaces each XMC module a PCI--PCI Bridge. This bridge connects both modules the 32- or 64-bit, 33/66 MHz PCI/PCI-X bus Optional x4pcie Optional Serial I/O x4pcie Optional Serial I/O PCIe PCI BRIDGE PCI PCI BRIDGE PCIe PCI BRIDGE Optional 6U cpci Optional Interfaces Option -104 provides 20 pairs of LVDS connections between the and the J3 connecr for cusm I/O. Option -105 provides dual gigabit links between the and the J3 connecr support serial procols. The J3 connecr supports Option -104 or Option The two options are mutually exclusive. The J5 connecr supports Option -104 or Option -105 for the 2nd XMC module. J3 PCI/PCI-X Bus 32/64-bit, 33/66 MHz J5 6U cpci Single Density The 2nd XMC module, its associated PCIe--PCI Bridge and the optional interface connection J5 are not present. LVDS J3 40 VIRTEX-6 XMC MODULE Optional PCI/PCI-X Bus PCIe PCI BRIDGE x4 PCIe 32-bit, 33/66 MHz 3U cpci Single Density A PCIe--PCI Bridge connects the x4 PCIe interface the XMC module the 32- or 64-bit, 33/66 MHz PCI/PCI-X bus. 3U cpci Optional Interfaces Option -104 provides 20 pairs of LVDS connections between the and the J3 connecr for cusm I/O. 8

9 Support Software Pentek ReadyFlow Board Support Package Users of high-performance data acquisition and signal processing boards often find themselves frustrated by the fact that when their new devices are delivered, they are unable put them immediate use. To address this issue, Pentek has developed the ReadyFlow BSPs (Board Support Packages) for all its board-level products. The package contains C-language examples that demonstrate the capabilities of Pentek products. The examples included provide the answers most of the questions that occur with firsttime users of these products. ReadyFlow BSPs are designed reduce development time during the initial stages and when new hardware is added the system. All packages are built with a consistent style and functionnaming convention. Similar parameters on different boards have similar function calls, thereby allowing immediate familiarity with new hardware. Command Line Interface The Command Line Interface is a precompiled executable that runs the hardware right out of the box, without the need write any code. Specific the hardware features of the supported board, it allows operating arguments be entered on the command line for controlling board parameters. For command line functions that control data acquisition, the captured data can be saved in a host file or routed the Signal Analyzer. Signal Analyzer When used with the Command Line Interface, the Signal Analyzer allows users immediately. start acquiring and displaying data. A full-featured analysis ol, the Signal Analyzer displays data in time and frequency domains. Built-in measurement functions display 2nd and 3rd harmonics, THD (tal harmonic disrtion), and SINAD (signal noise and disrtion). Interactive cursors allow users mark data points and instantly calculate amplitude and frequency of displayed signals. Pentek GateFlow Design Kit Using the Design Kit The GateFlow Design Kit allows the user modify, replace and extend the standard facry-installed functions in the incorporate special modes of operation, new control structures, and specialized signal-processing algorithms. The Cobalt architecture configures the with standard facry-supplied interfaces including memory controllers, DMA engines, and interfaces, timing and synchronization structures, triggering and gating logic, time stamping and header tagging, data formatting engines, and the PCIe interface. These resources are connected the User Application Container using well-defined ports that present easy--use data and control signals, effectively abstracting the lower level details of the hardware. The User Application Container Shown here is the block diagram of a typical Cobalt module. The User Application Container holds a collection of different facry-installed IP modules connected the various interfaces through the standard ports surrounding the container. The specific IP modules for each product are described in further detail in the datasheets on the following pages. The GateFlow Design Kit provides a complete Xilinx ISE Foundation Tool project folder containing all the files necessary for the developer Sync Bus Interface Clock Generar Controller Controller Global Registers FLASH Interface 9 Board Registers User Application Container PCI Express Backend PCI Express Interface recompile the entire project with or without any required changes. VHDL source code for each IP module provides excellent examples of how the IP modules work, how they might be modified, and how they might be replaced with cusm IP implement a specific function. Front Panel Interface Facry Installed Base Function Application & Control Data Packing & Formatting Meta Data Files Linked-List Control Linked-List Control User Registers DMAs P14 LVDS P MGTs Timestamp Test Generar Controller Controller Defined and documented interface signals Virtex-6

10 Model 720: Transceiver with Three s, DUC, Two s - XMC Model 720 is the first member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6. A multichannel, highspeed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. It includes three s, one DUC, two s and four banks of memory. In addition supporting PCI Express Gen. 2 as a native interface, the Model 720 includes general purpose and gigabit serial connecrs for applicationspecific I/O. Features Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s Three 200 MHz -bit s One digital upconverter Two 800 MHz -bit s Up 2 GB of or 32 MB of Sample clock synchronization an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up x8 User-configurable gigabit serial interface LVDS connections the Virtex-6 for cusm I/O Converters The front end accepts three full-scale analog HF or IF inputs on front panel SSMC connecrs at +8 dbm in 50 ohms with transformer coupling in three Texas Instruments ADS MHz, -bit converters. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. Sample Clk / Reference Clk In TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate Gate Sync / PPS Sync / PPS Timing Bus TIMING BUS Clock / Sync / Gate / PPS VCXO Clock/Sync Bus Clock/Sync Bus In In In Out Out 200 MHz -BIT Digital Upconverter and s A TI DAC5688 DUC (digital upconverter) and accepts a baseband real or complex data stream the which is optionally interpolated, upconverted and then delivered the two s. When operating as a DUC, it interpolates and translates real or complex baseband input signals any IF center frequency up 360 MHz. It delivers real or quadrature (I+Q) digital outputs the dual -bit converter. Analog output is through a pair of front panel SSMC connecrs. If translation is disabled, the DAC5688 acts as a dual interpolating -bit with output sampling rates up 800 MHz. In both modes the DAC5688 provides interpolation facrs of 2x, 4x and 8x. 200 MHz -BIT 200 MHz -BIT VIRTEX-6 LX130T, LX240T, LX365T, SX315T or SX475T 800 MHz 800 MHz -BIT -BIT DIGITAL UPCONVERTER 32 LVDS Contact Pentek for availability of rugged and conduction-cooled versions Config FLASH 64 MB 8X 40 option 150 option 155 option 0 option 5 Banks 1&2 Banks 3&4 x8 PCIe P15 XMC Gigabit Serial I/O (option 105) P XMC (option 104) P14 PMC 10

11 Model 720: Transceiver with Three s, DUC, Two s - XMC Installed IP Modules The 720 facry-installed functions include three acquisition and a waveform playback IP modules, ideally matched the board s analog interfaces. IP modules for either or memories, a controller for all data clocking and synchronization functions, a test signal generar, and a PCIe interface complete the facryinstalled functions and enable the 720 operate as a complete turnkey solution, without the need develop any IP. Acquisition IP Modules The 720 features three Acquisition IP Modules for easily capturing and moving data. Each module can receive data any of the three s, a test signal generar or the Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. Bank 1 DATA PACKING & FLOW IP MODULE 1 Ch 1 Bank 2 Ch 2 Ch 3 INPUT MULTIPLEXER DATA PACKING & FLOW IP MODULE 2 Waveform Playback IP Module The Model 720 facry-installed functions include a sophisticated Waveform Playback IP module. A linked-list controller allows users easily play back the dual s waveforms sred in either on-board memory or off-board host memory. Parameters including length of waveform, delay playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. loopback Bank 3 DATA PACKING & FLOW IP MODULE 3 TEST SIGNAL Bank 4 DATA UNPACKING & FLOW WAVEFORM PLAYBACK IP MODULE VIRTEX-6 DATAFLOW DETAIL PCIe INTEACE (supports user installed IP) Bank 1 Bank 2 Bank 3 Bank 4 PCIe 8X 40 Gigabit Serial I/O 11

12 Model 720: Transceiver with Three s, DUC, Two s - XMC Also Available A Ordering Information Model x8 PCI Express Model U VPX COTS and rugged Model Description Channel 200 MHz and 2-Channel 800 MHz with Virtex-6 - XMC As above - PCIe As above - 3U VPX Options: -062 XC6VLX240T -063 XC6VLX365T -064 XC6VSX315T -065 XC6VSX475T -104 LVDS I/O -105 Gigabit serial I/O -150 Two 8 MB Banks (Banks 1 and 2) -0 Two 8 MB Banks (Banks 3 and 4) -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with interpolation Resolution: bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one clock and one clock Clock Synthesizer Clock Source: Selectable onboard programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, independently for the clock and clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus: 26-pin connecr LVPECL bus includes, clock/sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/pps inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, XC6VLX365T, XC6VSX315T, or XC6VSX475T Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option -105: Installs the XMC P connecr configurable as one 8X or two gigabit serial links the Option 150 or 0: Two 8 MB memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard XMC module, 2.91 in. x 5.87 in. Contact Pentek for availability of rugged and conduction-cooled versions 12

13 Model 721: Transceiver with Three s, DDCs, DUC, Two s - XMC The model 721 consists of a Model 720 as described previously, but with the addition of three multiband DDCs, one interpolar and one beamformer IP Cores installed in the Virtex-6. These IP Cores are in addition the facry-installed IP Modules described in the Model 720. DDC IP Cores Within each Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the Acquisition IP Modules, many different configurations can be achieved including one driving all three DDCs or each of the three s driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges DC ƒ s, where ƒ s is the sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as three different output bandwidths for the board. Decimations can be programmed 2 65,536 providing a wide range satisfy most applications. The decimating filter for each DDC accepts a unique set of usersupplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*ƒ s /N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 db. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or-bit I + -bit Q samples at a rate of ƒ s /N. Interpolar IP Core The DAC5688 provides interpolation facrs of 2x, 4x and 8x. In addition the DAC5688, an -based interpolar core provides additional interpolation 2x 65,536x. The two interpolars can be combined crate a tal range 2x 524,288x. Beamformer IP Core In addition the DDCs, the 721 features a complete beamforming subsystem. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up 8K samples. The power meters present average power measurements for each DDC core output in easy--read registers. next board Bank 1 AURORA GIGABIT SERIAL INTEACE sum out sum in DDC DEC: 2TO DATA PACKING & FLOW IPMODULE 1 SUMMER BEAMFORMER CORE previous board Ch 1 Ch 2 Ch 3 INPUT MULTIPLEXER DDC DEC: 2TO DATA PACKING & FLOW Bank 2 Bank 3 IPMODULE 2 loopback DDC DEC: 2TO POWER METER & THRESHOLD POWER METER & THRESHOLD POWER METER & THRESHOLD DETECT DETECT DETECT DDC CORE DDC CORE DDC CORE In addition, each DDC core includes a threshold detecr aumatically send an interrupt the processor if the average power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the three DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back in the Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 721 s can be chained gether via a built-in Xilinx Aurora gigabit serial interface through the P XMC connecr. This allows summation across channels on multiple boards. DATA PACKING & FLOW IPMODULE 3 VIRTEX-6 DATAFLOW DETAIL TEST SIGNAL Bank 4 PCIe INTEACE WAVEFORM PLAYBACK IP MODULE 8X PCIe INTERPOLATOR 2TO IP CORE DATA UNPACKING & FLOW 13

14 Model 721: Transceiver with Three s, DDCs, DUC, Two s - XMC Also Available A Specifications Ordering Information Model x8 PCI Express Model U VPX COTS and rugged Model Description Channel 200 MHz with DDC, DUC with 2-Channel 800 MHz, Virtex-6 - XMC As above - PCIe As above - 3U VPX Options: -062 XC6VLX240T -063 XC6VLX365T -064 XC6VSX315T -065 XC6VSX475T -104 LVDS I/O -150 Two 8 MB Banks (Banks 1 and 2) -0 Two 8 MB Banks (Banks 3 and 4) -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) Contact Pentek for availability of rugged and conduction-cooled versions Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Digital Downconverters Quantity: Three channels Decimation Range: 2x 65,536x in two stages of 2x 256x LO Tuning Freq. Resolution: 32 bits, 0 ƒ s LO SFDR: >120 db Phase Offset Resolution: 32 bits, degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 db passband ripple, >100 db spband attenuation Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: bits Digital Interpolar Interpolation Range: 2x 65,536x in two stages of 2x 256x Beamformer Summation: Three channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connecr using Aurora procol Phase Shift Coefficients: I & Q with -bit resolution Gain Coefficients: -bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Front Panel Analog Signal Outputs Output: Transformer-coupled, front panel female SSMC connecrs Transformer: Coil Craft WBC4-6TLB 14 Full Scale Output: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one clock and one clock Clock Synthesizer Clock Source: Selectable onboard programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, independently for the clock and clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus: 26-pin connecr LVPECL bus includes, clock/sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/pps inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VLX365T, XC6VSX315T, or XC6VSX475T Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option 150 or 0: Two 8 MB memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard XMC module, 2.91 in. x 5.87 in.

15 Model 730: 1 GHz, 1 GHz - XMC Model 730 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6. A high-speed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes 1 GHz and converters and four banks of memory. In addition supporting PCI Express Gen. 2 as a native interface, the Model 730 includes optional general purpose and gigabit serial card connecrs for application-specific I/O. Features Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s One 1 GHz 12-bit One 1 GHz -bit Up 2 GB of or MB of Sample clock synchronization an external system reference LVPECL sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up x8 User-configurable gigabit serial interface LVDS connections the Virtex-6 for cusm I/O Contact Pentek for availability of rugged and conduction-cooled versions Converter The front end accepts an analog HF or IF input on a front panel SSMC connecr with transformer coupling in a Texas Instruments ADS GHz, 12-bit converter. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. Sample Clk / Reference Clk In TTL PPS/Gate/Sync Gate In Sync In Sync Bus Gate In Sync In Sync Bus TIMING BUS Clock / Sync / Gate / PPS VCXO Clock/Sync Bus Clock/Sync Bus VIRTEX-6 LX130T, LX240T, LX365T, SX315T or SX475T Converter The 730 features a TI DAC5681Z 1 GHz, -bit. The converter has an input sample rate of 1 GSPS, allowing it acept full rate data the. Additionally, the includes a 2x or 4x interpolation filter for applications that provide 1/2 or 1/4 rate input data. Analog output is transformercoupled a front panel SSMC connecr. In 1 GHz 12-BIT 12 Config FLASH 64 MB Out 1 GHz -BIT 8X LVDS 40 Banks 1&2 Banks 3&4 option 155 option 5 option 150 x8 PCIe P15 XMC Gigabit Serial I/O (option 105) P XMC (option 104) P14 PMC 15

16 Model 730: 1 GHz, 1 GHz - XMC Installed IP Modules The 730 facry-installed functions include an acquisition and a waveform playback IP module. In addition, IP modules for either or memories, a controller for all data clocking and synchronization functions, a test signal generar and a PCIe interface complete the facryinstalled functions and enable the 730 operate as a complete turnkey solution, without the need develop any IP. Acquisition IP Module The 730 features an Acquisition IP Module for easy capture and data moving. The IP module can receive data the, a test signal generar, or the Waveform Playback IP Module in loopback mode. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. The memory banks are supported with a DMA engine for moving data through the PCIe interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. LER Bank 1 Bank 2 DATA PACKING & FLOW loopback INPUT MULTIPLEXER IP MODULE LER Bank 3 Waveform Playback IP Module The Model 730 facry-installed functions include a sophisticated Waveform Playback IP module. A linked-list controller allows users easily play back waveforms sred in either on-board memory or off- board host memory the. Parameters including length of waveform, delay playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. TEST SIGNAL Bank 4 DATA UNPACKING & FLOW WAVEFORM PLAYBACK IP MODULE VIRTEX-6 DATAFLOW DETAIL PCIe INTEACE (supports user installed IP) Bank 1 Bank 2 Bank 3 Bank 4 PCIe 8X 40 Gigabit Serial I/O

17 Model 730: 1 GHz, 1 GHz - XMC Also Available A Specifications Ordering Information Model x8 PCI Express Model U VPX COTS and rugged Model Description GHz and, Virtex-6 - XMC As above - PCIe As above - 3U VPX Options: -062 XC6VLX240T XC6VLX365T XC6VSX315T XC6VSX475T LVDS I/O -105 Gigabit serial I/O -150 Two 8 MB Banks (Banks 1 and 2) -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Converter Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz 1 GHz Resolution: 12 bits Converter Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connecrs Sample Clock Sources: On-board clock synthesizer generates two clocks: one clock and one clock Clock Synthesizer Clock Source: Selectable onboard programmable VCXO or front panel external clock VCXO Frequency Ranges: MHz, MHz, and MHz Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, independently for the clock and clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts 100 MHz 1 GHz divider input clock, or PLL system reference Timing Bus: 7-pin connecrs, LVPECL bus for sync and gate, one connecr and one connecr External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2, XC6VLX365T-2, XC6VSX315T-2, or XC6VSX475T-2 Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option -105: Installs the XMC P connecr configurable as one 8X or two gigabit serial links the Option 150: Two 8 MB memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen.1 or Gen.2, x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard XMC module, 2.91 in. x 5.87 in. Contact Pentek for availability of rugged and conduction-cooled versions 17

18 Model 750: Transceiver with Two s, DUC, Two s - XMC Model 750 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6. A multichannel, high-speed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes two s, one DUC, two s, and four banks of memory. In addition supporting PCI Express Gen. 2 as a native interface, the Model 750 includes optional general-purpose and gigabit serial card connecrs for application-specific I/O. Features Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s Two 500 MHz 12-bit s One digital upconverter Two 800 MHz -bit s Up 2 GB of or 32 MB of Sample clock synchronization an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up x8 VITA 42.0 XMC compatible with switched fabric interfaces LVDS connections the Virtex-6 for cusm I/O Converter The front end accepts two full-scale analog HF or IF inputs on front panel SSMC connecrs at +5 dbm in 50 ohms with transformer coupling in two Texas Instruments ADS MHz, 12-bit converters. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. Sample Clk / Reference Clk In TTL PPS/Gate/Sync TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate Gate Sync / PPS Sync / PPS Timing Bus TIMING BUS Clock / Sync / Gate / PPS VCXO Clock/Sync Bus Clock/Sync Bus In 500 MHz 12-BIT Digital Upconverter and s A TI DAC5688 DUC and accepts a baseband real or complex data stream the which is optionally interpolated, upconverted and then delivered the two s. When operating as a DUC, it interpolates and translates real or complex baseband input signals any IF center frequency up 360 MHz. It delivers real or quadrature (I+Q) digital outputs the dual -bit converter. Analog output is through a pair of front panel SSMC connecrs. If translation is disabled, the DAC5688 acts as a dual interpolating -bit converter with output sampling rates up 800 MHz. In both modes the DAC5688 provides interpolation facrs of 2x, 4x and 8x. In 500 MHz 12-BIT VIRTEX-6 LX130T, LX240T, LX365T, SX315T or SX475T Out 800 MHz -BIT 32 Out 800 MHz -BIT DIGITAL UPCONVERTER LVDS Contact Pentek for availability of rugged and conduction-cooled versions Config FLASH 64 MB 8X 40 option 150 option 155 option 0 option 5 Banks 1&2 Banks 3&4 x8 PCIe P15 XMC Gigabit Serial I/O (option 105) P XMC (option 104) P14 PMC 18

19 Model 750: Transceiver with Two s, DUC, Two s - XMC Installed IP Modules The 750 facry-installed functions include two acquisition and one waveform playback IP modules. In addition, IP modules for either or memories, a controller for all data clocking and synchronization functions, a test signal generar and a PCIe interface complete the facryinstalled functions and enable the 750 operate as a complete turnkey solution, without the need develop any IP. Acquisition IP Modules The 750 features two Acquisition IP Modules for easy capture and data moving. Each IP module can receive data either of the two s, a test signal generar or the Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for moving data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. Bank 1 DATA PACKING & FLOW IP MODULE 1 Ch 1 Ch 2 INPUT MULTIPLEXER Bank 2 DATA PACKING & FLOW IP MODULE 2 Waveform Playback IP Module The Model 750 facry-installed functions include a sophisticated Waveform Playback IP module. A linked-list controller allows users easily play back waveforms sred in either on-board memory or off- board host memory the dual s. Parameters including length of waveform, delay playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. loopback TEST SIGNAL Bank 3 DATA UNPACKING & FLOW WAVEFORM PLAYBACK IP MODULE VIRTEX-6 DATAFLOW DETAIL PCIe INTEACE (supports user installed IP) Bank 1 Bank 2 Bank 3 Bank 4 PCIe 8X 40 Gigabit Serial I/O 19

20 Model 750: Transceiver with Two s, DUC, Two s - XMC Also Available A Specifications Ordering Information Model x8 PCI Express Model U VPX COTS and rugged Model Description 750 Two 500 MHz s, one DUC, Two 800 MHz s with Virtex-6 - XMC As above - PCIe As above - 3U VPX Options: MHz, 14-bit s -062 XC6VLX240T XC6VLX365T XC6VSX315T XC6VSX475T LVDS I/O -105 Gigabit serial I/O -150 Two 8 MB Banks (Banks 1 and 2) -0 Two 8 MB Banks (Banks 3 and 4) -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters (standard) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz 500 MHz Resolution: 12 bits Converters (option 014) Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz 400 MHz Resolution: 14 bits Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz, max. Output IF: DC 400 MHz, max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz, max. with interpolation Resolution: bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one clock and one clock Clock Synthesizer Clock Source: Selectable onboard programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, independently for the clock and clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connecr LVPECL bus includes, clock/ sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/ PPS inputs External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2, XC6VLX365T-2, XC6VSX315T-2, or XC6VSX475T-2 Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option -105: Installs the XMC P connecr configurable as one 8X or two gigabit serial links the Option 150 or 0: Two 8 MB memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen.1 or Gen.2, x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard XMC module, 2.91 in. x 5.87 in. Contact Pentek for availability of rugged and conduction-cooled versions 20

21 Model 760: 4-Channel 200 MHz - XMC Model 760 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6. A multichannel, highspeed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes four s and four banks of memory. In addition supporting PCI Express Gen. 2 as a native interface, the Model 760 includes general purpose and gigabit serial connecrs for application-specific I/O. Converters The front end accepts four full-scale analog HF or IF inputs on front panel SSMC connecrs at +8 dbm in 50 ohms with transformer coupling in four Texas Instruments ADS MHz, -bit converters. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. Features Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s Four 200 MHz -bit s Up 2 GB of or 32 MB of Sample clock synchronization an external system reference LVPECL clock/sync bus for multimodule synchronization In In In In PCI Express (Gen. 1 & 2) interface up x8 VITA 42.0 XMC compatible with switched fabric interfaces User-configurable gigabit serial interface LVDS connections the Virtex-6 for cusm I/O Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B Timing Bus TIMING BUS Clock / Sync / Gate / PPS VCXO Clock/Sync Bus 200 MHz -BIT 200 MHz -BIT 200 MHz -BIT VIRTEX-6 LX130T, LX240T, LX365T, SX315T or SX475T 200 MHz -BIT LVDS Contact Pentek for availability of rugged and conduction-cooled versions Config FLASH 64 MB 8X 40 option 150 option 155 option 0 option 5 x8 PCIe P15 XMC Gigabit Serial I/O (option 105) P XMC (option 104) P14 PMC Banks1&2 Banks3&4 21

22 Model 760: 4-Channel 200 MHz - XMC Installed IP Modules The 760 facry-installed functions include four acquisition IP modules. IP modules for either or memories, a controller for all data clocking and synchronization functions, a test signal generar, and a PCIe interface complete the facryinstalled functions and enable the 760 operate as a complete turnkey solution without the need develop any IP. Acquisition IP Modules The 760 features four Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data any of the four s or a test signal generar Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. Ch 1 Ch 2 Ch 3 Ch 4 TEST SIGNAL INPUT MULTIPLEXER DATA PACKING & FLOW DATA PACKING & FLOW DATA PACKING & FLOW DATA PACKING & FLOW Bank 1 Bank 2 Bank 3 Bank 4 IP MODULE 1 IP MODULE 2 IP MODULE 3 IP MODULE 4 VIRTEX-6 DATAFLOW DETAIL PCIe INTEACE (supports user installed IP) Bank 1 Bank 2 Bank 3 Bank 4 PCIe 8X 40 Gigabit Serial I/O 22

23 Model 760: 4-Channel 200 MHz - XMC Also Available A Specifications Ordering Information Model x8 PCI Express Model U VPX COTS and rugged Model Description Channel 200 MHz with Virtex-6 - XMC As above - PCIe As above - 3U VPX Options: -062 XC6VLX240T -063 XC6VLX365T -064 XC6VSX315T -065 XC6VSX475T -104 LVDS I/O -105 Gigabit serial I/O -150 Two 8 MB Banks (Banks 1 and 2) -0 Two 8 MB Banks (Banks 3 and 4) -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable onboard programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connecr; LVPECL bus includes, clock/sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, XC6VLX365T, XC6VSX315T, or XC6VSX475T Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option -105: Installs the XMC P connecr configurable as one 8X or two gigabit serial links the Option 150 or 0: Two 8 MB memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard XMC module, 2.91 in. x 5.87 in. Contact Pentek for availability of rugged and conduction-cooled versions 23

24 Model 761: 4-Channel 200 MHz with DDCs and Beamformer - XMC The model 761 consists of a Model 760 as described previously, but with the addition of four multiband DDCs, and one beamformer IP Cores installed in the Virtex-6. These IP Cores are in addition the facry-installed IP Modules described in the Model 760. DDC IP Cores Within each Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the Acquisition IP Modules, many different configurations can be achieved including one driving all four DDCs or each of the four s driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges DC ƒ s, where ƒ s is the sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as three different output bandwidths for the board. Decimations can be programmed 2 65,536 providing a wide range satisfy most applications. The decimating filter for each DDC accepts a unique set of usersupplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*ƒ s /N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 db. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or-bit I + -bit Q samples at a rate of ƒ s /N. Beamformer IP Core In addition the DDCs, the 761 features a complete beamforming subsystem. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up 8K samples. The power meters present average power measurements for each DDC core output in easy--read registers. In addition, each DDC core includes a threshold detecr aumatically send an interrupt the processor if the average power level of any DDC core falls below or exceeds a programmable threshold. TEST SIGNAL next board Bank 1 AURORA GIGABIT SERIAL INTEACE sum out sum in SUMMER BEAMFORMER CORE previous board DDC DEC: 2TO DATA PACKING & FLOW IPMODULE 1 Ch 1 DDC DEC: 2TO DATA PACKING & FLOW IPMODULE 2 Ch 2 A programmable summation block provides summing of any of the four DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back in the Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 761 s can be chained gether via a built-in Xilinx Aurora gigabit serial interface through the P XMC connecr. This allows summation across channels on multiple boards. INPUT MULTIPLEXER VIRTEX-6 DATAFLOW DETAIL Ch 3 DDC DEC: 2TO DATA PACKING & FLOW IPMODULE 3 Ch 4 DDC DEC: 2TO POWER METER & THRESHOLD POWER METER & THRESHOLD POWER METER & THRESHOLD POWER METER & THRESHOLD DETECT DETECT DETECT DETECT DDC CORE DDC CORE DDC CORE DDC CORE DATA PACKING & FLOW Bank 2 Bank 3 Bank 4 IPMODULE 4 PCIe INTEACE 8X PCIe 24

25 Model 761: 4-Channel 200 MHz with DDCs and Beamformer - XMC Also Available A Specifications Ordering Information Model x8 PCI Express Model U VPX COTS and rugged Model Description Channel 200 MHz with DDCs and Virtex-6 - XMC As above - PCIe As above - 3U VPX Options: -062 XC6VLX240T -063 XC6VLX365T -064 XC6VSX315T -065 XC6VSX475T -104 LVDS I/O -150 Two 8 MB Banks (Banks 1 and 2) -0 Two 8 MB Banks (Banks 3 and 4) -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) Contact Pentek for availability of rugged and conduction-cooled versions Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Digital Downconverters Quantity: Four channels Decimation Range: 2x 65,536x in two stages of 2x 256x LO Tuning Freq. Resolution: 32 bits, 0 ƒ s LO SFDR: >120 db Phase Offset Resolution: 32 bits, degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 db passband ripple, >100 db spband attenuation Beamformer Summation: Four channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connecr using Aurora procol Phase Shift Coefficients: I & Q with -bit resolution Gain Coefficients: -bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable onboard programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the clock 25 External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus: 26-pin connecr LVPECL bus includes, clock/sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VLX365T, XC6VSX315T, or XC6VSX475T Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option 150 or 0: Two 8 MB memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard XMC module, 2.91 in. x 5.87 in.

26 .... Model 762: 4-Channel 200 MHz with 32-Channel DDC - XMC The model 762 consists of a Model 760 as described previously, but with the addition of four 8-Channel DDC IP Cores installed in the Virtex-6. These IP Cores are in addition the facry-installed IP Modules described in the Model 760. DDC IP Cores Within each Acquisition IP Module is a powerful 8-channel DDC bank. Because of the flexible input routing of the Acquisition IP Modules, many different configurations can be achieved including one driving all 32 DDC channels or each of the four s driving its own DDC bank. Each of the 32 channels has an independent 32-bit tuning frequency setting that ranges DC ƒ s, where ƒ s is the sampling frequency. All of the 8 channels within a bank share a common decimation setting that can range 8192, programmable in steps of 8. For example, with a sampling rate of 200 MHz, the available output bandwidths range khz 10.0 MHz. Each 8-channel bank can have its own unique decimation setting supporting a different bandwidth associated with each of the four acquisition modules. The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*ƒ s /N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 db. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of ƒ s /N. Any number of channels can be enabled within each bank, selectable 0 8. Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within a bank. Ch 1 Ch 2 Ch 3 Ch 4 TEST SIGNAL INPUT MULTIPLEXER Bank 1 DIGITAL DOWN- CONVERTER BANK 1: CH 1-8 DEC: TO 8192 DDC CORE DATA PACKING & FLOW IP MODULE 1 DIGITAL DOWN- CONVERTER BANK 2: CH 9- DEC: TO 8192 DDC CORE DATA PACKING & FLOW Bank 2 Bank 3 Bank 4 IP MODULE 2 DIGITAL DOWN- CONVERTER BANK 3: CH DEC: TO 8192 DDC CORE DATA PACKING & FLOW IP MODULE 3 DIGITAL DOWN- CONVERTER BANK 4: CH DEC: TO 8192 DDC CORE DATA PACKING & FLOW IP MODULE 4 VIRTEX-6 DATAFLOW DETAIL PCIe INTEACE (supports user installed IP) 32 Bank 1 32 Bank 2 32 Bank 3 32 Bank 4 8X PCIe Gigabit Serial I/O 40 26

27 Model 762: 4-Channel 200 MHz with 32-Channel DDC - XMC Also Available A Ordering Information Model x8 PCI Express Model U VPX COTS and rugged Model Description Ch 200 MHz with 32-Ch DDC and Virtex-6 - XMC As above - PCIe As above - 3U VPX Options: -062 XC6VLX240T -063 XC6VLX365T -064 XC6VSX315T -065 XC6VSX475T -104 LVDS I/O -105 Gigabit serial I/O -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Digital Downconverters Quantity: Four 8-channel banks, one per acquisition module Decimation Range: x 8192x in steps of 8x LO Tuning Freq. Resolution: 32 bits, 0 ƒ s Phase Offset Resolution: 32 bits, degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, >100 db spband attenuation Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable onboard programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock, or PLL system reference Timing Bus: 26-pin connecr LVPECL bus includes, clock/sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VLX365T, XC6VSX315T, or XC6VSX475T Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option -105: Installs the XMC P connecr configurable as one 8X or two gigabit serial links the Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard XMC module, 2.91 in. x 5.87 in. Contact Pentek for availability of rugged and conduction-cooled versions 27

28 Model 790: L-Band Tuner with 2-Channel 200 MHz - XMC Model 790 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6. A 2-Channel highspeed data converter, it is suitable for connection directly the port of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes an L-Band tuner, two s and four banks of memory. In addition supporting PCI Express Gen. 2 as a native interface, the Model 790 includes general purpose and gigabit serial connecrs for applicationspecific I/O. Features Accepts signals 925 MHz 2175 MHz Programmable LNA boosts LNB (low-noise block) antenna signal levels with up 80 db gain Programmable analog downconverter provides I + Q baseband signals with bandwidths ranging 4 40 MHz Two 200 MHz -bit s Supports Xilinx Virtex-6 LXT and SXT s 2 GB of or 32 MB of Sample clock synchronization an external system reference PCI Express (Gen. 1 & 2) interface, up x8 Clock/sync bus for multimodule synchronization VITA 42.0 XMC compatible with switched fabric interfaces User-configurable gigabit serial interface LVDS connections the Virtex-6 for cusm I/O Contact Pentek for availability of rugged and conduction-cooled versions Tuner A front panel SSMC connecr accepts L-Band signals between 925 MHz and 2175 MHz an antenna LNB (low noise block). A Maxim MAX2112 tuner directly converts these L-Band signals baseband using a broadband I/Q downconverter. The device includes an variablegain LNA (low noise amplifier), a PLL (phase- locked loop) synthesized local oscillar, quadrature (I + Q) downconverting mixers, baseband lowpass filters with programmable cuff frequency, and variable-gain baseband amplifiers. The fractional-n PLL synthesizer locks its VCO an on-board crystal, the timing generar output, or an Sample Clk / Reference Clk In Trigger 1 Trigger 2 TTL Gate / Trig TTL Sync / PPS Sample Clk Ref In Gate A Gate B Sync / PPS A Sync / PPS B Timing Bus TIMING Clock / Sync / Gate / PPS VCXO Ref Clock/Sync option 150 option 155 Ref In XTAL OSC Option 100 VIRTEX-6 LX130T, LX240T, LX365T, SX315T or SX475T 200 MHz -BIT option 0 option 5 Banks 1&2 Banks 3&4 external reference input between 12 and 30 MHz. Together, the baseband amplifiers and the LNA offer a programmable-gain range of more than 80 db. An integrated lowpass filter with variable bandwidth provides bandwidths ranging 4 40 MHz, programmable with 8 bits of resolution. Converters The analog baseband I and Q analog tuner outputs are then applied two Texas Instruments ADS MHz, -bit converters. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. I In MAX2112 Ref Out Q 200 MHz -BIT Config FLASH 64 MB GC Control 8X x8 PCIe P15 XMC 12-BIT IC 2 2 Gigabit Serial I/O (option 105) P XMC LVDS 40 (option 104) P14 PMC 28

29 Installed IP Modules Model 790: L-Band Tuner with 2-Channel 200 MHz - XMC The 790 facry-installed functions include two acquisition IP modules. IP modules for either or memories, a controller for all data clocking and synchronization functions, a test signal generar, and a PCIe interface complete the facryinstalled functions and enable the 790 operate as a complete turnkey solution without the need develop any IP. Acquisition IP Modules The 790 features two Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data either of the two s or a test signal generar Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. (I) (Q) TEST SIGNAL INPUT MULTIPLEXER DATA PACKING & FLOW DATA PACKING & FLOW Bank 1 Bank 2 IP MODULE 1 IP MODULE 2 VIRTEX-6 DATAFLOW DETAIL PCIe INTEACE (supports user installed IP) Bank 1 Bank 2 Bank 3 Bank 4 PCIe 8X 40 Gigabit Serial I/O 29

30 Model 790: L-Band Tuner with 2-Channel 200 MHz - XMC Also Available A Ordering Information Model x8 PCI Express Model U VPX COTS and rugged Model Description 790 L-Band Tuner with 2-Channel 200 MHz and Virtex-6 - XMC As above - PCIe As above - 3U VPX Options: -062 XC6VLX240T -063 XC6VLX365T -064 XC6VSX315T -065 XC6VSX475T -100 On-board 27 MHz crystal oscillar reference -104 LVDS I/O -105 Gigabit serial I/O -150 Two 8 MB Banks (Banks 1 and 2) -0 Two 8 MB Banks (Banks 3 and 4) -155 Two Banks (Banks 1 and 2) -5 Two Banks (Banks 3 and 4) Specifications Front Panel Analog Signal Input Connecr: Front panel female SSMC Impedance: 50 ohms L-Band Tuner Type: Maxim MAX2112 Input Frequency Range: 925 MHz 2175 MHz Monolithic VCO Phase Noise: -97 dbc/hz at 10 khz Fractional-N PLL Synthesizer: freq VCO = (N.F) x freq REF where integer N = and fractional F is a 20-bit binary value PLL Reference (freq REF ): Front panel SSMC connecr or on-board 27 MHz crystal (Option -100), MHz LNA Gain: 0 65 db, controlled by a programmable 12-bit converter Baseband Amplifier Gain: 0 15 db, in 1 db steps Baseband Low Pass Filter: Cuff frequency programmable 4 40 MHz with 8-bit resolution Dynamic Range: -75 dbm 0 dbm Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources: On-board timing generar/synthesizer Clock Synthesizer Clock Source: Selectable onboard programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, for the clock Timing Generar External Clock Input Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Generar Bus: 26-pin front panel connecr LVPECL bus includes, clock/sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Input Quantity: 2 Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, XC6VLX365T, XC6VSX315T, or XC6VSX475T Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option -105: Installs the XMC P connecr configurable as one 8X or two gigabit serial links the Option 150 or 0: Two 8 MB memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard XMC module, 2.91 in. x 5.87 in. Contact Pentek for availability of rugged and conduction-cooled versions 30

31 Preconfigured Cobalt Recording and Playback Instruments Model RTS 2706: 200 MHz Real-Time Data Recording and Playback Instrument Features Rugged RTS 2706 Complete multiband recording and playback instrument 4U 19 inch industrial rack-mount PC server chassis Windows 7 Professional workstation with high-performance Intel Core TM i7 processor -bit 200 MHz s -bit 800 MHz s Real-time sustained recording rates of up 00 MB/sec Configurations one eight channels of recording and playback From 2 20 terabytes srage NTFS RAID disk array RAID levels of 0,1, 5, 6, 10 and 50 SystemFlow GUI with Signal Viewer analysis ol which includes a virtual oscilloscope and spectrum analyzer File headers include time stamping and recording parameters Optional DDC decimation and DUC interpolation range 2 65,536 Up 80 MHz record and playback signal bandwidths IF frequencies 700 MHz Optional GPS time and position stamping The Pentek RTS 2706 is a turnkey, multiband recording and playback instrument for recording and reproducing highbandwidth signals. The RTS 2706 uses -bit, 200 MHz converters and provides sustained recording rates up 00 MB/sec in four-channel configuration. The RTS 2706 uses Pentek s high-powered Virtex-6-based Cobalt modules, that provide flexibility in channel count, with optional digital downconversion capabilities. Optional -bit, 800 MHz converters with digital upconversion allow real-time reproduction of recorded signals. sampling rates, DDC decimations and bandwidths, sampling rates, and DUC interpolations are among the GUI-selectable system parameters, providing a fully programmable instrument capable of recording and reproducing a wide range of signals. Optional GPS time and position stamping allows the user record this critical signal information. SystemFlow Signal Viewer The SystemFlow Signal Viewer includes a virtual oscilloscope and spectrum analyzer for signal moniring in both the time and frequency domains. It is extremely useful for previewing live inputs prior recording, and for moniring signals as they are being recorded help ensure successful recording sessions. The viewer can also be used inspect and analyze the recorded files after the recording is complete. 31 SystemFlow Software The RTS 2706 includes the System-Flow Recording Software. SystemFlow features a Windows-based GUI (graphical user interface) that provides a simple means configure and control the instrument. Cusm configurations can be sred as profiles and later loaded when needed, allowing the user select preconfigured settings with a single click. SystemFlow also includes signal viewing and analysis ols, that allow the user monir the signal prior, during, and after a recording session. These ols include a virtual oscilloscope and a virtual spectrum analyzer. Built on a Windows 7 Professional workstation, the RTS 2706 allows the user install post processing and analysis ols operate on the recorded data. The instrument records data the native NTFS file system, providing immediate access the recorded data. Advanced signal analysis capabilities include aumatic calculars for signal amplitude and frequency, second and third harmonic components, THD (tal harmonic disrtion) and SINAD (signal noise and disrtion). With time and frequency zoom, panning modes, and dual annotated cursors mark and measure points of interest, the SystemFlow Signal Viewer can often eliminate the need for a separate oscilloscope or spectrum analyzer in the field.

32 Performance Graphs Performance: Models 720, 721, 760, 761, 762, RTS 2706 Spurious Free Dynamic Range Spurious Pick-up f in = 70 MHz, f s = 200 MHz, Internal Clock Two-Tone SFDR f s = 200 MHz, Internal Clock Two-Tone SFDR f 1 = 30 MHz, f 2 = 70 MHz, f s = 200 MHz Adjacent Channel Crosstalk Crosstalk f 1 = 69 MHz, f 2 = 71 MHz, f s = 200 MHz Input Frequency Response f in Ch2 = 70 MHz, f s = 200 MHz, Ch 1 shown f s = 200 MHz, Internal Clock Performance: Models 720, 721, RTS 2706 Spurious Free Dynamic Range Spurious Free Dynamic Range f out = 70 MHz, f s = 200 MHz, Internal Clock f out = 120 MHz, f s = 400 MHz, External Clock 32

33 Model 7809: 4-Channel SFP Transceiver PCIe Module for Cobalt Boards Features Compatible with Pentek PCI Express Cobalt boards Extends range of gigabit serial I/O links Four SFP modules drive cable lengths up 10 km Support for both optical and copper cables Single-mode and multi-mode fibre optical Data rates 5 Gbits/sec Payload data rates 500 MB/sec for each cable Ordering Information Model Description Channel SFP Transceiver PCIe Module Options: -002 Two 850 nm multi-mode fiber optical channel SFPs (500 m distance) -004 Four 850 nm multi-mode fiber optical channel SFPs (500 m distance) Contact Pentek for availability of other interfaces General Information Model 7809 is a PCIe module that provides gigabit serial transceiver network cable links for Pentek s Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6. The 7809 and the Cobalt board are installed in adjacent slots in a PCIe motherboard or backplane and joined with a gigabit serial flex circuit cable. The 7809 takes advantage of the small form-facr pluggable (SFP) or Mini-GBIC standard, supporting a variety of hot-pluggable transceiver modules for optical and copper network cables. Up four modules can be installed. Since the 7809 is procol transparent, it is compatible with many procols including Serial FPDP, PCIe, Xilinx Aurora, Serial-RapidIO, Gigabit Ethernet, SONET, Fibre Channel, and others. The Cobalt Connection The 786xx series PCIe Cobalt boards feature two optional gigabit serial connecrs along the p edge of the circuit board. These two ports are wired directly P of the XMC module. The 7809 circuit board has one gigabit serial connecr along its p edge. A short flex circuit cable is installed between the 7809 connecr and one of the two Cobalt connecrs. This provides a full-duplex gigabit serial path between the modules that can operate at serial bit rates 5 GHz. A second 7809 can be installed adjacent the Cobalt board support a second transceiver link. Flex Circuit Cable Cobalt Module Gigabit Serial Connecr 33 EQUALIZER Pre-Emphasis De-Emphasis Each of the four gigabit serial links within a port consists of a transmit pair and a receive pair connected one SFP module through an equalizer circuit improve transceiver performance. The Virtex-6 in the Cobalt module is used implement the required procol engine for the P links the Some Cobalt boards (such as the and 78661) are equipped with facry-installed IP supporting Xilinx Aurora links for cascade beamforming summation across multiple boards. Pentek s GateFlow Design Kit allows users implement cusm procols for other applications. GateFlow is compatible with the Xilinx ISE Foundation Tool Suite, and includes a complete project file and VHDL source code. SFP Modules SFP transceiver modules support a variety of different transmitter and receiver types. These modules simply plug in the SFP sockets so they can be easily installed or replaced by users. Users can choose the appropriate transceiver for each link support the required distance and data rates. Both single-mode and multi-mode optical fibre devices are available for cable interconnection distances up 550 m and 10 km, respectively. Pentek offers the 7809 with options for either two or four 850 nm multi-mode fibre optical SFP modules installed. Each 7809 is supplied with the gigabit serial flex circuit cable assembly for connection a suitably equipped 786xx series PCIe Cobalt board. SFP MODULE 1 SFP MODULE 2 SFP MODULE 3 SFP MODULE 4 Optical or Copper Cable Optical or Copper Cable Optical or Copper Cable Optical or Copper Cable

34 Coming Soon Model 740: 1-Channel 3 GHz or 2-Channel 1.5 GHz - XMC In In Features One 3 GHz, 12-bit, or Two 1.5 GHz, 12-bit s 2 GB of LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up x8 User-configurable gigabit serial interface LVDS connections the Virtex-6 for cusm I/O Contact Pentek for availability of rugged and conduction-cooled versions Sample Clk TTL PPS/Gate/Sync TIMING BUS Clock/Sync Bus 3.6 GHz (1 Channel) or Gate In Reset In Clock / Sync / Gate / PPS 1.8 GHz (2 Channel) 12-Bit Ref Clk In Ref Clk Out Sync Bus Banks1&2 VIRTEX-6 LX130T, LX240T, LX365T, SX315T or SX475T Banks3&4 Config FLASH 64 MB 8X x8 PCIe P15 XMC Gigabit Serial I/O (option 105) P XMC LVDS 40 (option 104) P14 PMC Model 770: 4-Channel 1.25 GHz with 4-Channel DUC - XMC Out Out Out Out Features Four 1.25 GHz, -bit s Four digital upconverters Up 2 GB of or 32 MB of Sample clock synchronization an external system reference Clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up x8 User-configurable gigabit serial interface LVDS connections the Virtex-6 for cusm I/O Sample Clk / Reference Clk In Trigger In Gate In Sync In Sync Bus 1 Gate In Sync In Sync Bus 2 TIMING BUS Clock / Sync / Gate / PPS VCXO Clock/Sync Bus option 150 option 155 Banks1& GHz -BIT DIGITAL UPCONVERTER VIRTEX-6 LX130T, LX240T, LX365T, SX315T or SX475T 1.25 GHz -BIT DIGITAL UPCONVERTER option 0 option 5 Banks3&4 Config FLASH 64 MB 1.25 GHz -BIT DIGITAL UPCONVERTER 8X x8 PCIe P15 XMC 1.25 GHz -BIT DIGITAL UPCONVERTER Gigabit Serial I/O (option 105) P XMC LVDS 40 (option 104) P14 PMC Contact Pentek for availability of rugged and conduction-cooled versions 34

35 Cusmer Information Placing an Order When placing purchase orders for Pentek products, please provide the model numbers and descriptions used in this catalog. You may place your orders by letter, telephone, or fax; you should confirm a verbal order by mail, or fax. All orders should specify a purchase order number, bill and ship- address, method of shipment, and a contact name and telephone number. U.S. orders should be made out Pentek, Inc. and may be placed directly at our office address, or c/o our authorized sales representative in your area. International orders may be placed with us, or with our authorized distribur in your country. They have pricing and availability information and they will be pleased assist you. Prices and Price Quotations All prices are F.O.B. facry in U.S. dollars. Shipping charges and applicable import, federal, state or local taxes, are paid by the purchaser. We re glad respond your request for price quotation just contact the corporate office, or your local representative. Price and delivery quotations are valid for 30 days, unless otherwise stated. Quantity discounts for large orders are available and will be included in our price quotation, if applicable. Terms Terms are Net 30 days for accounts with established credit; until credit is established, we require prepayment, or will ship C.O.D. Shipping For new orders, we normally ship UPS ground with shipping charges prepaid and added our invoice. If you are in a hurry, we will ship UPS Red, UPS Blue, FedEx, or the carrier of your choice, as you request. Order Cancellation and Returns All orders placed with Pentek are considered binding and are subject cancellation charges. Hardware products included in this catalog may be returned within 30 days after receipt, subject a rescking charge. Before returning a product, please call Cusmer Service obtain a Return Material Authorization (RMA) number. Software purchases are final and we cannot allow returns. Warranty Pentek warrants its products conform published specifications and be free defects in materials and workmanship for a period of one year the date of delivery, when used under normal operating conditions and within the service conditions for which they were furnished. The obligation of Pentek arising a warranty claim shall be limited repairing or, optionally, replacing without charge any product which proves be defective within the term and scope of the warranty. Pentek must be notified of the defect or nonconformity within the warranty period. The affected product must be returned with shipping charges and insurance prepaid. Pentek will pay shipping charges for the return of product buyer, except for products returned outside of the USA. Limitations of Warranty This warranty does not apply products which have been repaired or altered by anyone other than Pentek or its authorized representatives. The warranty does not extend products that have been damaged by misuse, neglect, improper installation, unauthorized modification, or extreme environmental conditions. Pentek specifically disclaims merchantability or fitness for a particular purpose. We will not be held liable for incidental or consequential damages arising the sale, use, or installation of any of our products. Under any circumstances Pentek s liability under this warranty will not exceed the purchase price of the product. Extended Warranty You may purchase an extended warranty on our hardware products for a fee of 1% of the list price per month of coverage, or 10% of the list price per year of coverage. All Pentek software products (excluding 3rd-party products) include free maintenance and free upgrades for one year. Extended software maintenance is available for one, two, and three years, starting after the first year. Service vice and Repair Before returning a product for service and repair, please contact Cusmer Service obtain a Return Material Authorization (RMA) number and have the following information available: model number, serial number, name and address of person returning the product and a description of the problem experienced. Carefully package the product in its original antistatic material, if it is still available, and ship it us: prepaid (if within the US) or free domicile DDP (if outside the US). Show the RMA number on the outside of the package and include a written description of the malfunction. When the work is completed, we will return the product you free of charge, along with a statement of work done, if under warranty. Out-of-warranty work will be charged on a material and service time basis, and we will be happy quote you a cost estimate for the repair and return shipping before proceeding. 35

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