Cobalt/Onyx Selection Chart. A/D Converters D/A Converters Other Qty Rate Bits Qty Rate Bits Features MHz MHz 16

Transcription

1 Last Updated: May 2014

2 Contents Xilinx Performance... 3 The Cobalt/Onyx Architecture... 4 Cobalt/Onyx Formats & Interfaces... 9 Support Software Models 720 & 71720: Transceiver with Three s, DUC, Two s, Virtex-6 & Virtex-7 s - XMC... Model 721: Transceiver with Three s, DDCs, DUC, Two s - XMC Models 730 & 71730: 1 GHz, 1 GHz, Virtex-6 & Virtex-7 s - XMC Model 740: 1-Channel 3.6 GHz or 2-Channel 1.8 GHz, 12-bit, Virtex-6 - XMC Model 741: 1-Channel 3.6 GHz or 2-Channel 1.8 GHz, 12-bit, with DDC, Virtex-6 - XMC Model 71741: 1-Channel 3.6 GHz or 2-Channel 1.8 GHz, 12-bit, with DDC, Virtex-6 - XMC Model 750: Transceiver with Two s, DUC, Two s, Virtex-6 - XMC Model 751: Transceiver with Two s, DDC, DUC, Two s, Virtex-6 - XMC Model 71751: Transceiver with Two s, DDC, DUC, Two s, Virtex-7 - XMC Models 760 & 71760: 4-Channel 200 MHz, Virtex-6 & Virtex-7 s - XMC Model 761: 4-Channel 200 MHz with DDCs and Beamformer, Virtex-6 -XMC Model 762: 4-Channel 200 MHz with 32-Channel DDC, Virtex-6 - XMC Model 763: 1100 GSM Channelizer with Quad 200, Virtex-6 - XMC Model 770: 4-Channel 1.25 GHz with DUC, Virtex-6 - XMC Model 771: 4-Channel 1.25 GHz with DUC, Extended Interpolation, Virtex-6 - XMC Model 71771: 4-Channel 1.25 GHz with DUC, Extended Interpolation, Virtex-7 - XMC Model 790: L-Band Tuner with 2-Channel 200 MHz, Virtex-6 - XMC Performance Graphs Model 710: LVDS Digital I/O with Virtex-6 - XMC Model 711: Quad Serial FPDP Interface with Virtex-6 - XMC Model 7192: High-Speed Synchronizer and Distribution Board - PMC/XMC Model 9192: Rackmount High-Speed System Synchronizer Unit Model 7893: System Synchronizer and Distribution Board Model 7194: High-Speed Clock Generar - PMC/XMC Model 8266: PC Development System for Cobalt and Onyx Boards Cusmer Information Converters Converters Other Qty Rate Bits Qty Rate Bits Features MHz MHz MHz MHz 3 DDCs, Sum, Int MHz Cobalt/Onyx Selection Chart MHz 4 DDCs, Sum MHz 32 DDCs, Sum MHz 1100 DDCs MHz L-Band Tuner MHz MHz MHz MHz 2 DDCs, Int MHz MHz MHz MHz 2 DDCs, Int GHz GHz /2 3.6/1.8 GHz /2 3.6/1.8 GHz 12 1/2 DDCs, GHz GHz Extended Int 710 LVDS I/O 711 Quad sfpdp Rate = Maximum Sampling Frequency DDC = Digital Downconverter Int = Interpolation Filter sfpdp = Serial FPDP VITA 17.1 Sum = Beamforming Summation Block & Aurora Chaining Interface 2

3 Xilinx Performance The Latest Generations of Virtex s With each new generation of devices, Xilinx continues push the performance envelope match the ever increasing requirements of target applications. The announcement of the Virtex-6 and Virtex-7 were no exception. More processing power, lower power consumption, and updated interface features match the latest technology I/O requirements, are all part of these new devices. While it might be easy assume that faster, bigger, more powerful is better, it s important understand how the latest innovations actually deliver this higher performance best match the device the specific requirements of the application. One of the standard metrics for s is the number of logic cells. This figure shows the steady improvement in the last four generations of Xilinx s starting with the Virtex-4 and continuing the Virtex-7. The graph displays the number of logic cells contained in a range of different density devices offered in a 35 mm x 35 mm BGA (Ball-Grid Array) package. This clearly shows the dramatic increase in resource density, bounded by the constraints of the size and power dissipation capacity of a given package. Since Virtex-4 CLBs (Configurable Logic Blocks) comprise eight logic cells, while Virtex-5 and Virtex-6 CLBs comprise 12, the increase in logic cells between Virtex-4 and Virtex-5 actually translates a decrease in CLBs because each CLB in the Virtex-5 requires more logic cells. While the Virtex-5 CLBs are more powerful than their Virtex-4 counterparts, there are still fewer of them use. What is also clear from this graph is that the Virtex-6 represents a significant increase in density from the Virtex-5 family. The Virtex-7 offers the highest performance thus far with twice the performance and twice the resources of the Virtex-6. The Virtex-7 devices feature lowpower 28 nm process technology implement up 3.1 Tbits/sec of I/O and up 2 million logic cells. They provide up 6.7 TMACs of DSP resources, especially important for software radio applications. Because of new process technologies and other power management schemes, they consume half the power of Virtex-6 for a given function. This combination of lower power and higher performance for each of the key resources benefits software radio, opens up new product markets, and extends the capabilities of existing applications. Logic Cells In Thousands T T 485T 550T 585T T LX195T LX130T LX240T SX315T LX356T SX475T LX40 LX/SX50T FX70T LX85T SX95T LX/FX110T LX155T Virtex-7 SX55 LX0 Virtex-6 LX/FX60 LX80 LXFX100 Virtex-5 Smaller Devices Larger Devices Virtex-4 Logic Cell Density Comparison, Virtex-4, Virtex-5, Virtex-6, and Virtex-7 s Used in Pentek Products 3

4 The Cobalt & Onyx Architecture Features and Implementation Cobalt & Onyx Architectural Features Cobalt : Xilinx Virtex-6 Onyx : Xilinx Virtex-7 Configurable memory resources depending on model On-board clocking and synchronization Modular I/O design support a wide range of signal types I/O Module The I/O module is a separate printedcircuit board that caries all of the analog interface circuitry providing excellent isolation from noise. Typical front panel signals include analog in and out, clocking, sync, and triggering. Cobalt & Onyx Performance Features sampling rates from 10 MHz 3.6 GHz sampling rates up 1.25 GHz Powerful linked-list DMA engines PCI Express as the primary control and data transfer interface Secondary serial gigabit interface All models available in XMC, PCI Express, OpenVPX and CompactPCI formats Available in commercial and in several ruggedization levels up and including conduction cooling y Resources These two smaller boards are used for the memory resources allowing for cusmization of two types of memory depending on model. Main Board The main board serves as the foundation of all Cobalt and Onyx products. It houses the, FLASH memory, XMC interfaces, user programmable interfaces and hosts the memory and I/O modules. Flexible Architecture The modularity of this assembly offers an unprecedented degree of flexibility for creating Cobalt or Onyx modules with completely different features by just incorporating different I/O modules. As shown in the diagram, the front panel allows for a maximum of six SSMC signal connecrs. The external clocking, trigger and synchronization connecr is a front-panel multipin flat cable connecr and is the same on all models, except those designed operate at frequencies higher than 1.0 GHz. 4

5 The Cobalt & Onyx Architecture Components and Circuitry Cobalt or Onyx I/O Module Shown here is a typical Cobalt or Onyx I/O module. The input analog ports are transformer-coupled two high-speed converters. The digital outputs are delivered in the Virtex-6 or Virtex-7 for signal processing, data capture or for routing other module resources. Besides the two s, the typical module could include one DUC (Digital Upconverter), and two s which are transformer-coupled the output analog ports. In addition the input and output ports, the module includes a multiport connecr for clocking and synchronization. All connecrs are on the front panel. TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate Gate Sync / PPS Sync / PPS Timing Bus VCXO Sample Clk / Reference Clk In TIMING BUS Clock / Sync /Gate / PPS CONFIG FLASH ONYX Only Clock/Sync Bus Clock/Sync Bus Config Bus 8X GATEXPRESS CONFIGURATION MANAGER P15 XMC In CONFIG FLASH 64 MB COBALT Only 8X P15 XMC In COBALT: VIRTEX-6 LX130T, LX240T or SX315T ONYX: VIRTEX-7 VX330T or VX690T LVDS Option -105 Serial I/O P XMC 40 Cobalt 48 Onyx Option -104 GPIO P14 PMC Out DIGITAL UPCONVERTER Cobalt Configurations Out Xilinx Virtex-6 or Virtex-7 The Cobalt Virtex-6 site can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, or SX315T. The Onyx Virtex-7 site can be populated with one of two s match the specific requirements of the processing task. Supported s are: VX330T or VX690T. The SX315T features 1344 DSP48E slices, while the VX690T features 3600 DSP48E1 slices. These devices are ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. Onyx Configuration FLASH Cobalt: The -bit wide 64 MB FLASH provides non-volatile memory for facry boot code, self-test, and user parameters Onyx: The -bit wide 1024 MB FLASH provides non-volatile memory for facry boot code, self-test, user parameters, and images for dynamically reconfiguring the. y Resources Cobalt: Up four independent memory banks can be configured with all,, or as combination of two banks of each memory type. Each bank can be up 8 MB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, banks can each be up deep. 5 Onyx: Four independent memory banks are available. Each bank is 1 GB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include an data transient capture mode and waveform playback mode. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. More on next page

6 The Cobalt & Onyx Architecture Components and Circuitry Clocking and Synchronization The internal timing buses provide either a single clock or two different clock rates the and signal paths. The timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generar receives an external sample clock which can be used directly for either the or sections or can be divided by a built-in clock synthesizer circuit provide different and clocks. In an alternate mode, the sample clock can be sourced from an onboard programmable VCXO (Voltage-Controlled Crystal Oscillar). In this mode, the synthesizer locks the VCXO an external system reference, typically 10 MHz. A front panel 26-pin LVPECL Clock/ Sync connecr allows multiple boards be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate Gate Sync / PPS Sync / PPS Timing Bus Sample Clk / Reference Clk In Clock/Sync Bus Clock/Sync Bus In In Out DIGITAL UPCONVERTER Out VCXO TIMING BUS Clock / Sync /Gate / PPS COBALT: VIRTEX-6 LX130T, LX240T or SX315T ONYX: VIRTEX-7 VX330T or VX690T LVDS CONFIG FLASH ONYX Only Config Bus 8X GATEXPRESS CONFIGURATION MANAGER P15 XMC CONFIG FLASH 64 MB COBALT Only 8X P15 XMC Option -105 Serial I/O P XMC 40 Cobalt 48 Onyx Option -104 GPIO P14 PMC Cobalt Configurations Onyx Configuration Available only in the Onyx series, the GateXpress TM is a sophisticated configuration manager for loading and reloading the. At powerup, GateXpress presents a target for the host computer discover, effectively giving the time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window. The board s configuration FLASH can hold up four images for dynamically reconfiguring the. Board Interfaces The is also used implement the primary board interfaces. The basic XMC module shown here is also available in different formats, such as PCI Express, OpenVPX, and CompactPCI. More information about formats and interfaces starts on page 9. 6

7 The Cobalt & Onyx Architecture TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate Gate Sync / PPS Sync / PPS Timing Bus Sample Clk / Reference Clk In Clock/Sync Bus Clock/Sync Bus In In Out DIGITAL UPCONVERTER Out VCXO TIMING BUS Clock / Sync /Gate / PPS ONYX: VIRTEX-7 VX330T or VX690T LVDS CONFIG FLASH ONYX Only Config Bus 8X GATEXPRESS CONFIGURATION MANAGER P15 XMC Option -105 Serial I/O P XMC 40 Cobalt 48 Onyx Option -104 GPIO P14 PMC GateXpress for Configuration The Onyx architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load from FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on most PCs. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first is the option load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred on the host computer and loaded through as needed. The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. 7

8 The Cobalt & Onyx Architecture Dataflow All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering, and memory control. The Cobalt & Onyx Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt/Onyx family is delivered with facry-installed applications ideally matched the board s analog interfaces. Depending on model, the facry-installed functions may include acquisition and waveform playback IP modules. IP modules for either or (Cobalt only) memories, a controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facryinstalled functions and enable the board operate as a complete turnkey solution without the need develop any IP. For applications that require specialized functions, users can install cusm IP for data processing. Pentek GateFlow Design Kits (described later in this catalog) include all of the facry installed modules as documented source code. Developers can integrate their IP with the Pentek facry-installed functions or use the GateFlow completely replace the Pentek IP with theirs. Acquisition IP Modules This typical Cobalt/Onyx module includes two Acquisition IP modules for easy capture and data moving. Each IP module can receive data from either of the two s, a test signal generar or from the Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. Bank 1 DATA PACKING & FLOW METADATA ACQUISITION IP MODULE 1 from Ch 1 from Ch 2 INPUT MULTIPLEXER Bank 2 DATA PACKING & FLOW METADATA ACQUISITION IP MODULE 2 Waveform Playback IP Module Facry-installed functions for this typical Cobalt/Onyx module include a sophisticated Waveform Playback IP module. A linked-list controller allows users easily play back waveforms sred in either on-board memory or off- board host memory the dual s. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. loopback TEST SIGNAL Bank 3 DATA UNPACKING & FLOW WAVEFORM PLAYBACK IP MODULE VIRTEX-6/VIRTEX-7 DATAFLOW DETAIL INTEACE (supports user installed IP) Bank 1 Bank 2 Bank 3 Bank 4 8X 40 Gigabit Serial I/O GPIO 8

9 Cobalt & Onyx Formats & Interfaces XMC Format Here is a phograph of the typical board reviewed in detail in the previous section. In its XMC configuration, each Cobalt or Onyx module complies with the VITA 42.0 XMC specification and is suitable for mounting on motherboards with PMC/XMC connecrs. All XMC modules are available in commercial and in several ruggedization levels up and including conduction cooling. The XMC format applies the Model 71xxx product family. TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate Gate Sync / PPS Sync / PPS Timing Bus Sample Clk / Reference Clk In Clock/Sync Bus Clock/Sync Bus In In Out DIGITAL UPCONVERTER Out VCXO TIMING BUS Clock / Sync /Gate / PPS COBALT: VIRTEX-6 LX130T, LX240T or SX315T ONYX: VIRTEX-7 VX330T or VX690T LVDS CONFIG FLASH ONYX Only Config Bus P15 XMC 8X GATEXPRESS CONFIGURATION MANAGER CONFIG FLASH 64 MB COBALT Only 8X P15 XMC Option -105 Serial I/O P XMC 40 Cobalt 48 Onyx Option -104 GPIO P14 PMC Cobalt Configurations Onyx Configuration PCI Express Interface The Cobalt XMC includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Gen. 2 provides 4 GB/sec peak data transfer rate. The Onyx XMC includes an industrystandard interface fully compliant with PCI Express Gen. 1, 2 & 3 bus specifications. Gen. 3 provides 8 GB/sec peak transfer rate. The x8 interface includes multiple DMA controllers for efficient transfers and from the module. XMC Interface Both Cobalt and Onyx XMC products comply with the VITA 42.0 XMC specification. Each of the two connecrs provides dual links or a single 8X link. With dual XMC connecrs, the XMC products support both x4 and x8 on the first XMC connecr leaving the second connecr free support userinstalled transfer procols specific the target application. Optional Interfaces Option -104 installs the P14 PMC connecr with 20 pairs of LVDS connections (Cobalt) or 24 pairs (Onyx) the for cusm I/O. Option -105 installs the P XMC connecr with a single 8X or dual gigabit links the support serial procols. 9

10 Cobalt & Onyx Formats & Interfaces PCI Express Format The PCI Express format shown here is suitable for mounting in PCs with connecrs and interfaces. Physically, the XMC module reviewed in the previous page is mounted on a PCI Express carrier board with x8 motherboard connecrs. Other connecrs provide additional interfaces as described below. The unique design of the carrier includes an integrated fan that keeps the module cool even in demanding situations while still requiring a single slot. TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate Gate Sync / PPS Sync / PPS Timing Bus Sample Clk / Reference Clk In Clock/Sync Bus Clock/Sync Bus In In Out DIGITAL UPCONVERTER Out VCXO TIMING BUS Clock / Sync /Gate / PPS COBALT: VIRTEX-6 LX130T, LX240T or SX315T ONYX: VIRTEX-7 VX330T or VX690T LVDS CONFIG FLASH Config Bus 8X GATEXPRESS CONFIGURATION MANAGER CONFIG FLASH 64 MB 8X Option -105 Serial I/O 40 Cobalt 48 Onyx Option -104 GPIO Cobalt Configurations ONYX Only COBALT Only Dual Serial Conn 68-pin Header x8 PCI Express x8 PCI Express Onyx Configuration PCI Express Interface The Cobalt board includes an industry-standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Gen. 2 provides 4 GB/sec peak data transfer rate. The Onyx board includes an industry-standard interface fully compliant with PCI Express Gen. 1, 2 & 3 bus specifications. Gen. 3 provides 8 GB/sec peak transfer rate. The x8 interface includes multiple DMA controllers for efficient transfers and from the module. Optional Interfaces Option -104 connects 20 pairs of LVDS connections (Cobalt) or 24 pairs (Onyx) from the on PMC P14 a 68-pin DIL ribbon-cable header on the board for cusm I/O. Option -105 connects two gigabit serial links from the on XMC P two gigabit serial connecrs along the p edge of the board. 10

11 Cobalt & Onyx Formats & Interfaces 3U OpenVPX Format 1 The OpenVPX Format 1 is compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPX TM System Specification) Shown here is the 3U OpenVPX COTS version (left) and the rugged version which is available in several ruggedization levels up and including conduction cooling. Another OpenVPX format is described in the next page. TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate Gate Sync / PPS Sync / PPS Timing Bus Sample Clk / Reference Clk In Clock/Sync Bus Clock/Sync Bus In In Out DIGITAL UPCONVERTER Out VCXO TIMING BUS Clock / Sync /Gate / PPS COBALT: VIRTEX-6 LX130T, LX240T or SX315T ONYX: VIRTEX-7 VX330T or VX690T LVDS CONFIG FLASH Config Bus ONYX Only 8X GATEXPRESS CONFIGURATION MANAGER VPX BACKPLANE CONFIG FLASH 64 MB COBALT Only CROSSBAR SWITCH Gbit Gbit Serial Serial VPX-P1 8X Gbit Serial Gbit Serial Option -105 Serial I/O 40 VPX-P2 Option -104 GPIO Cobalt Configurations Onyx Configuration PCI Express Interface The Cobalt 3U OpenVPX board includes an industry-standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Gen. 2 provides 4 GB/sec peak data transfer rate. The Onyx 3U OpenVPX board includes an industry-standard interface fully compliant with PCI Express Gen. 1, 2 & 3 bus specifications. Gen. 3 provides 8 GB/sec peak transfer rate. The x8 interface includes multiple DMA controllers for efficient transfers and from the board. Fabric-Transparent ransparent Crossbar Switch The 3U OpenVPX Cobalt or Onyx board features a unique high-speed switching configuration. A fabric-transparent crossbar switch bridges numerous interfaces and components on the board using gigabit serial data paths with no latency. Programmable signal input equalization and output pre-emphasis settings enable optimization. Data paths can be selected as single (1X) lanes, or groups of four lanes () for routing over the VPX-P1 connecr. 11 Optional Interfaces Option -104 provides 20 pairs of LVDS connections between the and the VPX-P2 connecr for cusm I/O. Option -105 connects two gigabit serial links from the on XMC P the crossbar switch for routing VPX-P1.

12 Cobalt & Onyx Formats & Interfaces 3U OpenVPX Format 2 The OpenVPX Format 2 is compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPX TM System Specification) Shown here is the 3U OpenVPX COTS version (left) and the rugged version which is available in several ruggedization levels up and including conduction cooling. A comparison of the two OpenVPX formats is given in the table below. TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate Gate Sync / PPS Sync / PPS Timing Bus Sample Clk / Reference Clk In Clock/Sync Bus Clock/Sync Bus In In Out DIGITAL UPCONVERTER Out VCXO TIMING BUS Clock / Sync /Gate / PPS COBALT: VIRTEX-6 LX130T, LX240T or SX315T ONYX: VIRTEX-7 VX330T or VX690T LVDS CONFIG FLASH Config Bus ONYX Only Gen. 2 x4 GATEXPRESS CONFIGURATION MANAGER CONFIG FLASH 64 MB COBALT Only Gen. 2 x4 VPX-P1 Option -105 Serial I/O 40 VPX-P2 Option -104 GPIO Cobalt Configurations Onyx Configuration VPX BACKPLANE PCI Express Interface Both Cobalt and Onyx boards include an industry-standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x4 interface includes multiple DMA controllers for efficient transfers and from the board. Optional Interfaces Option -104 installs 20 pairs of LVDS connections (Cobalt) or 24 pairs (Onyx) between the and VPX-P2 for cusm I/O. Option -105 connects two gigabit serial links from the VPX-P1 support serial procols. OpenVPX Families By omitting the Format 1 Crossbar switch, Format 2 products achieve significant reductions in power and price. These and other differences are shown in the comparison table. 12 Form Facr # of XMCs Crossbar Switch path Option -104 path Option -105 path Lowest Power OpenVPX Family Comparison Format 2 No VPX P1 24 pairs on VPX P2 Two x4 or one x8 on VPX P1 Yes 3U OpenVPX One XMC Format 1 Yes VPX P1 or P2 width x4 x8 Lowest Price Yes 20 pairs on VPX P2 Two x4 or one x8 on VPX P1 or P2 No No

13 Cobalt & Onyx Formats & Interfaces AMC Format Module Management The AMC format complies with the AMC.1 specification by providing an x8 connection AdvancedTCA carriers or µtca chassis. Module management is provided by an IPMI 2.0 MMC (Module Management Controller). TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate Gate Sync / PPS Sync / PPS Timing Bus Sample Clk / Reference Clk In Clock/Sync Bus Clock/Sync Bus In In Out DIGITAL UPCONVERTER Out VCXO TIMING BUS Clock / Sync /Gate / PPS COBALT: VIRTEX-6 LX130T, LX240T or SX315T ONYX: VIRTEX-7 VX330T or VX690T LVDS CONFIG FLASH ONYX Only Config Bus 8X GATEXPRESS CONFIGURATION MANAGER Gen. 3 x8 CONFIG FLASH 64 MB 8X Gen. 2 x8 COBALT Only AMC Ports 411 x8 PCI Express IPMI LER RS-232 Front Panel 40 Cobalt 48 Onyx Option -104 GPIO Front Panel Cobalt Configurations Onyx Configuration PCI Express Interface The Cobalt AMC module includes an industry-standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 interface includes multiple DMA controllers for efficient transfers and from the board. The Onyx AMC module includes an industry-standard interface fully compliant with PCI Express Gen. 1, 2 & 3 bus specifications. The x8 interface includes multiple DMA controllers for efficient transfers and from the board. Module Management The Module Management Controller complies with the IPMI 2.0 MMC specification. 13 Optional Interface Option -104 installs a front panel connecr with 20 pairs of LVDS connections the for cusm I/O.

14 Cobalt & Onyx Formats & Interfaces CompactPCI Formats As shown here, the CompactPCI format is available in three configurations: 6U cpci with double density; this configuration mounts two XMC modules on a 6U carrier board. 6U cpci with single density; this configuration mounts only one XMC module on a 6U carrier board. 3U cpci mounts one XMC module on a 3U carrier board In order describe these three configurations in more detail, we have omitted the components and circuitry shown in the previous three formats; we just show the Virtex-6/Virtex-7 s with the external connections that define the standard and optional interfaces. LVDS VIRTEX-6/VIRTEX-7 1st XMC MODULE VIRTEX-6/VIRTEX-7 2nd XMC MODULE LVDS 6U cpci Double Density Two --PCI bridges connect the x4 interfaces from each XMC module a PCI--PCI bridge. This bridge connects both modules the 32- or 64-bit, 33/66 MHz PCI/PCI-X bus. 40 x4 x4 x4 x4 40 Config Config Bus Bus Option -104 GPIO CONFIG FLASH cpci J3 ONYX Only GATEXPRESS CONFIGURATION MANAGER x4 PCI BRIDGE 6U cpci Optional Interface CONFIG FLASH 64 MB COBALT Only PCI/PCI-X Bus Option -104 provides 20 pairs of LVDS connections between the and the J3 connecr for cusm I/O. The J5 connecr supports Option -104 for the 2nd XMC module. PCI PCI BRIDGE CONFIG FLASH 64 MB COBALT Only PCI BRIDGE 32/64-bit, 33/66 MHz GATEXPRESS CONFIGURATION MANAGER x4 6U cpci Single Density CONFIG FLASH ONYX Only Option -104 GPIO cpci J5 The 2nd XMC module, its associated --PCI bridge, and the optional interface connection J5 are not present. LVDS VIRTEX-6/VIRTEX-7 40 Option -104 GPIO CONFIG FLASH ONYX Only Config Bus GATEXPRESS CONFIGURATION MANAGER x4 x4 x4 PCI BRIDGE CONFIG FLASH 64 MB COBALT Only 3U cpci Single Density A --PCI bridge connects the x4 interface from the XMC module the 32-bit, 33/66 MHz PCI/PCI-X bus. cpci J3 PCI/PCI-X Bus 32-bit, 33/66 MHz 3U cpci Optional Interface Option -104 provides 20 pairs of LVDS connections between the and the J3 connecr for cusm I/O. 14

15 Support Software Pentek ReadyFlow Board Support Package Users of high-performance data acquisition and signal processing boards often find themselves frustrated by the fact that when their new devices are delivered, they are unable put them immediate use. To address this issue, Pentek has developed the ReadyFlow BSPs (Board Support Packages) for all of its board-level products. The package contains C-language examples that demonstrate the capabilities of Pentek products. The examples included provide the answers most of the questions that occur with firsttime users of these products. ReadyFlow BSPs are designed reduce development time during the initial stages and when new hardware is added the system. All packages are built with a consistent style and functionnaming convention. Similar parameters on different boards have similar function calls, thereby allowing immediate familiarity with new hardware. Command Line Interface The Command Line Interface is a precompiled executable that runs the hardware right out of the box, without the need write any code. Specific the hardware features of the supported board, it allows operating arguments be entered on the command line for controlling board parameters. For command line functions that control data acquisition, the captured data can be saved in a host file or routed the Signal Analyzer. Signal Analyzer When used with the Command Line Interface, the Signal Analyzer allows users immediately. start acquiring and displaying data. A full-featured analysis ol, the Signal Analyzer displays data in time and frequency domains. Built-in measurement functions display 2nd and 3rd harmonics, THD (tal harmonic disrtion), and SINAD (signal noise and disrtion). Interactive cursors allow users mark data points and instantly calculate amplitude and frequency of displayed signals. Pentek GateFlow Design Kit Using the Design Kit The GateFlow Design Kit allows the user modify, replace and extend the standard facry-installed functions in the incorporate special modes of operation, new control structures, and specialized signal-processing algorithms. The Cobalt or Onyx architecture configures the with standard facry-supplied interfaces including memory controllers, DMA engines, and interfaces, timing and synchronization structures, triggering and gating logic, time stamping and header tagging, data formatting engines, and the interface. These resources are connected the User Application Container using well-defined ports that present easy--use data and control signals, effectively abstracting the lower level details of the hardware. The User Application Container Shown here is the block diagram of a typical Cobalt/Onyx module. The User Application Container holds a collection of different facry-installed IP modules connected the various interfaces through the standard ports surrounding the container. The specific IP modules for each product are described in further detail in the following pages. The GateFlow Design Kit provides a complete Xilinx ISE Foundation Tool project folder containing all the files Sync Bus Interface Clock Generar Controller Controller Global Registers FLASH Interface 15 Board Registers User Application Container PCI Express Backend PCI Express Interface necessary for the developer recompile the entire project with or without any required changes. VHDL source code for each IP module provides excellent examples of how the IP modules work, how they might be modified, and how they might be replaced with cusm IP implement a specific function. Front Panel Interface Facry Installed Base Function Application & Control Data Packing & Formatting Meta Data Files Linked-List Control Linked-List Control User Registers DMAs P14 LVDS P MGTs Timestamp Test Generar Controller Controller Defined and documented interface signals V-6orV-7-

16 Models 720 & 71720: Transceiver with Three s, DUC, Two s - XMC Features Model 720 Model 720 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6. Model is a member of the Onyx family of high-performance modules based on the Virtex-7. These multichannel, high-speed data converters, are suitable for connection HF or IF ports of a communications or radar system. Their built-in data capture and playback features offer an ideal turnkey solution. Each model includes three s, one DUC, two s and four banks of memory. In addition supporting PCI Express as a native interface, these models include general-purpose and gigabit serial connecrs for applicationspecific I/O. Model Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT or Virtex-7 VXT s Model 71720: GateXpress supports dynamic reconfiguration across Three 200 MHz -bit s One digital upconverter Two 800 MHz -bit s Model 720: Up 2 GB of or 32 MB of ; Model 71720: 4 GB of Sample clock synchronization an external system reference LVPECL clock/sync bus for multimodule synchronization Model 720: PCI Express (Gen. 1 & 2) interface up x8; Model 71720: PCI Express (Gen. 1, 2, and 3) interface up x8 Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O Converters The front end accepts three full-scale analog HF or IF inputs on front panel SSMC connecrs at +8 dbm in 50 ohms with transformer coupling in three Texas Instruments ADS MHz, -bit converters. The digital outputs are delivered in the Virtex-6 or Virtex-7 for signal processing, data capture or for routing other module resources. Sample Clk / Reference Clk In TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate Gate Sync / PPS Sync / PPS Timing Bus TIMING BUS Clock / Sync / Gate / PPS VCXO CONFIG FLASH Clock/Sync Bus Clock/Sync Bus ONYX Only Config Bus P15 XMC 8X GATEXPRESS CONFIGURATION MANAGER 200 MHz -BIT CONFIG FLASH 64 MB COBALT Only 8X 200 MHz -BIT P15 XMC Digital Upconverter and s A TI DAC5688 DUC (digital upconverter) and accepts a baseband real or complex data stream from the which is optionally interpolated, upconverted and then delivered the two s. When operating as a DUC, it interpolates and translates real or complex baseband input signals any IF center frequency up 360 MHz. It delivers real or quadrature (I+Q) digital outputs the dual -bit converter. Analog output is through a pair of front panel SSMC connecrs. If translation is disabled, the DAC5688 acts as a dual interpolating -bit with output sampling rates up 800 MHz. In both modes the DAC5688 provides interpolation facrs of 2x, 4x and 8x. In In In Out Out COBALT: VIRTEX-6 LX130T, LX240T, or SX315T ONYX: VIRTEX-7 VX330T or VX690T LVDS Option -105 Serial I/O P XMC 200 MHz -BIT 40 Cobalt 48 Onyx Option -104 GPIO P14 PMC 800 MHz 800 MHz -BIT -BIT DIGITAL UPCONVERTER 32 Cobalt Configurations Contact Pentek for availability of rugged and conduction-cooled versions Onyx Configuration

17 Models 720 & 71720: Transceiver with Three s, DUC, Two s - XMC Installed IP Modules The facry-installed functions in both models include three acquisition and a waveform playback IP modules, ideally matched the board s analog interfaces. IP modules for either or memories, a controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facryinstalled functions and enable these models operate as complete turnkey solutions, without the need develop any IP. Acquisition IP Modules Both models feature three Acquisition IP Modules for easily capturing and moving data. Each module can receive data from any of the three s, a test signal generar or from the Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. Bank 1 DATA PACKING & FLOW METADATA ACQUISITION IP MODULE 1 from Ch 1 Bank 2 from Ch 2 from Ch 3 INPUT MULTIPLEXER DATA PACKING & FLOW METADATA ACQUISITION IP MODULE 2 Waveform Playback IP Module The facry-installed functions in both models include a sophisticated Waveform Playback IP module. A linked-list controller allows users easily play back the dual s waveforms sred in either on-board memory or off-board host memory. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. loopback Bank 3 DATA PACKING & FLOW METADATA ACQUISITION IP MODULE 3 TEST SIGNAL Bank 4 DATA UNPACKING & FLOW WAVEFORM PLAYBACK IP MODULE VIRTEX-6/VIRTEX-7 DATAFLOW DETAIL INTEACE (supports user installed IP) Bank 1 Bank 2 Bank 3 Bank 4 8X 40 Model 720 Gigabit Serial I/O GPIO 48 Model

18 Models 720 & 71720: Transceiver with Three s, DUC, Two s - XMC Also Available Specifications Model Format x8 PCI Express U OpenVPX - Format U OpenVPX - Format AMC U cpci - Single Density U cpci - Single Density U cpci - Double Density Model Format x8 PCI Express U OpenVPX - Format U OpenVPX - Format AMC U cpci - Single Density U cpci - Single Density U cpci - Double Density Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with interpolation Resolution: bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one clock and one clock Clock Synthesizer Clock Source: Selectable from onboard programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, independently for the clock and clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus: 26-pin connecr LVPECL bus includes, clock/sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/pps inputs Model 720 Xilinx Virtex-6 Standard: CXC6VLX130T Optional: XC6VLX240T, or XC6VSX315T Model Xilinx Virtex-7 Standard: XC7VX330T-2 Optional: XC7VX690T-2 Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs ( Model 720) or 24 pairs (Model 71720) the Option -105: Installs the XMC P connecr configurable as one 8X or two gigabit serial links the Model 720 Option 150 or 0: Two 8 MB memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR Model Type: Size: Four banks, 1 GB each PCI-Express Interface Model 720 PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Model PCI Express Bus: Gen. 1, 2 or 3: x4 or x8; Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard XMC module, 2.91 in. x 5.87 in. 18

19 Model 721: Transceiver with Three s, DDCs, DUC, Two s - XMC The model 721 consists of a Model 720 as described previously, but with the addition of three multiband DDCs, one interpolar and one beamformer IP Cores installed in the Virtex-6. These IP Cores are in addition the facry-installed IP Modules described in the Model 720. DDC IP Cores Within each Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the Acquisition IP Modules, many different configurations can be achieved including one driving all three DDCs or each of the three s driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges from DC ƒ s, where ƒ s is the sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as three different output bandwidths for the board. Decimations can be programmed from 2 65,536 providing a wide range satisfy most applications. The decimating filter for each DDC accepts a unique set of usersupplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*ƒ s /N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 db. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or-bit I + -bit Q samples at a rate of ƒ s /N. Interpolar IP Core The DAC5688 provides interpolation facrs of 2x, 4x and 8x. In addition the DAC5688, an -based interpolar core provides additional interpolation from 2x 65,536x. The two interpolars can be combined crate a tal range from 2x 524,288x. Beamformer IP Core In addition the DDCs, the 721 features a complete beamforming subsystem. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up 8K samples. The power meters present average power measurements for each DDC core output in easy--read registers. next board Bank 1 AURORA GIGABIT SERIAL INTEACE sum out SUMMER sum in BEAMFORMER CORE from previous board DDC DEC: 2TO POWER METER & THRESHOLD DETECT DATA PACKING & FLOW METADATA ACQUISITION IPMODULE 1 from Ch 1 from Ch 2 from Ch 3 INPUT MULTIPLEXER DDC DEC: 2TO POWER METER & THRESHOLD DETECT DATA PACKING & FLOW METADATA METADATA Bank 2 Bank 3 ACQUISITION IPMODULE 2 loopback DDC DEC: 2TO POWER METER & THRESHOLD DETECT DDC CORE DDC CORE DDC CORE In addition, each DDC core includes a threshold detecr aumatically send an interrupt the processor if the average power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the three DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back in the Acquisition IP Module 1 FIFO for reading over the. For larger systems, multiple 721 s can be chained gether via a built-in Xilinx Aurora gigabit serial interface through the P XMC connecr. This allows summation across channels on multiple boards. DATA PACKING & FLOW ACQUISITION IPMODULE 3 VIRTEX-6 DATAFLOW DETAIL TEST SIGNAL Bank 4 INTEACE WAVEFORM PLAYBACK IP MODULE 8X INTERPOLATOR 2TO IP CORE DATA UNPACKING & FLOW 19

20 Model 721: Transceiver with Three s, DDCs, DUC, Two s - XMC Also Available Specifications Model Format x8 PCI Express U OpenVPX - Format U OpenVPX - Format AMC U cpci - Single Density U cpci - Single Density U cpci - Double Density Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Digital Downconverters Quantity: Three channels Decimation Range: 2x 65,536x in two stages of 2x 256x LO Tuning Freq. Resolution: 32 bits, 0 ƒ s LO SFDR: >120 db Phase Offset Resolution: 32 bits, degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 db passband ripple, >100 db spband attenuation Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: bits Digital Interpolar Interpolation Range: 2x 65,536x in two stages of 2x 256x Beamformer Summation: Three channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connecr using Aurora procol Phase Shift Coefficients: I & Q with -bit resolution Gain Coefficients: -bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Front Panel Analog Signal Outputs Output: Transformer-coupled, front panel female SSMC connecrs Transformer: Coil Craft WBC4-6TLB 20 Full Scale Output: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one clock and one clock Clock Synthesizer Clock Source: Selectable from onboard programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, independently for the clock and clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus: 26-pin connecr LVPECL bus includes, clock/sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/pps inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option 150 or 0: Two 8 MB memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard XMC module, 2.91 in. x 5.87 in.

21 Models 730 & 71730: 1 GHz, 1 GHz - XMC Model 730 Model 730 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6. Model is a member of the Onyx family of high-performance modules based on the Virtex-7 PGA. These high-speed data converters are suitable for connection HF or IF ports of a communications or radar system. Their built-in data capture and playback features offer an ideal turnkey solution. Each model includes a 1 GHz and a 1 GHz converter and four banks of memory. In addition supporting PCI Express as a native interface, these models include optional general purpose and gigabit serial connecrs for application-specific I/O. Model Features Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT or Virtex-7 s Model 71730: GateXpress supports dynamic reconfiguration across One 1 GHz 12-bit One 1 GHz -bit Model 730: Up 2 GB of or 32 MB of ; Model 71730: 4 GB of Sample clock synchronization an external system reference LVPECL sync bus for multimodule synchronization Dual-µSync clock/sync bus for multimodule synchronization Model 730: PCI Express (Gen. 1 & 2) interface up x8; Model 71730: PCI Express (Gen. 1, 2 and 3) interface up x8 Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O Contact Pentek for availability of rugged and conduction-cooled versions Converter The front end accepts an analog HF or IF input on a front panel SSMC connecr with transformer coupling in a Texas Instruments ADS GHz, 12-bit converter. The digital outputs are delivered in the Virtex-6 or -7 for signal processing, data capture or for routing other module resources. Sample Clk / Reference Clk In TTL PPS/Gate/Sync Gate In Sync In Sync Bus Gate In Sync In Sync Bus TIMING BUS Clock / Sync / Gate / PPS VCXO CONFIG FLASH ONYX Only Clock/Sync Bus Clock/Sync Bus Config Bus P15 XMC 8X GATEXPRESS CONFIGURATION MANAGER CONFIG FLASH 64 MB COBALT Only 8X P15 XMC Converter Both models feature a TI DAC5681Z 1 GHz, -bit. The converter has an input sample rate of 1 GSPS, allowing it acept full rate data from the. Additionally, the includes a 2x or 4x interpolation filter for applications that provide 1/2 or 1/4 rate input data. Analog output is transformercoupled a front panel SSMC connecr. In 1 GHz 12-BIT COBALT: VIRTEX-6 LX130T, LX240T, or SX315T ONYX: VIRTEX-7 VX330T or VX690T LVDS 12 Option -105 Serial I/O P XMC 40 Cobalt 48 Onyx Option -104 GPIO P14 PMC Out 1 GHz -BIT Cobalt Configurations Onyx Configuration 21

22 Models 730 & 71730: 1 GHz, 1 GHz - XMC Installed IP Modules The facry-installed functions in both models include an acquisition and a waveform playback IP module. In addition, IP modules for either or memories, a controller for all data clocking and synchronization functions, a test signal generar and a interface complete the facryinstalled functions and enable these models operate as complete turnkey solutions, without the need develop any IP. Acquisition IP Module Both models feature an Acquisition IP Module for easy capture and data moving. The IP module can receive data from the, a test signal generar, or from the Waveform Playback IP Module in loopback mode. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. LER Bank 1 Bank 2 from DATA PACKING & FLOW METADATA loopback INPUT MULTIPLEXER ACQUISITION IP MODULE LER Bank 3 Waveform Playback IP Module The facry-installed functions in these models include a sophisticated Waveform Playback IP module. A linked-list controller allows users easily play back waveforms sred in either on-board memory or off- board host memory the. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. TEST SIGNAL Bank 4 DATA UNPACKING & FLOW WAVEFORM PLAYBACK IP MODULE VIRTEX-6 DATAFLOW DETAIL INTEACE (supports user installed IP) Bank 1 Bank 2 Bank 3 Bank 4 8X 40 Model 730 Gigabit Serial I/O GPIO 48 Model

23 Models 730 & 71730: 1 GHz, 1 GHz - XMC Also Available Specifications Model Format x8 PCI Express U OpenVPX - Format U OpenVPX - Format AMC U cpci - Single Density U cpci - Single Density U cpci - Double Density Model Format x8 PCI Express U OpenVPX - Format U OpenVPX - Format AMC U cpci - Single Density U cpci - Single Density U cpci - Double Density Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Converter Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz 1 GHz Resolution: 12 bits Converter Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connecrs Sample Clock Sources: On-board clock synthesizer generates two clocks: one clock and one clock Clock Synthesizer Clock Source: Selectable from onboard programmable VCXO or front panel external clock VCXO Frequency Ranges: MHz, MHz, and MHz Synchronization: VCXO can be phase-locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, independently for the clock and clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts 100 MHz 1 GHz divider input clock, or PLL system reference Timing Bus: 19-pin µsync bus connecr, includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Model 730 Xilinx Virtex-6 Standard: CXC6VLX130T Optional: XC6VLX240T, or XC6VSX315T Model Xilinx Virtex-7 Standard: XC7VX330T-2 Optional: XC7VX690T-2 Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs (Model 730) or 24 pairs (Model 71730) the Option -105: Installs the XMC P connecr configurable as one 8X or two gigabit serial links the Model 730 Option 150 or 0: Two 8 MB memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR Model Type: Size: Four banks, 1 GB each, 800 MHz (00 MHz DDR) PCI-Express Interface Model 730 PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Model PCI Express Bus: Gen. 1, 2 or 3: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard XMC module, 2.91 in. x 5.87 in. 23

24 Model 740: 1-Channel 3.6 GHz or 2-Channel 1.8 GHz, 12-bit - XMC Model 740 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6. A high-speed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes a 3.6 GHz, 12-bit converter and four banks of memory. In addition supporting PCI Express Gen. 2 as a native interface, the Model 740 includes optional general purpose and gigabit serial connecrs for application-specific I/O. Converter The front end accepts analog HF or IF inputs on a pair of front panel SSMC connecrs with transformer coupling in a Texas Instruments ADC12D bit. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the 740 have a full scale input range of +2 dbm +4 dbm. A built-in AuSync feature supports synchronization across multiple modules. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. Features Ideal radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s One-channel mode with 3.6 GHz, 12-bit Two-channel mode with 1.8 GHz, 12-bit s 2 GB of Sync bus for multimodule synchronization PCI Express Gen. 2 interface x8 Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O Contact Pentek for availability of rugged and conduction-cooled versions Sample Clk TTL PPS/Gate/Sync TIMING BUS 3.6 GHz (1 Channel) Clock/Sync Bus or Gate In Reset In Clock / Sync / Gate / PPS 1.8 GHz (2 Channel) 12-Bit Ref Clk In Ref Clk Out Sync Bus In 32 Banks 1&2 Banks 3&4 In VIRTEX-6 LX130T, LX240T or SX315T Config FLASH 64 MB 8X x8 P15 XMC Gigabit Serial I/O (option 105) P XMC LVDS 40 GPIO (option 104) P14 PMC 24

25 Installed IP Modules Model 740: 1-Channel 3.6 GHz or 2-Channel 1.8 GHz, 12-bit - XMC The 740 facry-installed functions include an acquisition IP module. In addition, IP modules for memories, a controller for all data clocking and synchronization functions, a test signal generar and a interface complete the facry-installed functions and enable the 740 operate as a complete turnkey solution, without the need develop any IP. Acquisition IP Module The 740 features an Acquisition IP Module for easy capture and data moving. The IP module can receive data from the, or a test signal generar. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. In single-channel mode, all four banks are used sre the single-channel of input data. In dual-channel mode, memory banks 1 and 2 sre data from input channel 1 and memory banks 3 and 4 sre data from input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. from from VIRTEX-6 DATAFLOW DETAIL (Two channel mode shown) INPUT MULTIPLEXER TEST SIGNAL DATA PACKING & FLOW METADATA MEM DATA PACKING & FLOW METADATA ACQUISITION IP MODULE ACQUISITION IP MODULE LER LER INTEACE (supports user installed IP) Bank 1 Bank 2 8X 40 Gigabit Serial I/O GPIO Bank 3 Bank 4 25

26 Model 740: 1-Channel 3.6 GHz or 2-Channel 1.8 GHz, 12-bit - XMC Also Available Specifications Model Format x8 PCI Express U OpenVPX - Format U OpenVPX - Format AMC U cpci - Single Density U cpci - Single Density U cpci - Double Density Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz 3.6 GHz; dual-channel mode: 150 MHz 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dbm +4 dbm, programmable Sample Clock Sources: Front panel SSMC connecr Sync Bus: Multi-pin connecrs, bus includes gate, reset and in and out ref clock External Trigger Input Type: Front panel female SSMC connecr, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option -105: Installs the XMC P connecr configurable as one 8X or two gigabit serial links the : Four memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard XMC module, 2.91 in. x 5.87 in. 26

27 Model 741: 1-Channel 3.6 GHz or 2-Channel 1.8 GHz, 12-bit, w/ DDC- XMC The model 741 consists of a Model 740 as described previously, but with the addition of two wideband DDC IP Cores installed in the Virtex-6. These IP Cores are in addition the facry-installed IP Modules described in the Model 740. DDC IP Cores Within the is a powerful DDC IP core. The core supports a singlechannel mode, accepting data samples from the at the full 3.6 GHz rate. Additionally, a dual-channel mode supports the s 1.8 GHz two-channel operation. In dual-channel mode, each DDC has an independent 32-bit tuning frequency setting that ranges from DC ƒ s, where ƒ s is the sampling frequency. In single-channel mode, decimation can be programmed 8x, x or 32x. In dual-channel mode, both channels share the same decimation rate, programmable 4x, 8x or x. The decimating filter for each DDC accepts a unique set of user-supplied -bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*ƒ s /N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 db. Each DDC delivers a complex output stream consisting of -bit I + -bit Q samples at a rate of ƒ s /N. from from VIRTEX-6 DATAFLOW DETAIL *Two channel mode shown. Programmable decimation of 8, or 32 available in one channel mode. INPUT MULTIPLEXER TEST SIGNAL DDC *DEC: 4, 8 or POWER METER & THRESHOLD DETECT DDC CORE DATAPACKING & FLOW METADATA MEM DDC *DEC: 4, 8 or POWER METER & THRESHOLD DETECT DDC CORE DATAPACKING & FLOW METADATA LER ACQUISITION IP MODULE ACQUISITION IP MODULE LER INTEACE Bank 1 Bank 2 8X 40 GPIO Bank 3 Bank 4 27

28 Model 741: 1-Channel 3.6 GHz or 2-Channel 1.8 GHz, 12-bit,, w/ DDC- - XMC Also Available Specifications Model Format x8 PCI Express U OpenVPX - Format U OpenVPX - Format AMC U cpci - Single Density U cpci - Single Density U cpci - Double Density Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz 3.6 GHz; dualchannel mode: 150 MHz 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dbm +4 dbm, programmable Digital Downconverters Modes: One or two channels, programmable Supported Sample Rate: One-channel mode: 3.6 GHz, two-channel mode: 1.8 GHz Decimation Range: One-channel mode: 8x, x or 32x, two-channel mode: 4x, 8x, or x LO Tuning Freq. Resolution: 32 bits, 0 ƒ s LO SFDR: >120 db Phase Offset Resolution: 32 bits, degrees FIR Filter: User-programmable 18-bit coefficients Default Filter Set: 80% bandwidth, <0.3 db passband ripple, >100 db spband attenuation Sample Clock Sources: Front panel SSMC connecr Sync Bus: Multipin front panel connecr, includes gate, reset, and in and out ref clock External Trigger Input Type: Front panel female SSMC connecr, TTL Function: Programmable functions include trigger and gate Field Programmable Gate Array: Xilinx Virtex-6 XC6VSX315T-2 Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the : Four memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard XMC module, 2.91 in. x 5.87 in. 28

29 Model 71741: 1-Channel 3.6 GHz or 2-Channel 1.8 GHz, 12-bit, w/ DDC - XMC Model is a member of the Onyx family of high-performance XMC modules based on the Xilinx Virtex-7. A high-speed data converter with a programmable digital downconverter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution. It includes a 3.6 GHz, 12-bit converter and four banks of memory. In addition supporting PCI Express Gen. 3 as a native interface, Model includes an optional connection the Virtex-7 for cusm I/O. The model includes two wideband DDC IP cores facry-installed in the Virtex-7. Converter The front end accepts analog HF or IF inputs on a pair of front panel SSMC connecrs with transformer-coupling in a Texas Instruments ADC12D bit. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the have a full scale input range of +2 dbm +4 dbm. A built-in AuSync feature supports synchronization across multiple modules. The digital outputs are delivered in the Virtex-7 for signal processing, data capture or for routing other module resources. Features Ideal radar and software radio interface solution Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across One-channel mode with 3.6 GHz, 12-bit Two-channel mode with 1.8 GHz, 12-bit s Programmable one- or two- channel DDC (Digital Downconverter) 4 GB of µsync clock/sync bus for multimodule synchronization PCI Express (Gen. 1, 2 & 3) interface up x8 Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-7 for cusm I/O Contact Pentek for availability of rugged and conduction-cooled versions Sample Clk TTL PPS/Gate/Sync TIMING BUS 3.6 GHz (1 Channel) Clock/Sync Bus or Gate In Reset In Clock / Sync / Gate / PPS 1.8 GHz (2 Channel) 12-Bit Ref Clk In Ref Clk Out Sync Bus CONFIG FLASH Config Bus GATEXPRESS CONFIGURATION MANAGER Gen. 3 x8 Gen. 3 x8 P15 XMC In In VIRTEX-7 VX330T or VX690T Gigabit Serial I/O (option 105) P XMC LVDS 48 GPIO (option 104) P14 PMC

30 Model 71741: 1-Channel 3.6 GHz or 2-Channel 1.8 GHz, 12-bit, w/ DDC - XMC Installed IP Modules The facry-installed functions include an acquisition IP module and a programmable DDC (digital downconverter). In addition, IP modules for memories, a controller for all data clocking and synchronization functions, a test signal generar and a interface complete the facry-installed functions and enable the operate as a complete turnkey solution, without the need develop any IP. Acquisition IP Module The features an Acquisition IP Module for easy capture and data moving. The IP module can receive data from the, or a test signal generar. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. In single-channel mode, all four banks are used sre the single-channel of input data. In dual-channel mode, memory banks 1 and 2 sre data from input channel 1 and memory banks 3 and 4 sre data from input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. DDC IP Cores Within the is a powerful DDC IP core. The core supports a singlechannel mode, accepting data samples from the at the full 3.6 GHz rate. Additionally, a dual-channel mode supports the s 1.8 GHz two-channel operation. In dual-channel mode, each DDC has an independent 32-bit tuning frequency setting that ranges from DC ƒ s, where ƒ s is the sampling frequency. In single-channel mode, decimation can be programmed 8x, x VIRTEX-7 DATAFLOW DETAIL *Two channel mode shown. Programmable decimation of 8, or 32 available in one channel mode. LER DDC *DEC: 4, 8 or POWER METER & THRESHOLD DETECT DDC CORE DATAPACKING & FLOW METADATA ACQUISITION IP MODULE INTEACE from or 32x. In dual-channel mode, both channels share the same decimation rate, programmable 4x, 8x or x. The decimating filter for each DDC accepts a unique set of usersupplied -bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*ƒ s /N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 db. Each DDC delivers a complex output stream consisting of -bit I + -bit Q samples at a rate of ƒ s /N. from INPUT MULTIPLEXER MEM DDC *DEC: 4, 8 or POWER METER & THRESHOLD DETECT DDC CORE DATAPACKING & FLOW METADATA ACQUISITION IP MODULE (supports user installed IP) TEST SIGNAL LER Bank 1 Bank 2 8X Gigabit Serial I/O 48 GPIO Bank 3 Bank 4 30

31 Model 71741: 1-Channel 3.6 GHz or 2-Channel 1.8 GHz, 12-bit, w/ DDC - XMC Also Available Specifications Model Format x8 PCI Express U OpenVPX - Format U OpenVPX - Format AMC U cpci - Single Density U cpci - Single Density U cpci - Double Density Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz 3.6 GHz; dualchannel mode: 150 MHz 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dbm +4 dbm, programmable Digital Downconverters Modes: One or two channels, programmable Supported Sample Rate: One-channel mode: 3.6 GHz, two-channel mode: 1.8 GHz Decimation Range: One-channel mode: 8x, x or 32x, two-channel mode: 4x, 8x, or x LO Tuning Freq. Resolution: 32 bits, 0 ƒ s LO SFDR: >120 db Phase Offset Resolution: 32 bits, degrees FIR Filter: User-programmable 18-bit coefficients Default Filter Set: 80% bandwidth, <0.3 db passband ripple, >100 db spband attenuation Sample Clock Source: Front panel SSMC connecr Timing Bus: 19-pin µsync bus connecr includes sync and gate/trigger inputs, CML External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O Option -104: Installs the PMC P14 connecr with 24 LVDS pairs the Option -105: Installs the XMC P connecr configurable as one 8X or two gigabit serial links the Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard XMC module, 2.91 in. x 5.87 in. 31

32 Model 750: Transceiver with Two s, DUC, Two s - XMC Model 750 is a member of the Cobalt family of high performance XMC mod- -ules based on the Xilinx Virtex-6. A multichannel, high-speed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes two s, one DUC, two s, and four banks of memory. In addition supporting PCI Express Gen. 2 as a native interface, the Model 750 includes optional general-purpose and gigabit serial card connecrs for application-specific I/O. Features Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s Two 500 MHz 12-bit s One digital upconverter Two 800 MHz -bit s Up 2 GB of or 32 MB of Sample clock synchronization an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up x8 Optional user configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O Contact Pentek for availability of rugged and conduction-cooled versions Converter The front end accepts two full-scale analog HF or IF inputs on front panel SSMC connecrs at +5 dbm in 50 ohms with transformer coupling in two Texas Instruments ADS MHz, 12-bit converters. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. Sample Clk / Reference Clk In TTL PPS/Gate/Sync TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate Gate Sync / PPS Sync / PPS Timing Bus TIMING BUS Clock / Sync / Gate / PPS VCXO Clock/Sync Bus Clock/Sync Bus In 500 MHz 12-BIT option 150 option 155 In 500 MHz 12-BIT option 0 option 5 Banks 1&2 Banks 3&4 Digital Upconverter and s A TI DAC5688 DUC and accepts a baseband real or complex data stream from the which is optionally interpolated, upconverted and then delivered the two s. When operating as a DUC, it interpolates and translates real or complex baseband input signals any IF center frequency up 360 MHz. It delivers real or quadrature (I+Q) digital outputs the dual -bit converter. Analog output is through a pair of front panel SSMC connecrs. If translation is disabled, the DAC5688 acts as a dual interpolating -bit converter with output sampling rates up 800 MHz. In both modes the DAC5688 provides interpolation facrs of 2x, 4x and 8x. VIRTEX-6 LX130T, LX240T or SX315T Config FLASH 64 MB 8X x8 P15 XMC Out 800 MHz -BIT 32 Out 800 MHz -BIT DIGITAL UPCONVERTER Gigabit Serial I/O (option 105) P XMC LVDS 40 GPIO (option 104) P14 PMC 32

33 Model 750: Transceiver with Two s, DUC, Two s - XMC Installed IP Modules The 750 facry-installed functions include two acquisition and one waveform playback IP modules. In addition, IP modules for either or memories, a controller for all data clocking and synchronization functions, a test signal generar and a interface complete the facryinstalled functions and enable the 750 operate as a complete turnkey solution, without the need develop any IP. Acquisition IP Modules The 750 features two Acquisition IP Modules for easy capture and data moving. Each IP module can receive data from either of the two s, a test signal generar or from the Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. Bank 1 DATA PACKING & FLOW METADATA ACQUISITION IP MODULE 1 from Ch 1 from Ch 2 INPUT MULTIPLEXER Bank 2 DATA PACKING & FLOW METADATA ACQUISITION IP MODULE 2 Waveform Playback IP Module The Model 750 facry-installed functions include a sophisticated Waveform Playback IP module. A linked-list controller allows users easily play back waveforms sred in either on-board memory or off- board host memory the dual s. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. loopback TEST SIGNAL Bank 3 DATA UNPACKING & FLOW WAVEFORM PLAYBACK IP MODULE VIRTEX-6 DATAFLOW DETAIL INTEACE (supports user installed IP) Bank 1 Bank 2 Bank 3 Bank 4 8X 40 Gigabit Serial I/O GPIO 33

34 Model 750: Transceiver with Two s, DUC, Two s - XMC Also Available Specifications Model Format x8 PCI Express U OpenVPX - Format U OpenVPX - Format AMC U cpci - Single Density U cpci - Single Density U cpci - Double Density Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters (standard) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz 500 MHz Resolution: 12 bits Converters (option 014) Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz 400 MHz Resolution: 14 bits Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz, max. Output IF: DC 400 MHz, max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz, max. with interpolation Resolution: bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one clock and one clock Clock Synthesizer Clock Source: Selectable from onboard programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, independently for the clock and clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connecr LVPECL bus includes, clock/ sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/ PPS inputs External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option -105: Installs the XMC P connecr configurable as one 8X or two gigabit serial links the Option 150 or 0: Two 8 MB memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen.1 or Gen.2, x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard XMC module, 2.91 in. x 5.87 in. 34

35 Model 751: Transceiver with Two s, DDC, DUC, Two s - XMC The model 751 consists of a Model 750 as described previously, but with the addition of two powerful DDCs and a beamformer IP Cores installed in the Virtex-6. These IP Cores are in addition the facry-installed IP modules described in the Model 750. The decimating filter for each DDC accepts a unique set of usersupplied -bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*ƒ s /N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 db. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or-bit I + -bit Q samples at a rate of ƒ s /N. Beamformer IP Core In addition the DDCs, the 751 features a complete beamforming subsystem. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up 8K samples. The power meters present average power measurements for each DDC core output in easy--read registers. In addition, each DDC core includes a threshold detecr aumatically send an interrupt the processor if the average power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the two DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back in the Acquisition IP Module 1 FIFO for reading over the. For larger systems, multiple 751 s can be chained gether via a built-in Xilinx Aurora gigabit serial interface through the P XMC connecr. This allows summation across channels on multiple boards. DDC IP Cores Within each Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the Acquisition IP Modules, many different configurations can be achieved including one driving both DDCs or each of the two s driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges from DC ƒ s, where ƒ s is the sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as two different output bandwidths for the board. Decimations can be programmed from 2 131,072 providing a wide range satisfy most applications. AURORA GIGABIT SERIAL INTEACE next board Bank 1 sum out SUMMER sum in BEAMFORMER CORE from previous board from Ch 1 DDC DEC: 2TO POWER METER & THRESHOLD DETECT DDC CORE DATA PACKING & FLOW METADATA ACQUISITION IPMODULE 1 from Ch 2 INPUT MULTIPLEXER Bank 2 loopback DDC DEC: 2TO POWER METER & THRESHOLD DETECT DDC CORE DATA PACKING & FLOW METADATA ACQUISITION IPMODULE 2 VIRTEX-6 DATAFLOW DETAIL TEST SIGNAL Bank 4 INTEACE WAVEFORM PLAYBACK IP MODULE 8X INTERPOLATOR 2TO IP CORE DATA UNPACKING & FLOW 35

36 Model 751: Transceiver with Two s, DDC, DUC, Two s - XMC Also Available Specifications Model Format x8 PCI Express U OpenVPX - Format U OpenVPX - Format AMC U cpci - Single Density U cpci - Single Density U cpci - Double Density Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer: Coil Craft WBC4-6TLB Full Scale Input: +5 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters (standard) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz 500 MHz Resolution: 12 bits Converters (option -014) Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz 400 MHz Resolution: 14 bits Digital Downconverters Quantity: Two channels Decimation Range: 2x 131,072x in two programmable stages of 2x 256x and one fixed 2x stage LO Tuning Freq. Resolution: 32 bits, 0 ƒ s LO SFDR: >120 db Phase Offset Resolution: 32 bits, degrees FIR Filter: -bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 db passband ripple, >100 db spband attenuation Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: bits Digital Interpolar Interpolation Range: 2x 65,536x in two stages of 2x 256x Beamformer Summation: Two channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connecr using Aurora procol Phase Shift Coefficients: I & Q with -bit resolution Gain Coefficients: -bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Front Panel Analog Signal Outputs Output: Transformer-coupled, front panel female SSMC connecrs Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one clock and one clock Clock Synthesizer Clock Source: Selectable from onboard programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, independently for the clock and clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus: 26-pin connecr LVPECL bus includes, clock/sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/pps inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option -150: Two 8 MB memory banks, 400 MHz DDR Option -155 or -5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 2: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Standard XMC, 2.91 in. x 5.87 in. 36

37 Model 71751: Transceiver with Two s, DDC, DUC, Two s - XMC Model is a member of the Onyx family of high performance XMC modules based on the Xilinx Virtex-7. A multichannel, high-speed data converter with a programmable DDC, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes two s, two s and four banks of memory. In addition supporting PCI Express Gen. 3 as a native interface, the Model includes a general-purpose connecr for application-specific I/O. Features Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across Two 500 MHz 12-bit s Two multiband DDCs (digital downconverters) One DUC (digital upconverter) Two 800 MHz -bit s 4 GB of Sample clock synchronization an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1, 2 & 3) interface up x8 Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-7 for cusm I/O Optional 400 MHz 14-bit s Contact Pentek for availability of rugged and conduction-cooled versions Converters The front end accepts two full-scale analog HF or IF inputs on front panel SSMC connecrs at +5 dbm in 50 ohms with transformer-coupling in two Texas Instruments ADS MHz, 12-bit converters. Optionally, a Texas Instruments ADS MHz, 14-bit may be installed. The digital outputs are delivered in the Virtex-7 for signal processing, data capture or for routing other module resources. Sample Clk / Reference Clk In TTL PPS/Gate/Sync TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate Gate Sync / PPS Sync / PPS Timing Bus TIMING BUS Clock / Sync / Gate / PPS VCXO CONFIG FLASH Clock/Sync Bus Clock/Sync Bus Config Bus In 500 MHz 12-BIT GATEXPRESS CONFIGURATION MANAGER Gen. 3 x8 Gen. 3 x8 P15 XMC In 500 MHz 12-BIT Digital Upconverter and s A TI DAC5688 DUC and accepts a baseband real or complex data stream from the which is optionally interpolated, upconverted and then delivered the two s. When operating as a DUC, it interpolates and translates real or complex baseband input signals any IF center frequency up 360 MHz. It delivers real or quadrature (I+Q) digital outputs the dual -bit converter. Analog output is through a pair of front panel SSMC connecrs. If translation is disabled, the DAC5688 acts as a dual interpolating -bit converter with output sampling rates up 800 MHz. In both modes the DAC5688 provides interpolation facrs of 2x, 4x and 8x. An -based interpolar provides additional interpolation from 2x 65,536x. The two interpolars can be combined create a tal range from 2x 524,288x VIRTEX-7 VX330T or VX690T Gigabit Serial I/O (option 105) P XMC LVDS GPIO (option 104) P14 PMC Out 800 MHz 800 MHz -BIT -BIT DIGITAL UPCONVERTER 32 Out 37

38 Model 71751: Transceiver with Two s, DDC, DUC, Two s - XMC Installed IP Modules The facry-installed functions include two acquisition and a waveform playback IP modules. Each of the two acquisition IP modules contains a powerful, programmable DDC IP core. The waveform playback IP module contains an interpolation IP core, ideal for matching playback rates the data and decimation rates of the acquisition modules. IP modules for memories, a controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facryinstalled functions and enable the operate as a complete turnkey solution, without the need develop any IP. Acquisition IP Modules The features two Acquisition IP Modules for easily capturing and moving data. Each module can receive data from either of the two s, a test signal generar or from the Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. DDC IP Core Within each Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the Acquisition IP Modules, many different configurations can be achieved including one driving both DDCs or each of the two s driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges from DC ƒ s, where ƒ s is the sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as two different output bandwidths for the board. Decimations can be programmed from 2 131,072 providing a wide range satisfy most applications. The decimating filter for each DDC accepts a unique set of usersupplied -bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*ƒ s /N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 db. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or-bit I + -bit Q samples at a rate of ƒ s /N. Bank 1 from Ch 1 DDC DEC: 2TO POWER METER & THRESHOLD DETECT DDC CORE DATA PACKING & FLOW METADATA ACQUISITION IPMODULE 1 38 VIRTEX-7 DATAFLOW DETAIL Bank 1 Bank 2 Bank 3 Bank 4 from Ch 2 INPUT MULTIPLEXER Bank 2 Waveform Playback IP Module The Model facry-installed functions include a sophisticated Waveform Playback IP module. A linked-list controller allows users easily play back the dual s waveforms sred in either on-board memory or off- board host memory. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. loopback DDC DEC: 2TO POWER METER & THRESHOLD DETECT DDC CORE DATA PACKING & FLOW METADATA ACQUISITION IPMODULE 2 INTEACE Bank 4 TEST SIGNAL (supports user installed IP) 8X 48 Gigabit Serial I/O GPIO INTERPOLATOR 2TO IP CORE DATA UNPACKING & FLOW WAVEFORM PLAYBACK IP MODULE

39 Model 71751: Transceiver with Two s, DDC, DUC, Two s - XMC Also Available Specifications Model Format x8 PCI Express U OpenVPX - Format U OpenVPX - Format AMC U cpci - Single Density U cpci - Single Density U cpci - Double Density Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front-panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters (standard) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz 500 MHz Resolution: 12 bits Converters (optional) Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz 400 MHz Resolution: 14 bits Digital Downconverters Quantity: Two channels Decimation Range: 2x 131,072x in two programmable stages of 2x 256x and one fixed 2x stage LO Tuning Freq. Resolution: 32 bits, 0 ƒ s LO SFDR: >120 db Phase Offset Resolution: 32 bits, degrees FIR Filter: -bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 db passband ripple, >100 db spband attenuation Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: bits Digital Interpolar Interpolation Range: 2x 65,536x in two stages of 2x 256x Total Interpolation Range ( and Digital combined): 2x 524,288x Front Panel Analog Signal Outputs Output: Transformer-coupled, frontpanel female SSMC connecrs Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one clock and one clock Clock Synthesizer Clock Source: Selectable from onboard programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, independently for the clock and clock External Clock Type: Front-panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus: 26-pin connecr LVPECL bus includes, clock/sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/pps inputs Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O Option -104: Installs the PMC P14 connecr with 24 LVDS pairs the Option -105: Provides one 8X or two gigabit links between the and VPX P1 connecr support serial procols. Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. 39

40 Models 760 & 71760: 4-Channel 200 MHz - XMC Model 760 Model 760 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6. Model is a member of the Onyx family of high-performance modules based on the Virtex-7. These multichannel, high-speed data converters, are suitable for connection HF or IF ports of a communications or radar system. Their built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. Each model includes four s and four banks of memory. In addition supporting PCI Express as a native interface, these models include generalpurpose and gigabit serial connecrs for application-specific I/O. Model Features Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT or Virtex-7 VXT s Model 71720: GateXpress supports dynamic reconfiguration across Four 200 MHz -bit s Model 760: Up 2 GB of or 32 MB of ; Model 71760: 4 GB of Sample clock synchronization an external system reference LVPECL clock/sync bus for multimodule synchronization Model 760: PCI Express (Gen. 1 & 2) interface up x8; Model 71760: PCI Express (Gen. 1, 2, and 3) interface up x8 Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O Contact Pentek for availability of rugged and conduction-cooled versions Converters The front end accepts four full-scale analog HF or IF inputs on front panel SSMC connecrs at +8 dbm in 50 ohms with transformer coupling in four Texas Instruments ADS MHz, -bit converters. The digital outputs are delivered in the for signal processing, data capture or for routing other module resources. Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B Timing Bus TIMING BUS Clock / Sync / Gate / PPS VCXO CONFIG FLASH ONYX Only Clock/Sync Bus Config Bus P15 XMC 8X GATEXPRESS CONFIGURATION MANAGER CONFIG FLASH 64 MB COBALT Only In 200 MHz -BIT 8X P15 XMC COBALT: VIRTEX-6 LX130T, LX240T, or SX315T ONYX: VIRTEX-7 VX330T or V 690T LVDS In 200 MHz -BIT Option -105 Serial I/O P XMC 40 Cobalt 48 Onyx Option -104 GPIO P14 PMC In 200 MHz -BIT In 200 MHz -BIT Cobalt Configurations Onyx Configuration 40

41 Models 760 & 71760: 4-Channel 200 MHz - XMC Installed IP Modules The facry-installed functions in both models include four acquisition IP modules. IP modules for either or memories, a controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facryinstalled functions and enable these models operate as complete turnkey solutions without the need develop any IP. Acquisition IP Modules Both models feature four Acquisition IP modules for easily capturing and moving data. Each IP module can receive data from any of the four s or a test signal generar Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. from Ch 1 from Ch 2 from Ch 3 from Ch 4 TEST SIGNAL INPUT MULTIPLEXER DATA PACKING & FLOW DATA PACKING & FLOW DATA PACKING & FLOW DATA PACKING & FLOW Bank 1 METADATA Bank 2 METADATA Bank 3 METADATA Bank 4 METADATA ACQUISITION IP MODULE 1 ACQUISITION IP MODULE 2 ACQUISITION IP MODULE 3 ACQUISITION IP MODULE 4 VIRTEX-6/VIRTEX-7 DATAFLOW DETAIL INTEACE (supports user installed IP) Bank 1 Bank 2 Bank 3 Bank 4 8X Gigabit Serial I/O GPIO 40 Model Model

42 Models 760 & 71760: 4-Channel 200 MHz - XMC Also Available Specifications Model Format x8 PCI Express U OpenVPX - Format U OpenVPX - Format AMC U cpci - Single Density U cpci - Single Density U cpci - Double Density Model Format x8 PCI Express U OpenVPX - Format U OpenVPX - Format AMC U cpci - Single Density U cpci - Single Density U cpci - Double Density Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from onboard programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connecr; LVPECL bus includes, clock/sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Model 760 Xilinx Virtex-6 Standard: XC6VLX130T Optional: XC6VLX240T or XC6VSX315T Model Xilinx Virtex-7 Standard: XC7VX330T-2 Optional: XC7VX690T-2 Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs (Model 760) or 24 pairs (Model 71760) the Option -105: Installs the XMC P connecr configurable as one 8X or two gigabit serial links the Model 760 Option 150 or 0: Two 8 MB memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR Model Type: Size: Four banks, 1 GB each PCI-Express Interface Model 760 PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Model PCI Express Bus: Gen. 1, 2 or 3: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard XMC module, 2.91 in. x 5.87 in. 42

43 Model 761: 4-Channel 200 MHz with DDCs and Beamformer - XMC The model 761 consists of a Model 760 as described previously, but with the addition of four multiband DDCs, and one beamformer IP Cores installed in the Virtex-6. These IP Cores are in addition the facry-installed IP Modules described in the Model 760. DDC IP Cores Within each Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the Acquisition IP Modules, many different configurations can be achieved including one driving all four DDCs or each of the four s driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges from DC ƒ s, where ƒ s is the sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as three different output bandwidths for the board. Decimations can be programmed from 2 65,536 providing a wide range satisfy most applications. The decimating filter for each DDC accepts a unique set of usersupplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*ƒ s /N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 db. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or-bit I + -bit Q samples at a rate of ƒ s /N. Beamformer IP Core In addition the DDCs, the 761 features a complete beamforming subsystem. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up 8K samples. The power meters present average power measurements for each DDC core output in easy--read registers. In addition, each DDC core includes a threshold detecr aumatically send an interrupt the processor if the average power level of any DDC core falls below or exceeds a programmable threshold. TEST SIGNAL next board Bank 1 AURORA GIGABIT SERIAL INTEACE DDC DEC: 2TO POWER METER & THRESHOLD DETECT DATA PACKING & FLOW METADATA ACQUISITION IPMODULE 1 sum out SUMMER sum in BEAMFORMER CORE from previous board from Ch 1 DDC DEC: 2TO POWER METER & THRESHOLD DETECT DATA PACKING & FLOW ACQUISITION IPMODULE 2 from Ch 2 A programmable summation block provides summing of any of the four DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back in the Acquisition IP Module 1 FIFO for reading over the. For larger systems, multiple 761 s can be chained gether via a built-in Xilinx Aurora gigabit serial interface through the P XMC connecr. This allows summation across channels on multiple boards. INPUT MULTIPLEXER VIRTEX-6 DATAFLOW DETAIL from Ch 3 DDC DEC: 2TO POWER METER & THRESHOLD DETECT DATA PACKING & FLOW ACQUISITION IPMODULE 3 from Ch 4 DDC DEC: 2TO POWER METER & THRESHOLD DETECT DDC CORE DDC CORE DDC CORE DDC CORE DATA PACKING & FLOW METADATA METADATA METADATA Bank 2 Bank 3 Bank 4 ACQUISITION IPMODULE 4 INTEACE 8X 43

44 Model 761: 4-Channel 200 MHz with DDCs and Beamformer - XMC Also Available Specifications Model Format x8 PCI Express U OpenVPX - Format U OpenVPX - Format AMC U cpci - Single Density U cpci - Single Density U cpci - Double Density Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Digital Downconverters Quantity: Four channels Decimation Range: 2x 65,536x in two stages of 2x 256x LO Tuning Freq. Resolution: 32 bits, 0 ƒ s LO SFDR: >120 db Phase Offset Resolution: 32 bits, degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 db passband ripple, >100 db spband attenuation Beamformer Summation: Four channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connecr using Aurora procol Phase Shift Coefficients: I & Q with -bit resolution Gain Coefficients: -bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from onboard programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus: 26-pin connecr LVPECL bus includes, clock/sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option 150 or 0: Two 8 MB memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard XMC module, 2.91 in. x 5.87 in. 44

45 .... Model 762: 4-Channel 200 MHz with 32-Channel DDC - XMC The Model 762 consists of a Model 760 as described previously, but with the addition of four 8-Channel DDC IP Cores installed in the Virtex-6. These IP Cores are in addition the facry-installed IP Modules described in the Model 760. DDC IP Cores Within each Acquisition IP Module is a powerful 8-channel DDC bank. Because of the flexible input routing of the Acquisition IP Modules, many different configurations can be achieved including one driving all 32 DDC channels or each of the four s driving its own DDC bank. Each of the 32 channels has an independent 32-bit tuning frequency setting that ranges from DC ƒ s, where ƒ s is the sampling frequency. All of the 8 channels within a bank share a common decimation setting that can range from The decimation range is programmable in steps of 8 from 1024 and steps of 64 from The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*ƒ s /N, where N is the decimation setting. The rejection of adjacentband components within the 80% output bandwidth is better than 100 db. For example, with a sampling rate of 200 MHz, the available output bandwidths range from khz 10.0 MHz. Each 8-channel bank can have its own unique decimation setting supporting a different bandwidth associated with each of the four acquisition modules. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of ƒ s /N. Any number of channels can be enabled within each bank, selectable from 0 8. Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within a bank. from Ch 1 from Ch 2 from Ch 3 from Ch 4 TEST SIGNAL INPUT MULTIPLEXER Bank 1 DIGITAL DOWN- CONVERTER BANK 1: CH 1-8 DEC: TO 8192 DDC CORE DATA PACKING & FLOW METADATA ACQUISITION IP MODULE 1 DIGITAL DOWN- CONVERTER BANK 2: CH 9- DEC: TO 8192 DDC CORE DATA PACKING & FLOW METADATA METADATA METADATA Bank 2 Bank 3 Bank 4 ACQUISITION IP MODULE 2 DIGITAL DOWN- CONVERTER BANK 3: CH DEC: TO 8192 DDC CORE DATA PACKING & FLOW ACQUISITION IP MODULE 3 DIGITAL DOWN- CONVERTER BANK 4: CH DEC: TO 8192 DDC CORE DATA PACKING & FLOW ACQUISITION IP MODULE 4 VIRTEX-6 DATAFLOW DETAIL INTEACE (supports user installed IP) 32 Bank 1 32 Bank 2 32 Bank 3 32 Bank 4 8X Gigabit Serial I/O 40 GPIO 45

46 Model 762: 4-Channel 200 MHz with 32-Channel DDC - XMC Also Available Specifications Model Format x8 PCI Express U OpenVPX - Format U OpenVPX - Format AMC U cpci - Single Density U cpci - Single Density U cpci - Double Density Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Digital Downconverters Quantity: Four 8-channel banks, one per acquisition module Decimation Range: 1024 in steps of 8 and in steps of 64 LO Tuning Freq. Resolution: 32 bits, 0 ƒ s Phase Offset Resolution: 32 bits, degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, >100 db spband attenuation Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from onboard programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock, or PLL system reference Timing Bus: 26-pin connecr LVPECL bus includes, clock/sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option -105: Installs the XMC P connecr configurable as one 8X or two gigabit serial links the Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard XMC module, 2.91 in. x 5.87 in. 46

47 Model 763: GSM Channelizer with Quad - XMC Features Complete GSM channelizer with analog IF interface Four 180 MHz -bit s Two banks of 375 DDCs for upper GSM band Two banks of 175 DDCs for lower GSM band Sample clock synchronization an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express Gen. 2 x8 The Model 763 consists of a Model 760 as described previously, but with the addition of 1100 GSM channelizer cores installed in the Virtex-6. GSM Channelizers The 763 contains four powerful GSM channelizer cores, two with 375 DDCs and two with 175 DDCs. Flexible input routing allows the independent, nonblocking assignment of any converter serve as the input source for any of the four GSM channelizers. Before connection the 763, the GSM bands must first be separately downconverted an IF frequency centered at 45, 135, or 225 MHz using an external analog tuner. These IF signals are then digitized by the 763 s at 180 MS/sec in the first, second, or third Nyquist zones, respectively. Super Channel Engines All 1100 DDCs generate parallel, complex output sample streams. At a sample rate of MS/sec, this represents an aggregate output rate of GB/sec, exceeding the 4 GB/sec peak rate of Gen. 2 x8 interface. To mitigate this situation, every four DDC channels are frequency-mutliplexed in a single super channel. This results in a reduction of the aggregate traffic by a facr of GB/sec, which is now well within the capability of the Gen. 2 x8 interface. These IP Cores are in addition the facry-installed IP Modules described in the Model 760. Super Channel Packets and Headers Super channel packets are formed by appending enabled superchannel samples sequentially from each bank. Once complete, a unique superchannel packet header is inserted at the beginning of each packet for identification. The header contains a time stamp, a sequential packet count, the number of enabled superchannels, the DMA channel identifier, and other information. By inspecting the header, the remaining data payload samples can be identified and recovered by the host. PCI Express Interface The Model 763 includes an industrystandard interface fully compliant with PCI Express Gen. 2 bus specifications. Supporting links up x8, the interface includes four DMA controllers for efficient packet transfers from each of the four DDC banks system memory. The interface is also used as the programming interface for all status and control between the 763 and host. Ch A In Ch B In Ch C In Ch D In 180 MHz -BIT 180 MHz -BIT 180 MHz -BIT 180 MHz -BIT M U X M U X M U X GSM CHANNELIZER 375 CHANNELS GSM CHANNELIZER 375 CHANNELS GSM CHANNELIZER 175 CHANNELS SUPER CHANNEL ENGINE SUPER CHANNEL ENGINE SUPER CHANNEL ENGINE PACKET PACKET PACKET FIFO & FIFO & FIFO & GEN 2 x8 INTEACE x4 or x8 Sample / Ref Clock In M U X GSM CHANNELIZER 175 CHANNELS SUPER CHANNEL ENGINE PACKET FIFO & Clock / Sync Bus Gate / Trigger / Sync / PPS CLOCK, SYNC & TRIGGER 180 MHz VCXO 47

48 Model 763: GSM Channelizer with Quad - XMC Also Available Specifications Model Format x8 PCI Express U OpenVPX - Format U OpenVPX - Format AMC U cpci - Single Density U cpci - Single Density U cpci - Double Density Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front-panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from onboard 180 MHz VCXO, front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external 10 MHz system reference External Clock Type: Front panel female SSMC connecr, sine wave, dbm, 50 ohms, AC-coupled, accepts 180 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin front panel connecr; LVPECL bus includes, clock/sync/ gate/pps inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS GSM Channel Banks DDCs per bank: two banks of 175 DDCsand two banks of 375 DDCs Overall bandwidth per bank: 35 MHz & 75 MHz for 175- and 375-channel banks IF (Center) Freq: 45, 135 or 225 MHz DDC Channels Channel Spacing: 200 khz, fixed DDC Center Frequencies: IF Freq ± k * 200 khz, where k = 0 87, or DDC Channel Filter Characteristics < 0.1 db passband flatness across ±80 khz from center (0 khz BW) > 18 db attenuation at ±100 khz > 78 db attenuation at ±170 khz > 83 db attenuation at ±600 khz > 93 db attenuation at ±800 KHz > 96 db attenuation at > ±3 MHz DDC Output Rate ƒ s : Resampled 180 MHz*13/20 = MS/sec DDC Data Output Format: 24 bits I + 24 bits Q Super Channels Content: Four consecutive DDC channels are frequency-offset from each other and then summed gether Frequency Offsets for each DDC: First: -ƒ s /4 ( khz) Second: 0 Hz Third: +ƒ s /4 ( khz) Fourth: +ƒ s /2 ( khz) Superchannel Sample Rate: ƒ s Superchannel Output Format: 26 bits I + 26 bits Q Number of Superchannels per Bank: 175-Channel banks: 44; 375-Channel banks: 94 Field Programmable Gate Array: Xilinx Virtex-6 XC6VSX315T PCI Express Interface PCI Express Bus: Gen. 2 x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard XMC module, 2.91 in. x 5.87 in. 48

49 Model 770: 4-Channel 1.25 GHz with DUC - XMC Model 770 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6. This 4-channel, high-speed data converter is suitable for connection transmit HF or IF ports of a communications or radar system. Its built-in data playback features offer an ideal turnkey solution for demanding transmit applications. The 770 includes four s, four digital upconverters and four banks of memory. In addition supporting PCI Express Gen. 2 as a native interface, the Model 770 includes general purpose and gigabit serial connecrs for application-specific I/O. Features Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s Four 1.25 GHz -bit s Four digital upconverters Programmable output levels 250 MHz max. output bandwidth 2 GB of Sample clock synchronization an external system reference Dual-µSync clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up x8 Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O Contact Pentek for availability of rugged and conduction-cooled versions Sample Clk / Reference Clk In Trigger In Gate In Sync In Sync Bus A Gate In Sync In Sync Bus B TIMING BUS Clock / Sync / Gate / PPS VCXO Clock/Sync Bus A Clock/Sync Bus B Out 1.25 GHz -BIT DIGITAL UPCONVERTER Out 1.25 GHz -BIT DIGITAL UPCONVERTER Banks1&2 Banks 3&4 Digital Upconverter and Two Texas Instruments DAC3484s provide four DUC (Digital Upconverter) and channels. Each channel accepts a baseband real or complex data stream from the and provides that input the upconvert, interpolate and stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals a user selectable IF center frequency. It delivers real or quadrature (I+Q) analog outputs a -bit converter. If translation is disabled, each acts as an interpolating -bit with output sampling rates up 1.25 GHz. In both modes, the provides interpolation facrs of 2x, 4x, 8x and x. Transformer-coupled analog output is through four front panel SSMC connecrs. Config FLASH 64 MB Out 1.25 GHz -BIT DIGITAL UPCONVERTER VIRTEX-6 LX130T, LX240T or SX315T 8X x8 P15 XMC Out 1.25 GHz -BIT DIGITAL UPCONVERTER Gigabit Serial I/O (option 105) P XMC LVDS 40 GPIO (option 104) P14 PMC 49

50 Model 770: 4-Channel 1.25 GHz with DUC - XMC Installed IP Modules The 770 facry-installed functions include four waveform playback IP modules, support waveform generation through the converters. IP modules for memories, a controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facry-installed functions and enable the 770 operate as a complete turnkey solution, without the need develop any IP. Waveform Playback IP Module The Model 770 facry-installed functions include a sophisticated Waveform Playback IP module. Four linked list controllers support waveform generation the four s from tables sred in either on-board memory or off-board host memory. Data for Channel 1 and Channel 2 are interleaved for delivery a dual channel device. For this reason, they must share a common trigger/gate, sample rate, interpolation facr, and other parameters. The same rules apply Channel 3 and Channel 4. Parameters including length of waveform, waveform repetition, etc. can be programmed for each channel. Up 64 individual link entries for each channel can be chained gether create complex waveforms with a minimum of programming. Ch1&2 Ch3&4 TEST SIGNAL DATA INTERLEAVER DATA INTERLEAVER DATA UNPACKING & FLOW DATA UNPACKING & FLOW DATA UNPACKING & FLOW DATA UNPACKING & FLOW Bank 1 WAVEFORM PLAYBACK IP MODULE 1 Bank 2 WAVEFORM PLAYBACK IP MODULE 2 Bank 3 WAVEFORM PLAYBACK IP MODULE 3 Bank 4 WAVEFORM PLAYBACK IP MODULE 4 VIRTEX-6 DATAFLOW DETAIL INTEACE (supports user installed IP) Bank 1 Bank 2 Bank 3 Bank 4 8X 40 Gigabit Serial I/O GPIO 50

51 Model 770: 4-Channel 1.25 GHz with DUC - XMC Also Available Specifications Model Format x8 PCI Express U OpenVPX - Format U OpenVPX - Format AMC U cpci - Single Density U cpci - Single Density U cpci - Double Density Converters Type: TI DAC3484 Input Data Rate: MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or x Resolution: bits Front Panel Analog Signal Outputs Quantity: Four outputs Output Type: Transformer-coupled, front panel female SSMC connecrs Full Scale Output: Programmable from 20 dbm (0.063 Vp-p) +4 dbm (1.0 Vp-p) in steps Full Scale Output Programming: 1.0x(G+1)/ Vp-p, where 4-bit integer G = 0 15 Clock Synthesizer Clock Source: Selectable from onboard programmable VCXO or front panel external clock VCXO Frequency Ranges: MHz, MHz and MHz Synchronization: VCXO can be phase-locked an external MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz sample clock or 5 or 10 MHz system reference External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin µsync bus connecr includes, sync and gate/trigger inputs, CML Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option -105: Installs the XMC P connecr configurable as one 8X or two gigabit serial links the : Four memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 or x8; Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard XMC module, 2.91 in. x 5.87 in. 51

52 Model 771: 4-Channel 1.25 GHz with DUC, Extended Interpolation - XMC The model 771 consists of a Model 770 as described previously, but with the addition of four wide-range programmable interpolation IP Cores installed in the Virtex-6. Installed in each of the four channels, these IP Cores are in addition the facry-installed IP modules described in the Model 770. Interpolar IP Core In addition the DAC3484, the 771 features an -based interpolation engine which adds two addinal interpolation stages programmable from 2x 256x. The combined interpolation results in a range from 2x 1,048,576x for each channel and is ideal for matching the digital downconversion and data reduction used on the receiving channels of many communications systems. Ch1&2 Ch3&4 TEST SIGNAL DATA INTERLEAVER DATA INTERLEAVER INTERPOLATOR 2 TO IP CORE INTERPOLATOR 2 TO IP CORE INTERPOLATOR 2 TO IP CORE INTERPOLATOR 2 TO IP CORE DATA UNPACKING & FLOW DATA UNPACKING & FLOW DATA UNPACKING & FLOW DATA UNPACKING & FLOW Bank 1 WAVEFORM PLAYBACK IP MODULE 1 Bank 2 WAVEFORM PLAYBACK IP MODULE 2 Bank 3 WAVEFORM PLAYBACK IP MODULE 3 Bank 4 WAVEFORM PLAYBACK IP MODULE 4 VIRTEX-6 DATAFLOW DETAIL INTEACE (supports user installed IP) Bank 1 Bank 2 Bank 3 Bank 4 8X 40 Gigabit Serial I/O GPIO 52

53 Model 771: 4-Channel 1.25 GHz with DUC, Extended Interpolation - XMC Also Available Specifications Model Format x8 PCI Express U OpenVPX - Format U OpenVPX - Format AMC U cpci - Single Density U cpci - Single Density U cpci - Double Density Converters Type: TI DAC3484 Input Data Rate: MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or x Resolution: bits Digital Interpolar Interpolation Range: 2x 65,536x in two stages of 2x 256x Front Panel Analog Signal Outputs Quantity: Four outputs Output Type: Transformer-coupled, front panel female SSMC connecrs Full Scale Output: Programmable from 20 dbm (0.063 Vp-p) +4 dbm (1.0 Vp-p) in steps Full Scale Output Programming: 1.0x(G+1)/ Vp-p, where 4-bit integer G = 0 15 Clock Synthesizer Clock Source: Selectable from onboard programmable VCXO or front panel external clock VCXO Frequency Ranges: MHz, MHz and MHz Synchronization: VCXO can be phase-locked an external MHz system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz sample clock or 5 or 10 MHz system reference External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin µsync bus connecr includes, sync and gate/trigger inputs, CML Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T-2 Optional: Xilinx Virtex-6 XC6VSX315T-2 Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option -105: Installs the XMC P connecr configurable as one 8X or two gigabit serial links the : Four memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 or x8; Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard XMC module, 2.91 in. x 5.87 in. 53

54 Model 71771: 4-Channel 1.25 GHz with DUC, Extended Interpolation - XMC Model is a member of the Onyx family of high performance XMC modules based on the Xilinx Virtex-7. This 4-channel, high-speed data converter is suitable for connection transmit HF or IF ports of a communications or radar system. Its built-in data playback features offer an ideal turnkey solution for demanding transmit applications. It includes four s with a wide range of programmable interpolation facrs, four digital upconverters and four banks of memory. In addition supporting PCI Express Gen. 3 as a native interface, the Model includes optional general-purpose and gigabit serial connecrs for applicationspecific I/O. Features Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across Four 1.25 GHz -bit s Four digital upconverters Extended interpolation range from 2x 1,048,576x Programmable output levels 250 MHz max. output bandwidth 4 GB of Sample clock synchronization an external system reference Dual-µSync clock/sync bus for multimodule synchronization PCI Express (Gen. 1, 2 & 3) interface up x8 Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-7 for cusm I/O Contact Pentek for availability of rugged and conduction-cooled versions Digital Upconverter and Two Texas Instruments DAC3484s provide four DUC (digital upconverter) and channels. Each channel accepts a baseband real or complex data stream from the and provides that input the upconvert, interpolate and stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals a user selectable IF center frequency. It delivers Sample Clk / Reference Clk In Trigger In Gate In Sync In Sync Bus A Gate In Sync In Sync Bus B TIMING BUS Clock / Sync / Gate / PPS VCXO CONFIG FLASH Clock/Sync Bus A Clock/Sync Bus B Config Bus Out 1.25 GHz -BIT DIGITAL UPCONVERTER GATEXPRESS CONFIGURATION MANAGER Gen. 3 x8 Gen. 3 x8 P15 XMC real or quadrature (I+Q) analog outputs a -bit converter. If translation is disabled, each acts as an interpolating -bit with output sampling rates up 1.25 GHz. In both modes, the provides interpolation facrs of 2x, 4x, 8x and x. Transformer-coupled analog outputs are through four front panel SSMC connecrs. Out 1.25 GHz -BIT DIGITAL UPCONVERTER Out 1.25 GHz -BIT DIGITAL UPCONVERTER VIRTEX-7 VX330T or VX690T Gigabit Serial I/O (option 105) P XMC LVDS GPIO (option 104) P14 PMC Out 1.25 GHz -BIT DIGITAL UPCONVERTER

55 Model 71771: 4-Channel 1.25 GHz with DUC, Extended Interpolation - XMC Installed IP Modules The facry-installed functions include four waveform playback IP modules, support waveform generation through the converters. IP modules for an interpolation engine, memories, a controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facry-installed functions and enable the operate as a complete turnkey solution, without the need develop any IP. Waveform Playback IP Module The Model facry-installed functions include a sophisticated Waveform Playback IP module. Four linked list controllers support waveform generation the four s from tables sred in either on-board memory or off-board host memory. Data for Channel 1 and Channel 2 are interleaved for delivery a dual channel device. For this reason, they must share a common trigger/gate, sample rate, interpolation facr, and other parameters. The same rules apply Channel 3 and Channel 4. Parameters including length of waveform, waveform repetition, etc. can be programmed for each channel. Up 64 individual link entries for each channel can be chained gether create complex waveforms with a minimum of programming. TEST SIGNAL DATA INTERLEAVER Ch1&2 Interpolar IP Core In addition the DAC3484, the features an -based interpolation engine which adds two addinal interpolation stages programmable from 2x 256x. The combined interpolation results in a range from 2x 1,048,576x for each channel and is ideal for matching the digital downconversion and data reduction used on the receiving channels of many communications systems. DATA INTERLEAVER Ch3&4 INTERPOLATOR 2 TO IP CORE INTERPOLATOR 2 TO IP CORE INTERPOLATOR 2 TO IP CORE INTERPOLATOR 2 TO IP CORE DATA UNPACKING & FLOW DATA UNPACKING & FLOW DATA UNPACKING & FLOW DATA UNPACKING & FLOW Bank 1 WAVEFORM PLAYBACK IP MODULE 1 Bank 2 WAVEFORM PLAYBACK IP MODULE 2 Bank 3 WAVEFORM PLAYBACK IP MODULE 3 Bank 4 WAVEFORM PLAYBACK IP MODULE 4 VIRTEX-7 DATAFLOW DETAIL INTEACE (supports user installed IP) Bank 1 Bank 2 Bank 3 Bank 4 8X 48 Gigabit Serial I/O GPIO 55

56 Model 71771: 4-Channel 1.25 GHz with DUC, Extended Interpolation - XMC Also Available Specifications Model Format x8 PCI Express U OpenVPX - Format U OpenVPX - Format AMC U cpci - Single Density U cpci - Single Density U cpci - Double Density Converters Type: TI DAC3484 Input Data Rate: MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or x Resolution: bits Digital Interpolar Interpolation Range: 2x 65,536x in two stages of 2x 256x Front Panel Analog Signal Outputs Quantity: Four outputs Output Type: Transformer-coupled, front panel female SSMC connecrs Full Scale Output: Programmable from 20 dbm (0.063 Vp-p) +4 dbm (1.0 Vp-p) in steps Full Scale Output Programming: 1.0x(G+1)/ Vp-p, where 4-bit integer G = 0 15 Clock Synthesizer Clock Source: Selectable from onboard programmable VCXO, front panel external clock or µsync timing buses Synchronization: Clocks can be locked a front panel 5 or 10 MHz system reference External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz sample clock or 5 or 10 MHz system reference External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin µsync bus connecr includes, clock, reset and gate/ trigger inputs and outputs, CML Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX485T-2, or XC7VX690T-2 Cusm I/O Option -104: Installs the PMC P14 connecr with 24 LVDS pairs the Option -105: Installs the XMC P connecr configurable as one 8X or two gigabit serial links the Type: Size: Four banks, 1 GB each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard XMC module, 2.91 in. x 5.87 in. 56

57 Model 790: L-Band Tuner with 2-Channel 200 MHz - XMC Model 790 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6. A 2-Channel highspeed data converter, it is suitable for connection directly the port of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes an L-Band tuner, two s and four banks of memory. In addition supporting PCI Express Gen. 2 as a native interface, the Model 790 includes general purpose and gigabit serial connecrs for applicationspecific I/O. Features Accepts signals from 925 MHz 2175 MHz Programmable LNA boosts LNB (low-noise block) antenna signal levels with up 80 db gain Programmable analog downconverter provides I + Q baseband signals with bandwidths ranging from 4 40 MHz Two 200 MHz -bit s Supports Xilinx Virtex-6 LXT and SXT s 2 GB of or 32 MB of Sample clock synchronization an external system reference PCI Express (Gen. 1 & 2) interface, up x8 Clock/sync bus for multimodule synchronization Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O Contact Pentek for availability of rugged and conduction-cooled versions Tuner A front panel SSMC connecr accepts L-Band signals between 925 MHz and 2175 MHz from an antenna LNB (low noise block). A Maxim MAX2112 tuner directly converts these L-Band signals baseband using a broadband I/Q downconverter. The device includes an variablegain LNA (low noise amplifier), a PLL (phase- locked loop) synthesized local oscillar, quadrature (I + Q) downconverting mixers, baseband lowpass filters with programmable cuff frequency, and variable-gain baseband amplifiers. The fractional-n PLL synthesizer locks its VCO an on-board crystal, the timing generar output, or an Sample Clk / Reference Clk In Trigger 1 Trigger 2 TTL Gate / Trig TTL Sync / PPS Sample Clk Ref In Gate A Gate B Sync / PPS A Sync / PPS B Timing Bus TIMING Clock / Sync / Gate / PPS VCXO Ref Clock/Sync option 150 option 155 Ref In 200 MHz -BIT option 0 option 5 Banks 1&2 Banks 3&4 external reference input between 12 and 30 MHz. Together, the baseband amplifiers and the LNA offer a programmable-gain range of more than 80 db. An integrated lowpass filter with variable bandwidth provides bandwidths ranging from 4 40 MHz, programmable with 8 bits of resolution. Converters The analog baseband I and Q analog tuner outputs are then applied two Texas Instruments ADS MHz, -bit converters. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. I In MAX2112 Ref Out Q 200 MHz -BIT Config FLASH 64 MB GC VIRTEX-6 LX130T, LX240T or SX315T Control 8X x8 P15 XMC 12-BIT IC 2 2 Gigabit Serial I/O (option 105) P XMC LVDS 40 GPIO (option 104) P14 PMC 57

58 Model 790: L-Band Tuner with 2-Channel 200 MHz - XMC Installed IP Modules The 790 facry-installed functions include two acquisition IP modules. IP modules for either or memories, a controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facryinstalled functions and enable the 790 operate as a complete turnkey solution without the need develop any IP. Acquisition IP Modules The 790 features two Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from either of the two s or a test signal generar Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. from (I) from (Q) TEST SIGNAL INPUT MULTIPLEXER DATA PACKING & FLOW DATA PACKING & FLOW Bank 1 METADATA Bank 2 METADATA ACQUISITION IP MODULE 1 ACQUISITION IP MODULE 2 VIRTEX-6 DATAFLOW DETAIL INTEACE (supports user installed IP) Bank 1 Bank 2 Bank 3 Bank 4 8X 40 Gigabit Serial I/O GPIO 58

59 Model 790: L-Band Tuner with 2-Channel 200 MHz - XMC Also Available Specifications Model Format x8 PCI Express U OpenVPX - Format U OpenVPX - Format AMC U cpci - Single Density U cpci - Single Density U cpci - Double Density Front Panel Analog Signal Input Connecr: Front panel female SSMC Impedance: 50 ohms L-Band Tuner Type: Maxim MAX2112 Input Frequency Range: 925 MHz 2175 MHz Monolithic VCO Phase Noise: -97 dbc/hz at 10 khz Fractional-N PLL Synthesizer: freq VCO = (N.F) x freq REF where integer N = and fractional F is a 20-bit binary value PLL Reference (freq REF ): Front panel SSMC connecr or on-board 27 MHz crystal (Option -100), MHz LNA Gain: 0 65 db, controlled by a programmable 12-bit converter Baseband Amplifier Gain: 0 15 db, in 1 db steps Baseband Low Pass Filter: Cuff frequency programmable from 4 40 MHz with 8-bit resolution Dynamic Range: -75 dbm 0 dbm Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources: On-board timing generar/synthesizer Clock Synthesizer Clock Source: Selectable from onboard programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, for the clock Timing Generar External Clock Input Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Generar Bus: 26-pin front panel connecr LVPECL bus includes, clock/sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Input Quantity: 2 Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option -105: Installs the XMC P connecr configurable as one 8X or two gigabit serial links the Option 150 or 0: Two 8 MB memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard XMC module, 2.91 in. x 5.87 in. 59

60 Performance Graphs Performance: Models 720, 71720, 721, 760, 71760, 761, 71761, 762, Spurious Free Dynamic Range Spurious Pick-up f in = 70 MHz, f s = 200 MHz, Internal Clock Two-Tone SFDR f s = 200 MHz, Internal Clock Two-Tone SFDR f 1 = 30 MHz, f 2 = 70 MHz, f s = 200 MHz Adjacent Channel Crosstalk Crosstalk f 1 = 69 MHz, f 2 = 71 MHz, f s = 200 MHz Input Frequency Response f in Ch2 = 70 MHz, f s = 200 MHz, Ch 1 shown f s = 200 MHz, Internal Clock Performance: Models 720, 721, Spurious Free Dynamic Range Spurious Free Dynamic Range f out = 70 MHz, f s = 200 MHz, Internal Clock f out = 120 MHz, f s = 400 MHz, External Clock 60

61 THIS PAGE INTENTIONALLY LEFT BLANK 61

62 Model 710: LVDS Digital I/O with Virtex-6 - XMC Model 710 is a member of the Cobalt family of high-performance XMC modules based on the Xilinx Virtex-6. This digital I/O module provides 32 LVDS differential inputs or outputs plus LVDS clock, data valid, and data flow control on a front panel 80-pin connecr. Its built-in data capture and data generation feature offers an ideal turnkey solution as well as a platform for developing and deploying cusm -processing IP. In addition supporting PCI Express Gen. 1 as a native interface, the Model 710 includes a general-purpose connecr for application-specific I/O. Features 32 bits of LVDS digital I/O One LVDS clock One LVDS data valid One LVDS data suspend Supports LXT and SXT Virtex-6 S DMA controller moves data and from system memory Up 2 GB of PCI Express interface Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O the carrier board Contact Pentek for availability of rugged and conduction-cooled versions Acquisition IP Module The module can be configured for digital input mode by setting a jumper on the board. In this case, the module accepts input data Clock and input Data Valid signals. This supports a continuous input Clock with data accepted only when the Data Valid line is true. The module can optionally generate a Data Suspend output signal indicating that the 710 is no longer capable of accepting data. The module accepts 32 bits from the front panel connecr or from an on-board test signal generar Banks1& Pairs LVDS Data VIRTEX-6 LX130T, LX240T or SX315T 32 Banks3&4 Option 5 80-pin Front Panel Connecr LVDS Clock Config FLASH 64 MB Generation IP Module The module can be configured for digital output mode by setting a jumper on the board. In this case, the module generates output data Clock and output Data Valid signals. This supports a continuous output Clock with data valid only when the Data Valid line is true. The module can optionally accept a Data Suspend input signal halt data generation when the destination device is no longer capable of accepting data. A linked-list controller allows users generate 32-bit digital words out through the front panel LVDS connecr from tables sred in either on-board or off-board host memory. Data Valid LVDS 40 8X Optional GPIO Data Suspend x8 Optional Gigabit Serial I/O PMC P14 XMC P15 XMC P 62

63 Model 710: LVDS Digital I/O with Virtex-6 - XMC Also Available Model Format x8 PCI Express U OpenVPX - Format U OpenVPX - Format AMC U cpci - Single Density U cpci - Single Density U cpci - Double Density Installed IP Modules IP modules for memories, a controller for all data clocking, a test signal generar, and a interface complete the facry-installed functions and enable the 710 operate as a complete turnkey solution without the need develop any IP. XMC Interface The Model 710 complies with the VITA 42.0 XMC specification. Each of two connecrs provides multilane gigabit serial interfaces with up a 6 GHz bit clock. With dual XMC connecrs, the 710 supports x4 or x8 on the primary P15 XMC connecr. The secondary P XMC connecr is used for dual or single 8X userinstalled gigabit serial interfaces, such as Aurora,, and serial RapidIO. PCI Express Interface The Model 710 includes an industrystandard interface fully compliant with PCI Express Gen. 1 bus specifications. Supporting a x4 or x8 connection, the interface includes multiple DMA controllers for efficient transfers and from the module. y Resources The 710 hardware architecture supports up four independent memory banks of. The board is always configured with 1 GB of memory (Banks 1 and 2). In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. For cusmers who need more memory support their IP, Banks 3 and 4 can be optionally added for a tal of 2 GB of Specifications Front Panel Input/Output Data Lines: 35 LVDS differential pairs (32 pairs supported in facryinstalled functions), 2.5 V compliant Clock: One LVDS differential pair, 2.5 V compliant Data Valid: One LVDS differential pair, 2.5 V compliant Data Suspend: One LVDS differential pair, 2.5 V compliant Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option -105: Installs the XMC P connecr configurable as one 8X or two gigabit serial links the Standard: Two memory banks (1 and 2), 400 MHz DDR Option 5: Two memory banks (3 and 4), 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard XMC module, 2.91 in. x 5.87 in. 63

64 Model 711: Quad Serial FPDP Interface with Virtex-6 - XMC Model 711 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6. A multichannel, gigabit serial interface, it is ideal for interfacing serial FPDP data converter boards or as a chassis--chassis data link. The 711 is fully compatible with the VITA 17.1 Serial FPDP specification. Its built-in data transfer features make it a complete turnkey solution. For users who require application-specific functions, the 711 serves as a flexible platform for developing and deploying cusm processing IP. In addition supporting PCI Express as a native interface, the Model 711 includes a general-purpose connecr for application-specific I/O. Serial FPDP Interface The 711 is fully compatible with the VITA 17.1 Serial FPDP specification. With the capability support , 2.125, 2.5, 3.125, and 4.25 Gbaud link rates and the option for multimode and single-mode optical interfaces, the board can work in virtually any system. Programmable modes include: flow control in both receive and transmit directions, CRC support, and copy/loop modes. Features Complete serial FPDP solution Fully compliant with VITA 17.1 specification Up 2 GB of PCI Express interface up x8 LVDS connections the Virtex-6 for cusm I/O Contact Pentek for availability of rugged and conduction-cooled versions CH 1 CH 2 CH 3 CH 4 RX TX RX TX RX TX RX TX FIBER OPTIC or COPPER INTEACE FIBER OPTIC or COPPER INTEACE FIBER OPTIC or COPPER INTEACE VIRTEX-6 LX240T, SX315T or SX475T FIBER OPTIC or COPPER INTEACE LVDS Banks1&2 Banks3&4 option 155 option 5 Config FLASH 64 MB 8X x8 40 GPIO (option -104) P15 XMC P14 PMC 64

65 Model 711: Quad Serial FPDP Interface with Virtex-6 - XMC Also Available Model Format x8 PCI Express U OpenVPX - Format U OpenVPX - Format AMC U cpci - Single Density U cpci - Single Density U cpci - Double Density Installed IP Modules Four identical serial FPDP interfaces are installed in the. The interfaces are fully compatible with the VITA 17.1 serial FPDP specification. Each interface includes a serial FPDP TX and a serial FPDP RX engine. These are enhanced with DMA engines for efficient transfers and from the board. Specifications Front Panel Serial FPDP Inputs/Outputs Fiber Optic Connecr Type: LC Laser: 850 nm (standard, other options available) Copper Connecr Type: Micro Twinax Fiber Optic or Copper Link Rates: , 2.125, 2.5, or 4.25 Gbaud (copper rate depends on cable langth) Fiber Optic or Copper Data Transfer Rates: 105, 210, 247, 309 or 420 MB/sec (depending on link rate) per serial FPDP port Field Programmable Gate Array: Xilinx Virtex-6 XC6VLX240T, XC6VSX315T, or XC6VSX475T Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Std XMC module, 2.91 in. x 5.87 in. optional buffer SERIAL FPDP RX ENGINE CH 1 RX PACKET DECONSTRUCT OPTIONAL CRC CHECK 2K x 32 RX FIFO 32K x 32 FIFO CH 1 TX DISPARITY CALCULATE M U X SERIAL FPDP TX ENGINE OPTIONAL CRC 64 x 32 COPY MODE RX FIFO PACKET CONSTRUCT RATE BALANCE IDLE INSERT/DELETE 2K x 32 TX FIFO Copy mode data path K x 32 FIFO SERIAL FPDP CHANNEL 1 optional buffer INTEACE 8X RX CH 2 TX SERIAL FPDP CHANNEL 2 optional buffer RX CH 3 SERIAL FPDP CHANNEL 3 TX optional buffer RX CH 4 SERIAL FPDP CHANNEL 4 TX VIRTEX-6 DATAFLOW DETAIL 65

66 Complementary Products Model 7192: High-Speed Synchronizer and Distribution Board - PMC/XMC Features Synchronizes up four separate high-speed Cobalt or Onyx I/O modules Synchronizes sampling and data acquisition for multichannel systems Synchronizes gating and triggering functions Clock rates up 1.8 GHz Front panel MMCX connecrs for input signals Front panel µsync connecrs compatible with a range of Pentek Cobalt and Onyx modules The Model 7192 High-Speed Synchronizer and Distribution Board synchronizes multiple Pentek Cobalt or Onyx modules within a system. It enables synchronous sampling and timing for a wide range of multichannel high-speed data acquisition, DSP, and software radio applications. Up four modules can be synchronized using the 7192, with each receiving a common clock along with timing signals that can be used for synchronizing, triggering and gating functions. Input Signals Model 7192 provides three front panel MMCX connecrs accept input signals from external sources: one for clock, one for gate or trigger and one for a synchronization signal. Clock signals can be applied from an external source such as a high performance sine-wave generar. Gate/trigger and sync signals can come from an external system source. In addition the MMCX connecr, a reference clock can be accepted through the first front panel µsync output connecr, allowing a single Cobalt or Onyx board generate the clock for all subsequent boards in the system. Sample Clk / Reference Clk In PROGRAMMABLE VCXO Clk In Ref In PLL & DIVIDER :N :N Output Signals The 7192 provides four front panel µsync output connecrs, compatible with a range of high-speed Pentek Cobalt and Onyx modules. The µsync signals include a reference clock, gate/ trigger and sync signals and are distributed through matched cables, simplifying system design. Clock Signals The 7192 can accept a user supplied external clock on its front panel MMCX connecr. As an alternative the external clock, the 7192 can use its on-board VCXO (programmable voltage-controlled crystal oscillar) as the clock source. The VCXO can operate alone or be locked a system reference clock signal delivered the front panel reference clock input. The external or onboard clock can operate at full rate or be divided and used register all sync and gate/trigger signals as well as providing a reference clock all connected modules. In addition, the clock is available at the Clock Out MMCX as a sample or reference clock for other boards in the system. TWSI Clock / Calibration Out Sync 1 Reference Clk In * TWSI Control In Gate / Trigger Out Sync Out Reference Clk Out Sync 2 Gate / Trigger In Sync In Clk/ Ref In Trig/ Gate In Sync In BUFFER & PROGRAM DELAYS Sync 3 Sync 4 Gate / Trigger Out Sync Out Reference Clk Out Gate / Trigger Out Sync Out Reference Clk Out * For 740 calibration Gate / Trigger Out Sync Out Reference Clk Out 66

67 Complementary Products Model 7192: High-Speed Synchronizer and Distribution Board - PMC/XMC Also Available Model Format 7892 x8 PCI Express U OpenVPX - Format AMC U cpci - Single Density U cpci - Single Density U cpci - Double Density Gate and Synchronization Signals The 7192 features separate inputs for gate/trigger and sync signals. A programmable delay allows the user make timing adjustments on the gate/trigger and sync signals before they are sent buffers for output through the µsync output connecrs. Calibration The 7192 features a calibration output specifically designed work with the Models 740 or GHz modules and provide a signal reference for phase adjustment across multiple s. Programming The 7192 allows programming of operating parameters including: VCXO frequency, clock dividers, and delays that allow the user make timing adjustments on the gate and sync signals. These adjustments are made before they are sent buffers for output through the µsync connecrs. The 7192 is programmed via a TWSI control interface on the first µsync connecr. The control interface is compatible with the front panel µsync connecrs of all high-speed Cobalt and Onyx modules, thereby providing a single cable connection that carries both control and timing signals. Supported Products The 7192 supports all high-speed models in the Cobalt family including the GHz and XMC, the GHz XMC and the 770 Four-channel 1.25 GHz, -bit XMC. The 7192 will also support high-speed models in the Onyx family as they become available. Specifications Front Panel Sample Clock/Reference Input Connecr Type: MMCX Input Impedance: 50 ohms Input Level: 0 dbm +10 dbm, sine wave Sample Clock Frequency: 100 MHz 2 GHz Reference Frequency: MHz Front Panel Gate/Trigger & Sync Inputs Connecr Type: MMCX Input Level: LVTTL Front Panel µsync Inputs/Outputs Quantity: 4 Connecr Type: 19-pin µhdmi Signal Level: CML Signals (µsync connecr 1): Reference Clock In, TWSI control In, Reference Clock Out, Gate/Trigger Out, Sync Out Signals (µsync connecrs 2 4): Reference Clock Out, Gate/Trigger Out, Sync Out Front Panel Clock / Calibration Output Connecr Type: MMCX Output Impedance: 50 ohms Output Level: +6 dbm nominal, sine wave Sample Clock Frequency: 100 MHz 1.8 GHz Programmable VCXO: Frequency Ranges: MHz, MHz, and MHz Tuning Resolution: 32 bits Unlocked Accuracy: +20 ppm PLL, Divider & Jitter Cleaner Type: Texas Instruments CDCM7005 Frequency Dividers: 1, 2, 3, 4, 6, 8 and PMC/XMC Interface: Power only on PMC P1 or XMC P15 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard PMC module, 2.91 in. x 5.87 in. 67

68 Complementary Products Model 9192: Rackmount High-Speed System Synchronizer Unit Features Synchronizes up twelve separate high-speed Cobalt or Onyx I/O modules Synchronizes sampling and data acquisition for multichannel systems Synchronizes gating and triggering functions Clock rates up 1.8 GHz Rear panel SMA connecrs for input signals Rear panel µsync connecrs compatible with a range of Pentek Cobalt and Onyx modules The Model 9192 Rackmount High-Speed System Synchronizer Unit synchronizes multiple Pentek Cobalt or Onyx modules within a system. It enables synchronous sampling and timing for a wide range of multichannel high-speed data acquisition, DSP, and software radio applications. Up twelve boards can be synchronized using the 9192, with each receiving a common clock along with timing signals that can be used for synchronizing, triggering and gating functions. Input Signals Model 9192 provides four rear panel SMA connecrs accept input signals from external sources: two for clock, one for gate or trigger and one for a synchronization signal. Clock signals can be applied from an external source such as a high performance sine-wave generar. Gate/trigger and sync signals can come from an external system source. In addition the SMA connecr, a External Clk In reference clock can be accepted through the first rear panel µsync output connecr, allowing a single Cobalt or Onyx board generate the clock for all subsequent boards in the system. Output Signals The 9192 provides four rear panel µsync output connecrs, compatible with a range of high-speed Pentek Cobalt and Onyx boards. The µsync signals include a reference clock, gate/ trigger and sync signals and are distributed through matched cables, simplifying system design. Clock Signals The 9192 can accept a user supplied external clock on its rear panel SMA connecr. As an alternative the external clock, the 9192 can use its onboard VCXO (programmable voltage controlled crystal oscillar) as the clock source. The VCXO can operate Sample Clk / Reference Clk In USB USB-TO-TWSI INTEACE PROGRAMMABLE VCXO Clk In Ref In PLL & DIVIDER :N :N CLOCK SPLITTER TWSI Clock Out 1 Sync 1 Reference Clk In * TWSI Control In Gate / Trigger Out Sync Out Reference Clk Out Sync 2 Clock Out 2 Clock Out 3 through Clock Out 11 Clock Out 12 Gate / Trigger In Sync In Clk Ref In Trig/ Gate In Sync In BUFFER & PROGRAM DELAYS Gate / Trigger Out Sync Out Reference Clk Out Sync 3 through Sync 11 Sync 12 * For 740 calibration Gate / Trigger Out Sync Out Reference Clk Out 68

69 Complementary Products Model 9192: Rackmount High-Speed System Synchronizer Unit alone or be locked a system reference clock signal delivered the rear panel reference clock input. The on-board or external clock can operate at full rate or can be divided and used register all sync and gate/ trigger signals as well as providing a reference clock all connected boards. In addition, the clock is available at twelve Clock Out SMAs as a sample or reference clock for other boards in the system. Gate and Synchronization Signals The 9192 features separate inputs for gate/trigger and sync signals. A programmable delay allows the user make timing adjustments on the gate/trigger and sync signals before they are sent buffers for output through the µsync output connecrs. Calibration The 9192 features twelve calibration outputs specifically designed work with the 740 or GHz board and provide a signal reference for phase adjustment across multiple s. Programming The 9192 allows programming of operation parameters including: VCXO frequency, clock dividers, and delays that allow the user make timing adjustments on the gate and sync signals. These adjustments are made before they are sent buffers for output through the µsync connecrs. The 9192 is programmed via a rear panel USB connecr or a TWSI control interface on the first µsync connecr. The control interface is compatible with the front panel µsync connecrs of all high-speed Cobalt and Onyx modules, thereby providing a single cable connection that carries both control and timing signals. Supported Products The 9192 supports all high-speed models in the Cobalt family including the GHz and XMC, the GHz XMC and the 770 Four-channel 1.25 GHz, -bit XMC. The 9192 will also support high-speed models in the Onyx family as they become available. Specifications Front Panel Sample Clock/Reference Input Connecr Type: SMA Input Impedance: 50 ohms Input Level: 0 dbm +10 dbm, sine wave Sample Clock Frequency: 100 MHz 2 GHz Reference Frequency: MHz Rear Panel Gate/Trigger & Sync Inputs Connecr Type: SMA Input Level: LVTTL Rear Panel µsync Inputs/Outputs Quantity: 12 Connecr Type: 19-pin µhdmi Signal Level: CML Signals (µsync connecr 1): Reference Clock In, TWSI control In, Reference Clock Out, Gate/Trigger Out, Sync Out Signals (µsync connecrs 2-12): Reference Clock Out, Gate/Trigger Out, Sync Out Rear Panel Clock / Calibration Outputs Quantity: 12 Connecr Type: SMA Output Impedance: 50 ohms Output Level: +6 dbm nominal at 1400 MHz, sine wave Sample Clock Frequency: 100 MHz 1.8 GHz Programmable VCXO: Frequency Ranges: MHz, MHz, and MHz Tuning Resolution: 32 bits Unlocked Accuracy: +20 ppm PLL, Divider & Jitter Cleaner Type: Texas Instruments CDCM7005 Frequency Dividers: 1, 2, 3, 4, 6, 8 and Power: 120VAC Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard 1U Rack-mount, 19 in. x 1.75 in. 69

70 Complementary Products Model 7893: System Synchronizer and Distribution Board - Model 7893 System Synchronizer and Distribution Board synchronizes multiple Pentek Cobalt and Onyx boards within a system. It enables synchronous sampling, playback and timing for a wide range of multichannel high-speed data acquisition, DSP and software radio applications. Up eight boards can be synchronized using the 7893, each receiving a common clock up 800 MHz along with timing signals that can be used for synchronizing, triggering and gating functions. For larger systems, up eight 7893 s can be linked gether provide synchronization for up 64 Cobalt or Onyx boards. single Cobalt or Onyx board generate the timing and clock signals for the 7893 for distribution of up eight additional boards. This input can also be used link multiple 7893 s for larger systems. Output Signals The 7893 provides eight timing bus output connecrs for distributing all needed timing and clock signals the front panels of Cobalt and Onyx boards via ribbon cables. The 7893 locks the Gate/Trigger and Sync/PPS signals the system s sample clock. The 7893 also provides four front panel SMA connecrs for distributing sample clocks other boards in the system. Features Synchronizes up eight separate Cobalt or Onyx boards Up eight 7893s can be linked gether synchronize up 64 boards Synchronizes sampling, data acquisition and playback for multichannel systems Synchronizes gating and triggering functions Onboard programmable sample clock generar Output clock rates up 800 MHz Front panel SMA connecrs for TTL input signals and clock outputs Single-slot format Input Signals The Model 7893 provides four front panel SMA connecrs accept LVTTL input signals from external sources: two for Sync/PPS and one for Gate/Trigger. In addition the synchronization signals, a front panel SMA connecr accepts sample clocks up 800 MHz or, in an alternate mode, accepts a 10 MHz reference clock lock an onboard VCXO sample clock source. The 7893 also accepts the 26-pin Timing Bus connecr used on Cobalt and Onyx boards. This input allows a Sample Clk / Reference Clk In Sample Clk A Sample Clk B Gate / Trig A Gate / Trig B Sync / PPS A Sync / PPS B Timing Bus In USB USB INTEACE : N CLK IN PLL & : N : N : N DIVIDER : N REF CLK IN Control USB Gate / Trig USB Sync / PPS VOLTAGE PROGRAM VCXO Clock Signals The 7893 can accept a clock from either the front panel SMA connecr or from the timing bus input connecr. In addition, the board is equipped with a programmable onboard VCXO clock generar which can free run or be locked a user supplied, 10 MHz, typical, system reference. In all cases, the sample clock can be divided by 1, 2, 4, 8 or prior distribution the Clock Out SMAs or the timing bus output connecrs. Sample Clk A Sample Clk B Sample Clk A Sample Clk B Clock Out 1 Clock Out 2 Clock Out 3 Clock Out 4 Timing Bus Out 1 Sample Clk A Sample Clk B Gate / Trig A Gate / Trig B Sync / PPS A Sync / PPS B TTL Gate / Trig In USB Gate / Trig Gate / Trig A Gate / Trig B BUFFER & PROGRAM DELAYS Timing Bus Out 2 through Timing Bus Out 7 TTL Sync / PPS A In TTL Sync / PPS B In USB Sync / PPS Sync / PPS A Sync / PPS B Timing Bus Out 8 Sample Clk A Sample Clk B Gate / Trig A Gate / Trig B Sync / PPS A Sync / PPS B 70

71 Complementary Products Model 7893: System Synchronizer and Distribution Board - USB Interface The 7893 is programmed via a USB interface. In addition status and control, the USB interface can be used generate Gate/Trigger and Sync/PPS signals for distribution all connected boards. Physical Characteristics The 7893 is a single-slot size board which can be mounted in any PCI or slot. The board receives power from a standard six-pin power connecr and uses the PCI or slot solely for physical mounting, with no electrical connections. Supported Products The 7893 supports a wide range of products in the Cobalt family including the and three-channel, 200 MHz transceivers, the and two-channel, 500 MHz transceivers, the 78660, and four-channel 200 MHz s, and the L-Band Tuner. The 7893 also supports the Cobalt and the Onyx four-channel 200 MHz and will support all complementary models in the Onyx family as they become available. Specifications Sample Clock/Reference Clock Input Type: Front panel female SMC connecr Signal: Sine wave, dbm, AC-coupled, 50 ohms, accepts MHz sample clock or MHz PLL system reference, typically 10 MHz TTL Gate/Trigger Input Type: Front panel female SMC connecr Signal: LVTTL Function: Programmable functions include gate and trigger TTL Sync/PPS Input A Type: Front panel female SMC connecr Signal: LVTTL Function: Programmable functions include sync and PPS TTL Sync/PPS Input B Type: Front panel female SMC connecr Signal: LVTTL Function: Programmable functions include sync and PPS Timing Bus In Type: One rear 26-pin connecr Signals: LVPECL bus includes: Sample Clock A & B In, Gate/Trigger A & B In, and Sync/PPS A & B In Clock Synthesizer Clock Source: Selectable from onboard programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference (front panel Reference Clock Input), typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for each of five on-board clock buses. Sample Clock Output Type: Four front panel female SMC connecrs, each can be independently divided Output Level: +9 dbm, nominal, sine wave Timing Bus Out Type: Eight rear 26-pin connecrs Signals: LVPECL bus includes: Sample Clock A & B Out, Gate/Trigger A & B Out, and Sync/PPS A & B Out Control: Rear USB input for connecting motherboard on-board USB 8-pin header Power: Rear 8-pin connecr compatible with power connecrs Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Half-length card, 4.38 in. x 7.13 in. 71

72 Complementary Products Model 7194: High-Speed Clock Generar- - PMC/XMC Features Provides sample clock for up four separate XMC Cobalt or Onyx boards Locks user-supplied 10 MHz reference clock or on-board reference. OCXO provides an exceptionally precise clock The Model 7194 High-Speed Clock Generar provides fixed-frequency sample clocks Cobalt and Onyx modules in multiboard systems. It enables synchronous sampling, playback and timing for a wide range of multichannel high-speed data acquisition and software radio applications. Sample Clock Synthesizer The Model 7194 uses a high-precision, fixed-frequency, PLO (Phase-Locked Oscillar) generate an output sample clock. The PLO accepts a 10 MHz reference clock through a front panel SMA connecr. The PLO locks the output sample clock the incoming reference. A power splitter then receives the sample clock and distributes it four front panel SMA connecrs. The 7194 is available with sample clock frequencies from GHz. On-board Reference Clock In addition accepting a reference clock on the front panel, the 7194 includes an on-board 10 MHz reference clock. The reference is an OCXO (Oven- Controlled Crystal Oscillar), which provides an exceptionally precise frequency standard with excellent phase noise characteristics. Physical Characteristics The 7194 is a standard PMC/XMC module. The module does not require programming and the PMC P14 or XMC P15 connecr is used solely for power. The module can be optionally configured with a -style 6-pin power connecr allowing it be used in virtually any chassis or enclosure. Clock Out 1 Reference Clock In FREQUENCY SYNTHESIZER REFERENCE CLOCK IN SAMPLE CLOCK OUT frequency set by board option POWER SPLITTER Clock Out 2 Clock Out 3 Clock Out 4 OVEN STABlLIZED OSCILLATOR Reference Clock Out Contact Pentek for additional sample clock options 72

73 Complementary Products Model 7194: High-Speed Clock Generar- - PMC/XMC Also Available Model Format 7894 x8 PCI Express U OpenVPX - Format AMC U cpci - Single Density U cpci - Single Density U cpci - Double Density Specifications Sample Clock Frequency: Fixed, GHz by ordering option Sample Clock Outputs Type: Four front panel female SMA connecrs Output Level: +10 dbm, nominal, sine wave Reference Clock In Type: Front panel female SMA connecr Frequency: 10 MHz Input Impedance: 50 ohms Input Level: 0 dbm +10 dbm, sine wave Reference Clock Out Type: Front panel female SMA connecr Center Frequency: 10 MHz Output Impedance: 50 ohms Output Level: +10 dbm, nominal, sine wave Frequency Stability vs. Change in Temperature: 50.0 ppb Frequency Calibration: +1.0 ppm Aging Daily: +10 ppb/day First Year: +300 ppb Total Frequency Tolerance (20 years): ppm Phase Noise 1 Hz Offset: -67 dbc/hz 10 Hz Offset: -100 dbc/hz 100 Hz Offset: -130 dbc/hz 1 KHz Offset: -148 dbc/hz 10 KHz Offset: -154 dbc/hz 100 KHz Offset: -155 dbc/hz PMC/XMC Interface: Power only on PMC P1 or XMC P15 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: PMC module, 2.91 in. x 5.87 in. Sample Clock Phase Noise Phase Noise (1 Hz BW, typical) Phase Noise db/ref dbc/hz 73

74 Complementary Products Model 8266: PC Development System for Cobalt and Onyx Boards Features 4U 19-inch rackmount PC server chassis, 21-inch deep 64-bit Windows 7 Professional or Linux workstation Intel Core TM i7 3.6 GHz processor 8 GB ReadyFlow drivers and board support libraries installed Out-of-the-box test examples All I/O cables included General Information The Model 8266 is a fully-integrated PC development system for Pentek Cobalt and Onyx PCI Express software radio, data acquisition, and I/O boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. ReadyFlow Software Pentek ReadyFlow drivers and board support libraries are preinstalled and tested with the ReadyFlow includes example applications with full source code, a command line interface for cusm control over hardware, and Pentek s Signal Analyzer, a full-featured analysis ol that continuously displays live signals in both time and frequency domains. System Implementation Built on a professional 4U rackmount workstation, the 8266 is equipped with the latest Intel processor, and a high-performance motherboard. These features accelerate application code development and provide unhindered access the high-bandwidth data available with Cobalt and Onyx analog and digital interfaces. The 8266 can be configured with 64-bit Windows or Linux operating systems. The 8266 uses a 19 4U rackmount chassis that is 21 deep. Enhanced forced- air ventilation assures adequate cooling for Pentek Cobalt and Onyx boards. The chassis is designed draw cool air from the front and push warm air out the back. A 1000 W, 80+ Gold Power Supply guarantees more than enough power for additional boards. Configuration The 8266 supports up four Pentek Cobalt or Onyx boards. Please contact Pentek configure a system that requires additional slots for 3rdparty hardware. Specifications Operating System: 64-bit Windows 7 Professional or Linux Processor: Intel Core i7 processor Clock Speed: 3.6 GHz : 8 GB Dimensions: 4U Chassis, 19" W x 21" D x 7" H Weight: 35 lb, approx. Operating Temp: C Srage Temp: C Relative Humidity: 5 95%, non-cond. Power Requirements: VAC, Hz, 1000 W max. Options Options are available for high-end multicore CPUs and extended memory support applications that require additional horsepower. All necessary analog I/O cables are installed and tested, providing SMA connectivity for all analog I/O lines. * The Pentek Signal Analyzer is not supported on 64-bit Linux. 74

75 Cusmer Information Placing an Order When placing a purchase order for Pentek products, please provide the model number and product description. You may place your orders by letter, telephone, or fax; you should confirm a verbal order by mail, or fax. All orders should specify a purchase order number, bill- and ship- address, method of shipment, and a contact name and telephone number. U.S. orders should be made out Pentek, Inc. and may be placed directly at our office address, or c/o our authorized sales representative in your area. International orders may be placed with us, or with our authorized distribur in your country. They have pricing and availability information and they will be pleased assist you. Prices and Price Quotations All prices are F.O.B. facry in U.S. dollars. Shipping charges and applicable import, federal, state or local taxes, are paid by the purchaser. We re glad respond your request for price quotation just contact the corporate office, or your local representative. Price and delivery quotations are valid for 30 days, unless otherwise stated. Quantity discounts for large orders are available and will be included in our price quotation, if applicable. Terms Terms are Net 30 days for accounts with established credit; until credit is established, we require prepayment, or will ship C.O.D. Shipping For new orders, we normally ship UPS ground with shipping charges prepaid and added our invoice. If you are in a hurry, we will ship UPS Red, UPS Blue, FedEx, or the carrier of your choice, as you request. Order Cancellation and Returns All orders placed with Pentek are considered binding and are subject cancellation charges. Hardware products may be returned within 30 days after receipt, subject a rescking charge. Before returning a product, please call Cusmer Service obtain a Return Material Authorization (RMA) number. Software purchases are final and we cannot allow returns. Warranty Pentek warrants its products conform published specifications and be free from defects in materials and workmanship for a period of one year from the date of delivery, when used under normal operating conditions and within the service conditions for which they were furnished. The obligation of Pentek arising from a warranty claim shall be limited repairing or, optionally, replacing without charge any product which proves be defective within the term and scope of the warranty. Pentek must be notified of the defect or nonconformity within the warranty period. The affected product must be returned with shipping charges and insurance prepaid. Pentek will pay shipping charges for the return of product buyer, except for products returned from outside the USA. Limitations of Warranty This warranty does not apply products which have been repaired or altered by anyone other than Pentek or its authorized representatives. The warranty does not extend products that have been damaged by misuse, neglect, improper installation, unauthorized modification, or extreme environmental conditions, that fall outside of the scope of the product s environmental specifications. Due the normal, finite write-cycle limits of Solid State Drives (SSDs), Pentek shall not be liable for warranty coverage of SSDs caused by wear-related issues that arise as an SSD reaches its write-cycle limit. Pentek specifically disclaims merchantability or fitness for a particular purpose. Pentek shall not be held liable for incidental or consequential damages arising from the sale, use, or installation of any Pentek product. Regardless of circumstances, Pentek s liability under this warranty shall not exceed the purchase price of the product. Extended Warranty You may purchase an extended warranty on our board-level products for a fee of 1% of the list price per month of coverage, or 10% of the list price per year of coverage. All Pentek software products (excluding 3rd-party products) include free maintenance and free upgrades for one year. Extended software maintenance is available for one, two, and three years, starting after the first year. Service and Repair You must obtain a Return Material Authorization (RMA) before returning any product Pentek for service or repair. RMA requests must be submitted online at: Return Material Authorization Form After the form is completed in its entirety and submitted, Pentek shall you a receipt and start processing your request. Once your request has been approved, Pentek shall e- mail you an RMA number, shipping instructions, and a quotation if the product is out of warranty. Carefully package the product in its original packaging, if it is still available, and ship it Pentek prepaid (if within the US) or free domicile DDP (if outside the US). Pentek shall not be responsible for loss or damage in shipment Pentek, so you are strongly encouraged insure the shipment for its full replacement value. When the work is completed, we will return the product you along with a statement of work performed. Cusmer Service phone: fax: custsrvc@pentek.com Copyright 2011, 2012, 2013, 2014 Pentek, Inc. All rights reserved. Contents of this publication may not be reproduced without written permission. Specifications and prices are subject change without notice. Pentek, ReadyFlow, GateFlow, SystemFlow, Cobalt and Onyx are tradenmarks or registered trademarks of Pentek, Inc. Other trademarks are properties of their respective owners. Printed in U.S.A. Worldwide distribution and support T-Cobalt/Onyx

76 76