Cobalt/Onyx Selection Chart. A/D Converters D/A Converters Other Qty Rate Bits Qty Rate Bits Features MHz MHz 16

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2 Contents Xilinx Performance... 3 The Cobalt/Onyx Architecture... 4 Cobalt/Onyx Formats & Interfaces... 9 Support Software Models 720 & 71720: Transceiver with Three s, DUC, Two s Model 721: Transceiver with Three s, DDCs, DUC, Two s Model 730: 1 GHz, 1 GHz Model 740: 1-Channel 3.6 GHz or 2-Channel 1.8 GHz, 12-bit Model 750: Transceiver with Two s, DUC, Two s Model 751: Transceiver with Two s, DDC, DUC, Two s Models 760 & 71760: 4-Channel 200 MHz Model 761: 4-Channel 200 MHz with DDCs and Beamformer Model 762: 4-Channel 200 MHz with 32-Channel DDC Model 770: 4-Channel 1.25 GHz with DUC Model 771: 4-Channel 1.25 GHz with DUC, Extended Interpolation Model 790: L-Band Tuner with 2-Channel 200 MHz Performance Graphs Model 711: Quad Serial FPDP Interface Model 7192: High-Speed Synchronizer and Distribution Board - PMC/ Model 9192: Rack-mount High-Speed System Synchronizer Unit Model 7893: System Synchronizer and Distribution Board Coming Soon! Cusmer Information Converters Converters Other Qty Rate Bits Qty Rate Bits Features MHz MHz MHz MHz 3 DDCs, Sum, Int MHz MHz 4 DDCs, Sum MHz 32 DDCs, Sum MHz L-Band Tuner MHz MHz MHz MHz 2 DDCs, Int MHz MHz MHz MHz 2 DDCs, Int GHz GHz GHz GHz 12 Cobalt/Onyx Selection Chart GHz GHz Extended Int 711 Quad sfpdp Rate = Maximum Sampling Frequency DDC = Digital Downconverter Int = Interpolation Filter sfpdp = Serial FPDP VITA 17.1 Sum = Beamforming Summation Block & Aurora Chaining Interface 2

3 Xilinx Performance The Latest e Generations r i of f Virtex t e s A With each new generation of devices, Xilinx continues push the performance envelope match the ever increasing requirements of target applications. The announcement of the Virtex-6 and Virtex-7 were no exception. More processing power, lower power consumption, and updated interface features match the latest technology I/O requirements, are all part of these new devices. While it might be easy assume that faster, bigger, more powerful is better, it s important understand how the latest innovations actually deliver this higher performance best match the device the specific requirements of the application. One of the standard metrics for s is the number of logic cells. This figure shows the steady improvement in the last four generations of Xilinx s starting with the Virtex-4 and continuing the Virtex-7. The graph displays the number of logic cells contained in a range of different density devices offered in a 35 mm x 35 mm BGA (Ball-Grid Array) package. This clearly shows the dramatic increase in resource density, bounded by the constraints of the size and power dissipation capacity of a given package. Since Virtex-4 CLBs (Configurable Logic Blocks) comprise eight logic cells, while Virtex-5 and Virtex-6 CLBs comprise 12, the increase in logic cells between Virtex-4 and Virtex-5 actually translates a decrease in CLBs because each CLB in the Virtex-5 requires more logic cells. While the Virtex-5 CLBs are more powerful than their Virtex-4 counterparts, there are still fewer of them use. What is also clear this graph is that the Virtex-6 represents a significant increase in density the Virtex-5 family. The Virtex-7 offers the highest performance thus far with twice the performance and twice the resources of the Virtex-6. The Virtex-7 devices feature lowpower 28 nm process technology implement up 3.1 Tbits/sec of I/O and up 2 million logic cells. They provide up 6.7 TMACs of DSP resources, especially important for software radio applications. Because of new process technologies and other power management schemes, they consume half the power of Virtex-6 for a given function. This combination of lower power and higher performance for each of the key resources benefits software radio, opens up new product markets, and extends the capabilities of existing applications. Logic Cells In Thousands T T 485T 550T 585T T LX195T LX130T LX240T SX315T LX356T SX475T LX40 LX/SX50T FX70T LX85T SX95T LX/FX110T LX155T Virtex-7 SX55 LX0 LX/FX60 Virtex-6 LX80 LXFX100 Virtex-5 Smaller Devices Larger Devices Virtex-4 Logic Cell Density Comparison, Virtex-4, Virtex-5, Virtex-6, and Virtex-7 s Used in Pentek Products 3

4 The Cobalt & Onyx Architecture Features s and n Implementation I me e tio Cobalt b l & Onyx n x Architectural h r ra FeaturesF t r Cobalt : Xilinx Virtex-6 Onyx TM : Xilinx Virtex-7 Configurable memory resources depending on model On-board clocking and synchronization Modular I/O design support a wide range of signal types I/O I Module o l e The I/O module is a separate printedcircuit board that caries all of the analog interface circuitry providing excellent isolation noise. Typical front panel signals include analog in and out, clocking, sync, and triggering. Cobalt l & Onyx n Performance P o n Features sampling rates 10 MHz 3 GHz sampling rates up 1.25 GHz Powerful linked-list DMA engines PCI Express as the primary control and data transfer interface Secondary serial gigabit interface All models available in, PCI Express, OpenVPX and CompactPCI formats Available in commercial and in several ruggedization levels up and including conduction cooling or ry Resources These two smaller boards are used for the memory resources allowing for cusmization of two types of memory depending on model. Main Board The main board serves as the foundation of all Cobalt and Onyx products. It houses the, memory, interfaces, user programmable interfaces and hosts the memory and I/O modules. Flexible b l Architectureh e u re The modularity of this assembly offers an unprecedented degree of flexibility for creating Cobalt or Onyx modules with completely different features by just incorporating different I/O modules. As shown in the diagram, the front panel allows for a maximum of six SSMC signal connecrs. The external clocking, trigger and synchronization connecr is a front-panel multipin flat cable connecr and is the same on all models, except those designed operate at frequencies higher than 1.0 GHz. 4

5 The Cobalt & Onyx Architecture Components o s and Circuitry c it Cobalt o or r Onyx I/O I Module o u l Shown here is a typical Cobalt or Onyx I/O module. The input analog ports are transformer-coupled two high-speed converters. The digital outputs are delivered in the Virtex-6 or Virtex-7 for signal processing, data capture or for routing other module resources. Besides the two s, the typical module could include one DUC (Digital Upconverter), and two s which are transformer-coupled the output analog ports. In addition the input and output ports, the module includes a multiport connecr for clocking and synchronization. All connecrs are on the front panel. TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate Gate Sync / PPS Sync / PPS Timing Bus VCXO Sample Clk / Reference Clk In TIMING BUS Clock / Sync /Gate / PPS CONFIG ONYX Only Clock/Sync Bus Clock/Sync Bus Config Bus 8X GATEXPRESS CONFIGURATION MANAGER P15 In CONFIG 64 MB COBALT Only In COBALT: VIRTEX-6 LX130T, LX240T, LX365T, SX315T or SX475T 8X P15 ONYX: VIRTEX-7 VX330T, VX485T or V 690T LVDS Option -105 Serial I/O P 40 Cobalt 48 Onyx Option -104 P14 PMC QDRII+ QDRII+ Out DIGITAL UPCONVERTER QDRII+ Cobalt Configurations Out QDRII+ Xilinx i Virtex-6 e o or Virtex-7 i 7 The Cobalt Virtex-6 can be populated with a variety of different s match the specific requirements of the processing task. Supported s include: LX130T, LX240T, LX365T, SX315T, or SX475T. Likewise, the Onyx Virtex-7 can be populated with a variety of s match the specific requirements of the processing task. Supported s include: VX330T, VX485T, or VX690T. The SXT parts feature up 20 DSP48E slices, while the VX690T features 3600 DSP48E1 slices. These devices are ideal for modulation/ demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. Onyx Configuration r Cobalt: The -bit wide 64 MB provides non-volatile memory for facry boot code, self-test, and user parameters Onyx: The -bit wide 1024 MB provides non-volatile memory for facry boot code, self-test, user parameters, and images for dynamically reconfiguring the. or e o y Resourcess o e Cobalt: Up four independent memory banks can be configured with all QDRII+,, or as combination of two banks of each memory type. Each QDRII+ bank can be up 8 MB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, banks can each be up deep. 5 Onyx: Four independent memory banks are available. Each bank is 1 GB deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include an data transient capture mode and waveform playback mode. In addition the facry-installed functions, cusm user-installed IP within the can take advantage of the memories for many other purposes. More on next page

6 The Cobalt & Onyx Architecture Components and Circuitry Clocking and Synchronization The internal timing buses provide either a single clock or two different clock rates the and signal paths. The timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generar receives an external sample clock which can be used directly for either the or sections or can be divided by a built-in clock synthesizer circuit provide different and clocks. In an alternate mode, the sample clock can be sourced an onboard programmable VCXO (Voltage-Controlled Crystal Oscillar). In this mode, the synthesizer locks the VCXO an external system reference, typically 10 MHz. A front panel 26-pin LVPECL Clock/ Sync connecr allows multiple boards be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate Gate Sync / PPS Sync / PPS Timing Bus Sample Clk / Reference Clk In Clock/Sync Bus Clock/Sync Bus In In Out DIGITAL UPCONVERTER Out VCXO TIMING BUS Clock / Sync /Gate / PPS COBALT: VIRTEX-6 LX130T, LX240T, LX365T, SX315T or SX475T ONYX: VIRTEX-7 VX330T, VX485T or V 690T LVDS CONFIG ONYX Only Config Bus 8X GATEXPRESS CONFIGURATION MANAGER P15 CONFIG 64 MB COBALT Only 8X P15 Option -105 Serial I/O P 40 Cobalt 48 Onyx Option -104 P14 PMC QDRII+ QDRII+ QDRII+ Cobalt Configurations QDRII+ Onyx Configuration Available only in the Onyx series, the GateXpress TM is a sophisticated configuration manager for loading and reloading the. At powerup, GateXpress presents a target for the host computer discover, effectively giving the time load. This is especially important for larger s where the loading times can exceed the discovery window. The board s configuration can hold up four images for dynamically reconfiguring the. Board Interfaces The is also used implement the primary board interfaces. The basic module shown here is also available in different formats, such as PCI Express, OpenVPX, and CompactPCI. More information about formats and interfaces starts on page 9. 6

7 The Cobalt & Onyx Architecture TTL Gate / Trig TTL Sync / PPS Sample C k Reset Gate Gate Sync / PPS Sync / PPS Timing Bus Sample Clk / Reference Clk In Clock/Sync Bus Clock/Sync Bus In In Out DIGITAL UPCONVERTER Out VCXO TIMING BUS Clock / Sync /Gate / PPS ONYX: VIRTEX-7 VX330T, VX485T or V 690T LVDS CONFIG ONYX Only Config Bus 8X GATEXPRESS CONFIGURATION MANAGER P15 Option -105 Serial I/O P 40 Cobalt 48 Onyx Option -104 P14 PMC GateXpress a r ess for f Configuration i a o The Onyx architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on most PCs. The board s configuration can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the via JTAG using Xilinx impact or through the board s interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first is the option load an alternate image through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred on the host computer and loaded through as needed. The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. 7

8 The Cobalt & Onyx Architecture A Dataflow af All of the board s data and control paths are accessible by the, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering, and memory control. The Cobalt & Onyx Architecture organizes the as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt/Onyx family is delivered with facry-installed applications ideally matched the board s analog interfaces. Depending on model, the facry-installed functions may include acquisition and waveform playback IP modules. IP modules for either or QDRII+ (Cobalt only) memories, a controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facryinstalled functions and enable the board operate as a complete turnkey solution without the need develop any IP. For applications that require specialized functions, users can install cusm IP for data processing. Pentek GateFlow Design Kits (described later in this catalog) include all of the facry installed modules as documented source code. Developers can integrate their IP with the Pentek facry-installed functions or use the GateFlow completely replace the Pentek IP with theirs. Acquisition q n IP Modules o u This typical Cobalt/Onyx module includes two Acquisition IP modules for easy capture and data moving. Each IP module can receive data either of the two s, a test signal generar or the Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. Bank 1 PACKING & FLOW META IP MODULE 1 Ch 1 Ch 2 INPUT MULTIPLEXER Bank 2 PACKING & FLOW META IP MODULE 2 Wa aveform o Playback l y c k IP Module e Facry-installed functions for this typical Cobalt/Onyx module include a sophisticated Waveform Playback IP module. A linked-list controller allows users easily play back waveforms sred in either on-board memory or off- board host memory the dual s. Parameters including length of waveform, delay playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. loopback TEST SIGNAL Bank 3 UNPACKING & FLOW WAVEFORM PLAYBACK IP MODULE VIRTEX-6/VIRTEX-7 FLOW DETAIL INTEACE (supports user installed IP) Bank 1 Bank 2 Bank 3 Bank 4 8X 40 Gigabit Serial I/O 8

9 Cobalt & Onyx Formats & Interfaces C Format Here is a phograph of the typical board reviewed in detail in the previous section. In its configuration, each Cobalt or Onyx module complies with the VITA 42.0 specification and is suitable for mounting on motherboards with PMC/ connecrs. All modules are available in commercial and in several ruggedization levels up and including conduction cooling. TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate Gate Sync / PPS Sync / PPS Timing Bus Sample Clk / Reference Clk In Clock/Sync Bus Clock/Sync Bus In In Out DIGITAL UPCONVERTER Out VCXO TIMING BUS Clock / Sync /Gate / PPS COBALT: VIRTEX-6 LX130T, LX240T, LX365T, SX315T or SX475T ONYX: VIRTEX-7 VX330T, VX485T or V 690T LVDS CONFIG ONYX Only Config Bus 8X GATEXPRESS CONFIGURATION MANAGER P15 CONFIG 64 MB COBALT Only 8X P15 Option -105 Serial I/O P 40 Cobalt 48 Onyx Option -104 P14 PMC QDRII+ QDRII+ QDRII+ Cobalt Configurations QDRII+ Onyx Configuration PCI Express r s Interfacee ce The Cobalt includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Gen. 2 provides 4 GB/sec peak data transfer rate. The Onyx includes an industrystandard interface fully compliant with PCI Express Gen. 1, 2 & 3 bus specifications. Gen. 3 provides 8 GB/sec peak transfer rate. The interface includes multiple DMA controllers for efficient transfers and the module. Interfacen a Both Cobalt and Onyx products comply with the VITA 42.0 specification. Each of the two connecrs provides dual links or a single 8X link. With dual connecrs, the products support both x4 and x8 on the first connecr leaving the second connecr free support userinstalled transfer procols specific the target application. Optional l Interfacese ace Option -104 installs the P14 PMC connecr with 20 pairs of LVDS connections (Cobalt) or 24 pairs (Onyx) the for cusm I/O. Option -105 installs the P connecr with a single 8X or dual gigabit links the support serial procols. 9

10 Cobalt & Onyx Formats & Interfaces PCI I Express s s Format The PCI Express format shown here is suitable for mounting in PCs with connecrs and interfaces. Physically, the module reviewed in the previous page is mounted on a PCI Express carrier board with x8 motherboard connecrs. Other connecrs on this board provide additional interfaces as described below. The unique design of the carrier includes an integrated fan that keeps the module cool even in demanding situations while still requiring a single slot. TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate Gate Sync / PPS Sync / PPS Timing Bus Sample Clk / Reference Clk In Clock/Sync Bus Clock/Sync Bus In In Out DIGITAL UPCONVERTER Out VCXO TIMING BUS Clock / Sync /Gate / PPS COBALT: VIRTEX-6 LX130T, LX240T, LX365T, SX315T or SX475T ONYX: VIRTEX-7 VX330T, VX485T or V 690T LVDS CONFIG Config Bus 8X GATEXPRESS CONFIGURATION MANAGER CONFIG 64 MB 8X Option -105 Serial I/O 40 Cobalt 48 Onyx Option -104 QDRII QDRII QDRII Cobalt Configurations QDRII ONYX Only COBALT Only Dual Serial Conn 68-pin Header x8 PCI Express x8 PCI Express Onyx Configuration PCI Express r s Interfacee ce The Cobalt board includes an industry-standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Gen. 2 provides 4 GB/sec peak data transfer rate. The Onyx board includes an industry-standard interface fully compliant with PCI Express Gen. 1, 2 & 3 bus specifications. Gen. 3 provides 8 GB/sec peak transfer rate. The interface includes multiple DMA controllers for efficient transfers and the module. Optional l Interfacese ce Option -104 connects 20 pairs of LVDS connections (Cobalt) or 24 pairs (Onyx) the on PMC P14 a 68-pin DIL ribbon-cable header on the board for cusm I/O. Option -105 connects two gigabit serial links the on P two gigabit serial connecrs along the p edge of the board. 10

11 Cobalt & Onyx Formats & Interfaces 3U 3 OpenVPX Formatr at The OpenVPX format is compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPX TM System Specification) Shown here is the 3U OpenVPX COTS version (left) and the rugged version which is available in several ruggedization levels up and including conduction cooling. TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate Gate Sync / PPS Sync / PPS Timing Bus Sample Clk / Reference C k In Clock/Sync Bus Clock/Sync Bus In In Out DIGITAL UPCONVERTER Out VCXO TIMING BUS Clock / Sync /Gate / PPS COBALT: VIRTEX-6 LX130T, LX240T, LX365T, SX315T or SX475T ONYX: VIRTEX-7 VX330T, VX485T or V 690T LVDS CONFIG Config Bus ONYX Only 8X GATEXPRESS CONFIGURATION MANAGER VPX BACKPLANE CONFIG 64 MB COBALT Only CROSSBAR SWITCH Gbit Gbit Serial Serial VPX-P1 8X Gbit Serial Gbit Serial Option -105 Serial I/O 40 VPX-P2 Option -104 QDRII QDRII QDRII Cobalt Configurations Onyx Configuration QDRII PCI Express r s Interface e The Cobalt 3U OpenVPX board includes an industry-standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Gen. 2 provides 4 GB/sec peak data transfer rate. The Onyx 3U OpenVPX board includes an industry-standard interface fully compliant with PCI Express Gen. 1, 2 & 3 bus specifications. Gen. 3 provides 8 GB/sec peak transfer rate. The interface includes multiple DMA controllers for efficient transfers and the board. Fabric-T ransparent n a n Crossbar C sb r Switch The 3U OpenVPX Cobalt or Onyx board features a unique high-speed switching configuration. A fabric-transparent crossbar switch bridges numerous interfaces and components on the board using gigabit serial data paths with no latency. Programmable signal input equalization and output pre-emphasis settings enable optimization. Data paths can be selected as single (1X) lanes, or groups of four lanes () for routing over the VPX-P1 connecr. 11 Optional i a Interfaces I t a e Option -104 provides 20 pairs of LVDS connections between the and the VPX-P2 connecr for cusm I/O. Option -105 connects two gigabit serial links the on P the crossbar switch for routing VPX-P1.

12 Cobalt & Onyx Formats & Interfaces CompactPCI I Formatsr a As shown here, the CompactPCI format is available in three configurations: 6U cpci with double density; this configuration mounts two modules on a 6U carrier board. 6U cpci with single density; this configuration mounts only one module on a 6U carrier board. 3U cpci mounts one module on a 3U carrier board In order describe these three configurations in more detail, we have omitted the components and circuitry shown in the previous three formats; we just show the Virtex-6/Virtex-7 s with the external connections that define the standard and optional interfaces. LVDS VIRTEX-6/VIRTEX-7 1st MODULE VIRTEX-6/VIRTEX-7 2nd MODULE LVDS 6U 6 cpci C Double u e Densityn Two --PCI bridges connect the x4 interfaces each module a PCI--PCI bridge. This bridge connects both modules the 32- or 64-bit, 33/66 MHz PCI/PCI-X bus. 40 x4 x4 x4 x4 40 Config Config Bus Bus Option -104 CONFIG cpci J3 ONYX Only GATEXPRESS CONFIGURATION MANAGER x4 PCI BRIDGE 6U cpci C Optional t o l Interfacee e CONFIG 64 MB COBALT Only PCI/PCI-X Bus Option -104 provides 20 pairs of LVDS connections between the and the J3 connecr for cusm I/O. The J5 connecr supports Option -104 for the 2nd module. PCI PCI BRIDGE CONFIG 64 MB COBALT Only PCI BRIDGE 32/64-bit, 33/66 MHz GATEXPRESS CONFIGURATION MANAGER x4 6U cpci I Single e Density n CONFIG ONYX Only Option -104 cpci J5 The 2nd module, its associated --PCI bridge and the optional interface connection J5 are not present. LVDS VIRTEX-6/VIRTEX-7 40 Option -104 CONFIG ONYX Only Config Bus GATEXPRESS CONFIGURATION MANAGER x4 x4 x4 PCI BRIDGE CONFIG 64 MB COBALT Only 3U 3 cpci c C Single l e Density n y A --PCI bridge connects the x4 interface the module the 32-bit, 33/66 MHz PCI/PCI-X bus. cpci J3 PCI/PCI-X Bus 32-bit, 33/66 MHz 3U cpci C Optional t n Interfacen e c Option -104 provides 20 pairs of LVDS connections between the and the J3 connecr for cusm I/O. 12

13 Support Software Pentek e ReadyFlow y l Board d Support t Package Users of high-performance data acquisition and signal processing boards often find themselves frustrated by the fact that when their new devices are delivered, they are unable put them immediate use. To address this issue, Pentek has developed the ReadyFlow BSPs (Board Support Packages) for all of its board-level products. The package contains C-language examples that demonstrate the capabilities of Pentek products. The examples included provide the answers most of the questions that occur with firsttime users of these products. ReadyFlow BSPs are designed reduce development time during the initial stages and when new hardware is added the system. All packages are built with a consistent style and functionnaming convention. Similar parameters on different boards have similar function calls, thereby allowing immediate familiarity with new hardware. Command o a Line e Interfacen e c The Command Line Interface is a precompiled executable that runs the hardware right out of the box, without the need write any code. Specific the hardware features of the supported board, it allows operating arguments be entered on the command line for controlling board parameters. For command line functions that control data acquisition, the captured data can be saved in a host file or routed the Signal Analyzer. Signal i a l AnalyzerA a z When used with the Command Line Interface, the Signal Analyzer allows users immediately. start acquiring and displaying data. A full-featured analysis ol, the Signal Analyzer displays data in time and frequency domains. Built-in measurement functions display 2nd and 3rd harmonics, THD (tal harmonic disrtion), and SINAD (signal noise and disrtion). Interactive cursors allow users mark data points and instantly calculate amplitude and frequency of displayed signals. Pentek e GateFlow e l A Design Kit Using g t the Design e n Kit The GateFlow Design Kit allows the user modify, replace and extend the standard facry-installed functions in the incorporate special modes of operation, new control structures, and specialized signal-processing algorithms. The Cobalt or Onyx architecture configures the with standard facry-supplied interfaces including memory controllers, DMA engines, and interfaces, timing and synchronization structures, triggering and gating logic, time stamping and header tagging, data formatting engines, and the interface. These resources are connected the User Application Container using well-defined ports that present easy--use data and control signals, effectively abstracting the lower level details of the hardware. The e User e Application l a i o Containero a e Shown here is the block diagram of a typical Cobalt/Onyx module. The User Application Container holds a collection of different facry-installed IP modules connected the various interfaces through the standard ports surrounding the container. The specific IP modules for each product are described in further detail in the following pages. The GateFlow Design Kit provides a complete Xilinx ISE Foundation Tool project folder containing all the files Sync Bus Interface Clock Generar Controller Controller Global Registers Interface 13 Board Registers User Application Container PCI Express Backend PCI Express Interface necessary for the developer recompile the entire project with or without any required changes. VHDL source code for each IP module provides excellent examples of how the IP modules work, how they might be modified, and how they might be replaced with cusm IP implement a specific function. Front Panel Interface Facry Installed Base Function Application & Control Data Packing & Formatting Meta Data Files Linked-List Control Linked-List Control User Registers DMAs P14 LVDS P MGTs Timestamp Test Generar Controller Controller Defined and documented interface signals V6orV7

14 Models & 71720: 1 2 : T ransceiver i v r with Three e s, D DUC,, T wo s / s - Features s Model 720 Model 720 is a member of the Cobalt family of high performance modules based on the Xilinx Virtex-6. Model is a member of the Onyx family of high-performance modules based on the Virtex-7. These multichannel, high-speed data converters, it is suitable for connection HF or IF ports of a communications or radar system. Their built-in data capture and playback features offer an ideal turnkey solution. Each model includes three s, one DUC, two s and four banks of memory. In addition supporting PCI Express as a native interface, these models include general-purpose and gigabit serial connecrs for applicationspecific I/O. Model Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT or Virtex-7 VXT s Model 71720: GateXpress supports dynamic reconfiguration across Three 200 MHz -bit s One digital upconverter Two 800 MHz -bit s Model 720: Up 2 GB of or 32 MB of QDRII+ ; Model 71720: 4 GB of Sample clock synchronization an external system reference LVPECL clock/sync bus for multimodule synchronization Model 720: PCI Express (Gen. 1 & 2) interface up x8; Model 71720: PCI Express (Gen. 1, 2, and 3) interface up x8 Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O ConvertersC v t s The front end accepts three full-scale analog HF or IF inputs on front panel SSMC connecrs at +8 dbm in 50 ohms with transformer coupling in three Texas Instruments ADS MHz, -bit converters. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. Sample C k / Reference Clk In TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate Gate Sync / PPS Sync / PPS Timing Bus TIMING BUS Clock / Sync / Gate / PPS VCXO CONFIG Clock/Sync Bus Clock/Sync Bus ONYX Only Config Bus P15 8X GATEXPRESS CONFIGURATION MANAGER 200 MHz BIT CONFIG 64 MB COBALT Only COBALT: VIRTEX-6 LX130T, LX240T, LX365T, SX315T or SX475T 8X 200 MHz BIT P15 Digital g a Upconverter e e and s A TI DAC5688 DUC (digital upconverter) and accepts a baseband real or complex data stream the which is optionally interpolated, upconverted and then delivered the two s. When operating as a DUC, it interpolates and translates real or complex baseband input signals any IF center frequency up 360 MHz. It delivers real or quadrature (I+Q) digital outputs the dual -bit converter. Analog output is through a pair of front panel SSMC connecrs. If translation is disabled, the DAC5688 acts as a dual interpolating -bit with output sampling rates up 800 MHz. In both modes the DAC5688 provides interpolation facrs of 2x, 4x and 8x. In In In Out Out ONYX: VIRTEX-7 VX330T, VX485T or V 690T LVDS Option -105 Serial I/O P 200 MHz BIT 40 Coba t 48 Onyx Option -104 P14 PMC QDRII+ 800 MHz 800 MHz BIT BIT DIGITAL UPCONVERTER QDRII+ 32 QDRII+ Cobalt Configurations QDRII+ Contact Pentek for availability of rugged and conduction-cooled versions Onyx Configuration 14

15 Models o & 71720: : T ransceiver e with h Three T e s, / DUC, C T wo s / A s - C Installed n t d I IP Modulesu s The facry-installed functions in both models include three acquisition and a waveform playback IP modules, ideally matched the board s analog interfaces. IP modules for either or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facryinstalled functions and enable these models operate as a complete turnkey solution, without the need develop any IP. Acquisition u i IP P Modules o Both models feature three Acquisition IP Modules for easily capturing and moving data. Each module can receive data any of the three s, a test signal generar or the Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. Bank 1 PACKING & FLOW META IP MODULE 1 Ch 1 Bank 2 Ch 2 Ch 3 INPUT MULTIPLEXER PACKING & FLOW META IP MODULE 2 W aveform a o Playback l IP Modulel The facry-installed functions in both models include a sophisticated Waveform Playback IP module. A linked-list controller allows users easily play back the dual s waveforms sred in either on-board memory or off-board host memory. Parameters including length of waveform, delay playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. loopback Bank 3 PACKING & FLOW META IP MODULE 3 TEST SIGNAL Bank 4 UNPACKING & FLOW WAVEFORM PLAYBACK IP MODULE VIRTEX-6/VIRTEX-7 X FLOW DETAIL INTEACE (supports user installed IP) Bank 1 Bank 2 Bank 3 Bank 4 8X 40 Model 720 Gigabit Serial I/O 48 Model

16 Models & 71720: 1 2 : T ransceiver i v r with Three e s, D DUC,, T wo s / s - Also o A vailablea b Specificationsp c f ic io Model U cpci Model x8 PCI Express Model U VPX COTS and rugged Model U VPX COTS and rugged Model U cpci Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with interpolation Resolution: bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one clock and one clock Clock Synthesizer Clock Source: Selectable onboard programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, independently for the clock and clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus: 26-pin connecr LVPECL bus includes, clock/sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/pps inputs Model 720 Standard: C XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, XC6VLX365T, XC6VSX315T, or XC6VSX475T Model Standard: Xilinx Virtex-7 XC7VX485T-2 Optional: Xilinx Virtex-7 XC7VX330T-2 or XC7VX690T-2 Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs ( Model 720) or 24 pairs (Model 71720) the Option -105: Installs the P connecr configurable as one 8X or two gigabit serial links the Model 720 Option 150 or 0: Two 8 MB QDRII+ memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR Model Type: Size: Four banks, 1 GB each PCI-Express Interface Model 760 PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Model PCI Express Bus: Gen. 1, 2 or 3: x4 or x8; Gen. 3 available only with the VX330T-2 or VX690T-2 s Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard module, 2.91 in. x 5.87 in.

17 Model 721: 6 1 T ransceiver r c e e with h Three e s, / DDCs, D C, DUC,, T wo s / s - C The model 721 consists of a Model 720 as described previously, but with the addition of three multiband DDCs, one interpolar and one beamformer IP Cores installed in the Virtex-6. These IP Cores are in addition the facry-installed IP Modules described in the Model 720. DDC IP P Coresr Within each Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the Acquisition IP Modules, many different configurations can be achieved including one driving all three DDCs or each of the three s driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges DC ƒ s, where ƒ s is the sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as three different output bandwidths for the board. Decimations can be programmed 2 65,536 providing a wide range satisfy most applications. The decimating filter for each DDC accepts a unique set of usersupplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*ƒ s /N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 db. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or-bit I + -bit Q samples at a rate of ƒ s /N. Interpolar n e l o IP I Coreo The DAC5688 provides interpolation facrs of 2x, 4x and 8x. In addition the DAC5688, an -based interpolar core provides additional interpolation 2x 65,536x. The two interpolars can be combined crate a tal range 2x 524,288x. Beamformer a o m IP CoreC r In addition the DDCs, the 721 features a complete beamforming subsystem. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up 8K samples. The power meters present average power measurements for each DDC core output in easy--read registers. next board Bank 1 AURORA GIGABIT SERIAL INTEACE sum out sum in DDC DEC: 2TO PACKING & FLOW META IPMODULE 1 SUMMER BEAMFORMER CORE previous board Ch 1 Ch 2 Ch 3 INPUT MULTIPLEXER DDC DEC: 2TO PACKING & FLOW META META Bank 2 Bank 3 IPMODULE 2 loopback PACKING & FLOW VIRTEX-6 FLOW DETAIL DDC DEC: 2TO POWER METER & THRESHOLD POWER METER & THRESHOLD POWER METER & THRESHOLD DETECT DETECT DETECT DDC CORE DDC CORE DDC CORE In addition, each DDC core includes a threshold detecr aumatically send an interrupt the processor if the average power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the three DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back in the Acquisition IP Module 1 FIFO for reading over the. For larger systems, multiple 721 s can be chained gether via a built-in Xilinx Aurora gigabit serial interface through the P connecr. This allows summation across channels on multiple boards. IPMODULE 3 TEST SIGNAL Bank 4 INTEACE WAVEFORM PLAYBACK IP MODULE 8X INTERPOLATOR 2TO IP CORE UNPACKING & FLOW 17

18 Model e l 721: 6 1 T ransceiver r e with h Three h e s, / s, DDCs, D C DUC,, T wo s / s - C Also o A vailable a b Specificationsp c fic io Model U cpci Model x8 PCI Express Model U VPX COTS and rugged Model U cpci Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Digital Downconverters Quantity: Three channels Decimation Range: 2x 65,536x in two stages of 2x 256x LO Tuning Freq. Resolution: 32 bits, 0 ƒ s LO SFDR: >120 db Phase Offset Resolution: 32 bits, degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 db passband ripple, >100 db spband attenuation Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: bits Digital Interpolar Interpolation Range: 2x 65,536x in two stages of 2x 256x Beamformer Summation: Three channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via connecr using Aurora procol Phase Shift Coefficients: I & Q with -bit resolution Gain Coefficients: -bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Front Panel Analog Signal Outputs Output: Transformer-coupled, front panel female SSMC connecrs Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one clock and one clock Clock Synthesizer Clock Source: Selectable onboard programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, independently for the clock and clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus: 26-pin connecr LVPECL bus includes, clock/sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/pps inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VLX365T, XC6VSX315T, or XC6VSX475T Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option 150 or 0: Two 8 MB QDRII+ memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard module, 2.91 in. x 5.87 in. 18

19 Model e 730: 1 3 : 1 GHz z, /, 1 GHz z / A - C Model 730 is a member of the Cobalt family of high performance modules based on the Xilinx Virtex-6. A high-speed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes 1 GHz and converters and four banks of memory. In addition supporting PCI Express Gen. 2 as a native interface, the Model 730 includes optional general purpose and gigabit serial card connecrs for application-specific I/O. Featuresa r Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s One 1 GHz 12-bit One 1 GHz -bit Up 2 GB of or MB of QDRII+ Sample clock synchronization an external system reference LVPECL sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up x8 Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O Contact Pentek for availability of rugged and conduction-cooled versions Convertero e e The front end accepts an analog HF or IF input on a front panel SSMC connecr with transformer coupling in a Texas Instruments ADS GHz, 12-bit converter. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. Sample Clk / Reference Clk In TTL PPS/Gate/Sync Gate In Sync In Sync Bus Gate In Sync In Sync Bus TIMING BUS Clock / Sync / Gate / PPS VCXO Clock/Sync Bus Clock/Sync Bus VIRTEX-6 LX130T, LX240T, LX365T, SX315T or SX475T Converter o e r The 730 features a TI DAC5681Z 1 GHz, -bit. The converter has an input sample rate of 1 GSPS, allowing it acept full rate data the. Additionally, the includes a 2x or 4x interpolation filter for applications that provide 1/2 or 1/4 rate input data. Analog output is transformercoupled a front panel SSMC connecr. In 1 GHz 12-BIT 12 Config 64 MB Out 1 GHz -BIT 8X LVDS 40 Banks 1&2 Banks 3&4 option 155 option 5 QDRII+ QDRII+ QDRII+ option 150 x8 P15 Gigabit Serial I/O (option 105) P (option 104) P14 PMC 19

20 Model l 730: 1 3 : 1 GHz z, /, 1 GHz A - C Installed I t a d IP Modules d s The 730 facry-installed functions include an acquisition and a waveform playback IP module. In addition, IP modules for either or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generar and a interface complete the facryinstalled functions and enable the 730 operate as a complete turnkey solution, without the need develop any IP. Acquisition i IP P Module o The 730 features an Acquisition IP Module for easy capture and data moving. The IP module can receive data the, a test signal generar, or the Waveform Playback IP Module in loopback mode. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. LER Bank 1 Bank 2 PACKING & FLOW META loopback INPUT MULTIPLEXER IP MODULE Bank 3 / W aveform a Playback a ac k IP Moduleo l The Model 730 facry-installed functions include a sophisticated Waveform Playback IP module. A linked-list controller allows users easily play back waveforms sred in either on-board memory or off- board host memory the. Parameters including length of waveform, delay playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. LER TEST SIGNAL Bank 4 UNPACKING & FLOW WAVEFORM PLAYBACK IP MODULE VIRTEX-6 FLOW DETAIL INTEACE (supports user installed IP) Bank 1 Bank 2 Bank 3 Bank 4 8X 40 Gigabit Serial I/O 20

21 Model e 730: 1 3 : 1 GHz z, /, 1 GHz z / A - C Also o A vailable a b Specificationsp c fic io Model U cpci Model x8 PCI Express Model U VPX COTS and rugged Model U cpci Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Converter Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz 1 GHz Resolution: 12 bits Converter Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connecrs Sample Clock Sources: On-board clock synthesizer generates two clocks: one clock and one clock Clock Synthesizer Clock Source: Selectable onboard programmable VCXO or front panel external clock VCXO Frequency Ranges: MHz, MHz, and MHz Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, independently for the clock and clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts 100 MHz 1 GHz divider input clock, or PLL system reference Timing Bus: 7-pin connecrs, LVPECL bus for sync and gate, one connecr and one connecr External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2, XC6VLX365T-2, XC6VSX315T-2, or XC6VSX475T-2 Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option -105: Installs the P connecr configurable as one 8X or two gigabit serial links the Option 150: Two 8 MB QDRII+ memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen.1 or Gen.2, x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard module, 2.91 in. x 5.87 in. 21

22 Model o l 740: 1 4 : 1-Ch annel e 3.6. GHz or 2-Ch - annel e l GHz, 12-bit C Model 740 is a member of the Cobalt family of high performance modules based on the Xilinx Virtex-6. A high-speed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes a 3.6 GHz, 12-bit converter and four banks of memory. In addition supporting PCI Express Gen. 2 as a native interface, the Model 740 includes optional general purpose and gigabit serial connecrs for application-specific I/O. ConverterC nv e The front end accepts analog HF or IF inputs on a pair of front panel SSMC connecrs with transformer coupling in a Texas Instruments ADC12D bit. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the 740 have a full scale input range of +2 dbm +4 dbm. A built-in AuSync feature supports synchronization across multiple modules. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. Featuresa r Ideal radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s One-channel mode with 3.6 GHz, 12-bit Two-channel mode with 1.8 GHz, 12-bit s 2 GB of Sync bus for multimodule synchronization PCI Express Gen. 2 interface x8 Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O Sample C k TTL PPS/Gate/Sync TIMING BUS Clock/Sync Bus 3.6 GHz (1 Channel) or Gate In Reset In Clock / Sync / Gate / PPS 1.8 GHz (2 Channel) 12-Bit Ref Clk In Ref Clk Out Sync Bus In In VIRTEX-6 LX130T, LX240T, LX365T, SX315T or SX475T Contact Pentek for availability of rugged and conduction-cooled versions Config 64 MB 8X LVDS 40 Banks 1&2 Banks 3&4 x8 Gigabit Serial I/O (option 105) (option 104) P15 P P14 PMC 22

23 Installed s l IP Modules u Model e 740: 1-Ch annel e G GHz or 2-Ch - hannel ne l GHz, 12-bit 1 - t / - The 740 facry-installed functions include an acquisition IP module. In addition, IP modules for memories, a controller for all data clocking and synchronization functions, a test signal generar and a interface complete the facry-installed functions and enable the 740 operate as a complete turnkey solution, without the need develop any IP. Acquisition q n IP Module l e The 740 features an Acquisition IP Module for easy capture and data moving. The IP module can receive data the, or a test signal generar. The IP module has associated memory banks for buffering data in FIFO mode or for sring data in transient capture mode. In single-channel mode, all four banks are used sre the single-channel of input data. In dual-channel mode, memory banks 1 and 2 sre data input channel 1 and memory banks 3 and 4 sre data input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. The memory banks are supported with a DMA engine for moving data through the interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. VIRTEX-6 FLOWA DETAIL (Two channel mode shown) INPUT MULTIPLEXER TEST SIGNAL PACKING & FLOW META MEM PACKING & FLOW META IP MODULE IP MODULE LER LER INTEACE (supports user installed IP) Bank 1 Bank 2 8X 40 Gigabit Serial I/O Bank 3 Bank 4 23

24 Model o l 740: 1 4 : 1-Ch annel e 3.6. GHz or 2-Ch - annel e l GHz, 12-bit C Also o A vailablea b Specifications c i a io Model x8 PCI Express Model U VPX COTS and rugged Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz 3.6 GHz; dual-channel mode: 150 MHz 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dbm +4 dbm, programmable Sample Clock Sources: Front panel SSMC connecr Sync Bus: Multi-pin connecrs, bus includes gate, reset and in and out ref clock External Trigger Input Type: Front panel female SSMC connecr, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2, XC6VLX365T-2, XC6VSX315T-2, or XC6VSX475T-2 Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option -105: Installs the P connecr configurable as one 8X or two gigabit serial links the : Four memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard module, 2.91 in. x 5.87 in. Model U cpci Model U cpci 24

25 Model o l 750: 1 5 : T r ransceiver a s r with i t T wo s, /, DUC, C, T wo s / s - X C Model 750 is a member of the Cobalt family of high performance mod- -ules based on the Xilinx Virtex-6. A multichannel, high-speed data converter, it is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes two s, one DUC, two s, and four banks of memory. In addition supporting PCI Express Gen. 2 as a native interface, the Model 750 includes optional general-purpose and gigabit serial card connecrs for application-specific I/O. Featuresa r Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s Two 500 MHz 12-bit s One digital upconverter Two 800 MHz -bit s Up 2 GB of or 32 MB of QDRII+ Sample clock synchronization an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up x8 Optional user configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O A Convertero r r The front end accepts two full-scale analog HF or IF inputs on front panel SSMC connecrs at +5 dbm in 50 ohms with transformer coupling in two Texas Instruments ADS MHz, 12-bit converters. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. Sample Clk / Reference Clk In TTL PPS/Gate/Sync TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate Gate Sync / PPS Sync / PPS Timing Bus TIMING BUS Clock / Sync / Gate / PPS VCXO Clock/Sync Bus Clock/Sync Bus In 500 MHz 12-BIT Digital g a Upconverter c n e e and s A TI DAC5688 DUC and accepts a baseband real or complex data stream the which is optionally interpolated, upconverted and then delivered the two s. When operating as a DUC, it interpolates and translates real or complex baseband input signals any IF center frequency up 360 MHz. It delivers real or quadrature (I+Q) digital outputs the dual -bit converter. Analog output is through a pair of front panel SSMC connecrs. If translation is disabled, the DAC5688 acts as a dual interpolating -bit converter with output sampling rates up 800 MHz. In both modes the DAC5688 provides interpolation facrs of 2x, 4x and 8x. In 500 MHz 12-BIT VIRTEX-6 LX130T, LX240T, LX365T, SX315T or SX475T Out 800 MHz -BIT 32 Out 800 MHz -BIT DIGITAL UPCONVERTER LVDS Contact Pentek for availability of rugged and conduction-cooled versions QDRII QDRII QDRII QDRII Config 64 MB 8X 40 QDRII option 150 option 155 QDRII option 0 option 5 Banks1&2 Banks 3&4 x8 P15 Gigabit Serial I/O (option 105) P (option 104) P14 PMC 25

26 Model l 750: 1 5 : T ransceiver r with h T wo s, A, DUC,, T wo s / s - Installed s l l IP Modules u The 750 facry-installed functions include two acquisition and one waveform playback IP modules. In addition, IP modules for either or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generar and a interface complete the facryinstalled functions and enable the 750 operate as a complete turnkey solution, without the need develop any IP. Acquisition u i IP P Modules o The 750 features two Acquisition IP Modules for easy capture and data moving. Each IP module can receive data either of the two s, a test signal generar or the Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. Bank 1 PACKING & FLOW META IP MODULE 1 Ch 1 Ch 2 INPUT MULTIPLEXER Bank 2 PACKING & FLOW META IP MODULE 2 W a aveform Playback l y a k IP P Moduleu e The Model 750 facry-installed functions include a sophisticated Waveform Playback IP module. A linked-list controller allows users easily play back waveforms sred in either on-board memory or off- board host memory the dual s. Parameters including length of waveform, delay playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. loopback TEST SIGNAL Bank 3 UNPACKING & FLOW WAVEFORM PLAYBACK IP MODULE VIRTEX-6 FLOW DETAIL INTEACE (supports user installed IP) Bank 1 Bank 2 Bank 3 Bank 4 8X 40 Gigabit Serial I/O 26

27 Model o l 750: 1 5 : T r ransceiver a s r with i t T wo s, /, DUC, C, T wo s / s - X C Also Available Specifications a io Model U cpci Model x8 PCI Express Model U VPX COTS and rugged Model U cpci Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters (standard) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz 500 MHz Resolution: 12 bits Converters (option 014) Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz 400 MHz Resolution: 14 bits Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz, max. Output IF: DC 400 MHz, max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz, max. with interpolation Resolution: bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one clock and one clock Clock Synthesizer Clock Source: Selectable onboard programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, independently for the clock and clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connecr LVPECL bus includes, clock/ sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/ PPS inputs External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2, XC6VLX365T-2, XC6VSX315T-2, or XC6VSX475T-2 Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option -105: Installs the P connecr configurable as one 8X or two gigabit serial links the Option 150 or 0: Two 8 MB QDRII+ memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen.1 or Gen.2, x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard module, 2.91 in. x 5.87 in. 27

28 Model o l 751: 1 5 : T ransceiver r with h T wo s,, DDC, C, DUC, C T wo s A - C The model 751 consists of a Model 750 as described previously, but with the addition of two powerful DDCs and a beamformer IP Cores installed in the Virtex-6. These IP Cores are in addition the facry-installed IP modules described in the Model 750. The decimating filter for each DDC accepts a unique set of usersupplied -bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*ƒ s /N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 db. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or-bit I + -bit Q samples at a rate of ƒ s /N. Beamformer a o m r IP CoreC re In addition the DDCs, the 751 features a complete beamforming subsystem. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up 8K samples. The power meters present average power measurements for each DDC core output in easy--read registers. In addition, each DDC core includes a threshold detecr aumatically send an interrupt the processor if the average power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the two DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back in the Acquisition IP Module 1 FIFO for reading over the. For larger systems, multiple 751 s can be chained gether via a built-in Xilinx Aurora gigabit serial interface through the P connecr. This allows summation across channels on multiple boards. DDC IP I Coreso s Within each Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the Acquisition IP Modules, many different configurations can be achieved including one driving both DDCs or each of the two s driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges DC ƒ s, where ƒ s is the sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as two different output bandwidths for the board. Decimations can be programmed 2 131,072 providing a wide range satisfy most applications. AURORA GIGABIT SERIAL INTEACE next board Bank 1 sum out sum in BEAMFORMER CORE previous board Ch 1 DDC DEC: 2TO PACKING & FLOW META SUMMER POWER METER & THRESHOLD DETECT DDC CORE IPMODULE 1 Ch 2 INPUT MULTIPLEXER Bank 2 loopback DDC DEC: 2TO POWER METER & THRESHOLD DETECT DDC CORE PACKING & FLOW META IPMODULE 2 VIRTEX-6 FLOWA DETAIL TEST SIGNAL Bank 4 INTEACE WAVEFORM PLAYBACK IP MODULE 8X INTERPOLATOR 2TO IP CORE UNPACKING & FLOW 28

29 Model e 751: 1 T ransceiver e e with h Two s, DDC, D, DUC, C, Two s / s - X C Also Available Specifications a io Model U cpci Model x8 PCI Express Model U VPX COTS and rugged Model U cpci Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer: Coil Craft WBC4-6TLB Full Scale Input: +5 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters (standard) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz 500 MHz Resolution: 12 bits Converters (option -014) Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz 400 MHz Resolution: 14 bits Digital Downconverters Quantity: Two channels Decimation Range: 2x 131,072x in two programmable stages of 2x 256x and one fixed 2x stage LO Tuning Freq. Resolution: 32 bits, 0 ƒ s LO SFDR: >120 db Phase Offset Resolution: 32 bits, degrees FIR Filter: -bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 db passband ripple, >100 db spband attenuation Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: bits Digital Interpolar Interpolation Range: 2x 65,536x in two stages of 2x 256x Beamformer Summation: Two channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via connecr using Aurora procol Phase Shift Coefficients: I & Q with -bit resolution Gain Coefficients: -bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit 29 Front Panel Analog Signal Outputs Output: Transformer-coupled, front panel female SSMC connecrs Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one clock and one clock Clock Synthesizer Clock Source: Selectable onboard programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, independently for the clock and clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus: 26-pin connecr LVPECL bus includes, clock/sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/pps inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VLX365T, XC6VSX315T, or XC6VSX475T Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option -150: Two 8 MB QDRII+ memory banks, 400 MHz DDR Option -155 or -5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 2: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Standard, 2.91 in. x 5.87 in.

30 Models & 71760: 7 4-Channel l 2000 MHz A D - C Model 760 Model 760 is a member of the Cobalt family of high performance modules based on the Xilinx Virtex-6. Model is a member of the Onyx family of high-performance modules based on the Virtex-7. These multichannel, high-speed data converters, are suitable for connection HF or IF ports of a communications or radar system. Their built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. Each model includes four s and four banks of memory. In addition supporting PCI Express as a native interface, these models include generalpurpose and gigabit serial connecrs for application-specific I/O. Model Featuresa t r Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT or Virtex-7 VXT s Model 71720: GateXpress supports dynamic reconfiguration across Four 200 MHz -bit s Model 760: Up 2 GB of or 32 MB of QDRII+ ; Model 71760: 4 GB of Sample clock synchronization an external system reference LVPECL clock/sync bus for multimodule synchronization Model 760: PCI Express (Gen. 1 & 2) interface up x8; Model 71760: PCI Express (Gen. 1, 2, and 3) interface up x8 Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O Contact Pentek for availability of rugged and conduction-cooled versions ConvertersC nve e The front end accepts four full-scale analog HF or IF inputs on front panel SSMC connecrs at +8 dbm in 50 ohms with transformer coupling in four Texas Instruments ADS MHz, -bit converters. The digital outputs are delivered in the for signal processing, data capture or for routing other module resources. Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B Timing Bus TIMING BUS Clock / Sync / Gate / PPS VCXO CONFIG ONYX Only Clock/Sync Bus Config Bus P15 8X GATEXPRESS CONFIGURATION MANAGER CONFIG 64 MB COBALT Only In 200 MHz BIT COBALT: VIRTEX-6 LX130T, LX240T, LX365T, SX315T or SX475T 8X P15 ONYX: VIRTEX-7 VX330T, VX485T or V 690T LVDS In 200 MHz BIT Option -105 Serial I/O P 40 Coba t 48 Onyx Option -104 P14 PMC In 200 MHz BIT QDRII+ In 200 MHz BIT QDRII+ QDRII+ Cobalt Configurations QDRII+ Onyx Configuration 30

31 Models o & 71760: 1 : 4-Channel 200 MHz z / - X Installed s l IP Modules u The facry-installed functions in both models include four acquisition IP modules. IP modules for either or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facryinstalled functions and enable these models operate as complete turnkey solutions without the need develop any IP. Acquisition i n IP I Modules u s Both models feature four Acquisition IP modules for easily capturing and moving data. Each IP module can receive data any of the four s or a test signal generar Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. Ch 1 Ch 2 Ch 3 Ch 4 TEST SIGNAL INPUT MULTIPLEXER PACKING & FLOW PACKING & FLOW PACKING & FLOW PACKING & FLOW Bank 1 META Bank 2 META Bank 3 META Bank 4 META IP MODULE 1 IP MODULE 2 IP MODULE 3 IP MODULE 4 VIRTEX-6/VIRTEX-7X FLOW DETAIL INTEACE (supports user installed IP) Bank 1 Bank 2 Bank 3 Bank 4 8X Gigabit Serial I/O 40 Model Model

32 Models & 71760: 7 4-Channel l 2000 MHz A D - C Also o A vailable a b Specificationsp c fic io Model x8 PCI Express Model U VPX COTS and rugged Model U VPX COTS and rugged Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable onboard programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connecr; LVPECL bus includes, clock/sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Model 760 Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, XC6VLX365T, XC6VSX315T, or XC6VSX475T Model 7760 Standard: Xilinx Virtex-7 XC7VX485T-2 Optional: Xilinx Virtex-7 XC7VX330T-2 or XC7VX690T-2 Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs (Model 760) or 24 pairs (Model 71760) the Option -105: Installs the P connecr configurable as one 8X or two gigabit serial links the Model 760 Option 150 or 0: Two 8 MB QDRII+ memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR Model Type: Size: Four banks, 1 GB each PCI-Express Interface Model 760 PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Model PCI Express Bus: Gen. 1, 2 or 3: x4 or x8; Gen. 3 available only with the VX330T-2 or VX690T-2 s Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard module, 2.91 in. x 5.87 in. Model U cpci Model U cpci 32

33 Model o 761: 1 6 : 4-Channel MHz / with h DDCs D C and Beamformer B e r - X C The model 761 consists of a Model 760 as described previously, but with the addition of four multiband DDCs, and one beamformer IP Cores installed in the Virtex-6. These IP Cores are in addition the facry-installed IP Modules described in the Model 760. DDC I IP Coreso s Within each Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the Acquisition IP Modules, many different configurations can be achieved including one driving all four DDCs or each of the four s driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges DC ƒ s, where ƒ s is the sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as three different output bandwidths for the board. Decimations can be programmed 2 65,536 providing a wide range satisfy most applications. The decimating filter for each DDC accepts a unique set of usersupplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*ƒ s /N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 db. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or-bit I + -bit Q samples at a rate of ƒ s /N. Beamformer e f r e IP P Coreo In addition the DDCs, the 761 features a complete beamforming subsystem. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up 8K samples. The power meters present average power measurements for each DDC core output in easy--read registers. In addition, each DDC core includes a threshold detecr aumatically send an interrupt the processor if the average power level of any DDC core falls below or exceeds a programmable threshold. TEST SIGNAL next board Bank 1 AURORA GIGABIT SERIAL INTEACE sum out sum in SUMMER BEAMFORMER CORE prevous board DDC DEC: 2TO PACKING & FLOW META IPMODULE 1 Ch 1 DDC DEC: 2TO PACKING & FLOW IPMODULE 2 Ch 2 A programmable summation block provides summing of any of the four DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back in the Acquisition IP Module 1 FIFO for reading over the. For larger systems, multiple 761 s can be chained gether via a built-in Xilinx Aurora gigabit serial interface through the P connecr. This allows summation across channels on multiple boards. INPUT MULTIPLEXER VIRTEX-6 FLOW DETAIL Ch 3 DDC DEC: 2TO PACKING & FLOW IPMODULE 3 Ch 4 DDC DEC: 2TO POWER METER & THRESHOLD POWER METER & THRESHOLD POWER METER & THRESHOLD POWER METER & THRESHOLD DETECT DETECT DETECT DETECT DDC CORE DDC CORE DDC CORE DDC CORE PACKING & FLOW META META META Bank 2 Bank 3 Bank 4 IPMODULE 4 INTEACE 8X 33

34 Model 761: Channel C l MHz A with DDCs D C and Beamformer e e - Also o A vailable a b Specificationsp c fic io Model U cpci Model x8 PCI Express Model U VPX COTS and rugged Model U cpci Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Digital Downconverters Quantity: Four channels Decimation Range: 2x 65,536x in two stages of 2x 256x LO Tuning Freq. Resolution: 32 bits, 0 ƒ s LO SFDR: >120 db Phase Offset Resolution: 32 bits, degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 db passband ripple, >100 db spband attenuation Beamformer Summation: Four channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via connecr using Aurora procol Phase Shift Coefficients: I & Q with -bit resolution Gain Coefficients: -bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable onboard programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus: 26-pin connecr LVPECL bus includes, clock/sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VLX365T, XC6VSX315T, or XC6VSX475T Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option 150 or 0: Two 8 MB QDRII+ memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard module, 2.91 in. x 5.87 in. 34

35 Model o l 762: 1 62 : 4-Channel MHz z / with t h 32-Channel 2 l DDC D - The model 762 consists of a Model 760 as described previously, but with the addition of four 8-Channel DDC IP Cores installed in the Virtex-6. These IP Cores are in addition the facry-installed IP Modules described in the Model 760. DDC I IP Coreso s Within each Acquisition IP Module is a powerful 8-channel DDC bank. Because of the flexible input routing of the Acquisition IP Modules, many different configurations can be achieved including one driving all 32 DDC channels or each of the four s driving its own DDC bank. Each of the 32 channels has an independent 32-bit tuning frequency setting that ranges DC ƒ s, where ƒ s is the sampling frequency. All of the 8 channels within a bank share a common decimation setting that can range 8192, programmable in steps of 8. For example, with a sampling rate of 200 MHz, the available output bandwidths range khz 10.0 MHz. Each 8-channel bank can have its own unique decimation setting supporting a different bandwidth associated with each of the four acquisition modules. The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*ƒ s /N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 db. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of ƒ s /N. Any number of channels can be enabled within each bank, selectable 0 8. Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within a bank. Ch 1 Ch 2 Ch 3 Ch 4 TEST SIGNAL INPUT MULTIPLEXER Bank 1 DIGITAL DOWN- CONVERTER BANK 1: CH 1-8 DEC: TO 8192 DDC CORE PACKING & FLOW META IP MODULE 1 DIGITAL DOWN- CONVERTER BANK 2: CH 9- DEC: TO 8192 DDC CORE PACKING & FLOW META META META Bank 2 Bank 3 Bank 4 IP MODULE 2 DIGITAL DOWN- CONVERTER BANK 3: CH DEC: TO 8192 DDC CORE PACKING & FLOW IP MODULE 3 DIGITAL DOWN- CONVERTER BANK 4: CH DEC: TO 8192 DDC CORE PACKING & FLOW IP MODULE 4 VIRTEX-6 FLOW DETAIL INTEACE (supports user installed IP) 32 Bank 1 32 Bank 2 32 Bank 3 32 Bank 4 8X Gigabit Serial I/O 40 35

36 Model l 762: 1 6 : 4-Channel ne MHz / with h 32-Channel 2 n l DDC D - Also o A vailable a b Specificationsp c fic io Model U cpci Model x8 PCI Express Model U VPX COTS and rugged Model U cpci Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Digital Downconverters Quantity: Four 8-channel banks, one per acquisition module Decimation Range: x 8192x in steps of 8x LO Tuning Freq. Resolution: 32 bits, 0 ƒ s Phase Offset Resolution: 32 bits, degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, >100 db spband attenuation Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable onboard programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock, or PLL system reference Timing Bus: 26-pin connecr LVPECL bus includes, clock/sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VLX365T, XC6VSX315T, or XC6VSX475T Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option -105: Installs the P connecr configurable as one 8X or two gigabit serial links the Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard module, 2.91 in. x 5.87 in. 36

37 Model o 770: 1 7 : 4-Channel GHz A with DUC C - X C Model 770 is a member of the Cobalt family of high performance modules based on the Xilinx Virtex-6. This 4-channel, high-speed data converter is suitable for connection transmit HF or IF ports of a communications or radar system. Its built-in data playback features offer an ideal turnkey solution for demanding transmit applications. The 770 includes four s, four digital upconverters and four banks of memory. In addition supporting PCI Express Gen. 2 as a native interface, the Model 770 includes general purpose and gigabit serial connecrs for application-specific I/O. Featuresa r Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s Four 1.25 GHz -bit s Four digital upconverters Programmable output levels 250 MHz max. output bandwidth 2 GB of Sample clock synchronization an external system reference Dual-µSync clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up x8 Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O Contact Pentek for availability of rugged and conduction-cooled versions Sample Clk / Reference Clk In Trigger In Gate In Sync In Sync Bus A Gate In Sync In Sync Bus B TIMING BUS Clock / Sync / Gate / PPS VCXO Clock/Sync Bus A Clock/Sync Bus B Out 1.25 GHz -BIT DIGITAL UPCONVERTER VIRTEX-6 LX130T, LX240T, LX365T, SX315T or SX475T Out 1.25 GHz -BIT DIGITAL UPCONVERTER Banks1&2 Banks 3&4 Digital g i a l Upconverter v and n Two Texas Instruments DAC3484s provide four DUC (Digital Upconverter) and channels. Each channel accepts a baseband real or complex data stream the and provides that input the upconvert, interpolate and stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals a user selectable IF center frequency. It delivers real or quadrature (I+Q) analog outputs a -bit converter. If translation is disabled, each acts as an interpolating -bit with output sampling rates up 1.25 GHz. In both modes, the provides interpolation facrs of 2x, 4x, 8x and x. Analog output is through four front panel SSMC connecrs. Config 64 MB Out 1.25 GHz -BIT DIGITAL UPCONVERTER 8X x8 P15 Out 1.25 GHz -BIT DIGITAL UPCONVERTER Gigabit Serial I/O (option 105) P LVDS 40 (option 104) P14 PMC 37

38 Model l 770: 1 7 : 4-Channel GHz z with h DUC C - C Installed s l l IP Modules u The 770 facry-installed functions include four waveform playback IP modules, support waveform generation through the converters. IP modules for memories, a controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facry-installed functions and enable the 770 operate as a complete turnkey solution, without the need develop any IP. / W aveform f r Playback P a a IP Moduled The Model 770 facry-installed functions include a sophisticated Waveform Playback IP module. Four linked list controllers support waveform generation the four s tables sred in either on-board memory or off-board host memory. Data for Channel 1 and Channel 2 are interleaved for delivery a dual channel device. For this reason, they must share a common trigger/gate, sample rate, interpolation facr, and other parameters. The same rules apply Channel 3 and Channel 4. Parameters including length of waveform, waveform repetition, etc. can be programmed for each channel. Up 64 individual link entries for each channel can be chained gether create complex waveforms with a minimum of programming. Ch1&2 Ch3&4 TEST SIGNAL INTERLEAVER INTERLEAVER UNPACKING & FLOW UNPACKING & FLOW UNPACKING & FLOW UNPACKING & FLOW Bank 1 WAVEFORM PLAYBACK IP MODULE 1 Bank 2 WAVEFORM PLAYBACK IP MODULE 2 Bank 3 WAVEFORM PLAYBACK IP MODULE 3 Bank 4 WAVEFORM PLAYBACK IP MODULE 4 VIRTEX-6 FLOW A DETAIL INTEACE (supports user installed IP) Bank 1 Bank 2 Bank 3 Bank 4 8X 40 Gigabit Serial I/O 38

39 Model o 770: 1 7 : 4-Channel GHz A with DUC C - X C Also Available Specifications c i a io Model x8 PCI Express Model U VPX COTS and rugged Converters Type: TI DAC3484 Input Data Rate: MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or x Resolution: bits Front Panel Analog Signal Outputs Quantity: Four outputs Output Type: Transformer-coupled, front panel female SSMC connecrs Full Scale Output: Programmable 20 dbm (0.063 Vp-p) +4 dbm (1.0 Vp-p) in steps Full Scale Output Programming: 1.0x(G+1)/ Vp-p, where 4-bit integer G = 0 15 Clock Synthesizer Clock Source: Selectable onboard programmable VCXO, front panel external clock or µsync timing buses Synchronization: Clocks can be locked a front panel 5 or 10 MHz system reference External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz sample clock or 5 or 10 MHz system reference External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin µsync bus connecr includes, clock, reset and gate/ trigger inputs and outputs, CML Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2, XC6VLX365T-2, XC6VSX315T-2, or XC6VSX475T-2 Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option -105: Installs the P connecr configurable as one 8X or two gigabit serial links the : Four memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 or x8; Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard module, 2.91 in. x 5.87 in. Model U cpci Model U cpci 39

40 Model l 771: 1 7 : 4-Channel GHz z A with h DUC, Extended Interpolation I r t - The model 771 consists of a Model 770 as described previously, but with the addition of four wide-range programmable interpolation IP Cores installed in the Virtex-6. Installed in each of the four channels, these IP Cores are in addition the facry-installed IP modules described in the Model 770. A W aveform Playback b IP Module d l The Model 771 facry-installed functions include a sophisticated Waveform Playback IP module. Four linked-list controllers support waveform generation the four s tables sred in either on-board memory or off-board host memory. Data for Channel 1 and Channel 2 are interleaved for delivery a dual channel device. For this reason, they must share a common trigger/ gate, sample rate, interpolation facr, and other parameters. The same rules apply Channel 3 and Channel 4. Parameters including length of waveform, waveform repetition, etc. can be programmed for each channel. Up 64 individual link entries for each channel can be chained gether create complex waveforms with a minimum of programming. Ch1&2 Ch3&4 TEST SIGNAL INTERLEAVER INTERLEAVER INTERPOLATOR 2 TO IP CORE INTERPOLATOR 2 TO IP CORE INTERPOLATOR 2 TO IP CORE INTERPOLATOR 2 TO IP CORE UNPACKING & FLOW UNPACKING & FLOW UNPACKING & FLOW UNPACKING & FLOW Bank 1 WAVEFORM PLAYBACK IP MODULE 1 Bank 2 WAVEFORM PLAYBACK IP MODULE 2 Bank 3 WAVEFORM PLAYBACK IP MODULE 3 Bank 4 WAVEFORM PLAYBACK IP MODULE 4 VIRTEX-6 FLOW DETAIL INTEACE (supports user installed IP) Bank 1 Bank 2 Bank 3 Bank 4 8X 40 Gigabit Serial I/O 40

41 Model 771: 7 : 4-Channel n l 1.25 GHz H / with t DUC, U, Extended E e d Interpolation i o - X C Also Available SpecificationsS e Model x8 PCI Express Model U VPX COTS and rugged Converters Type: TI DAC3484 Input Data Rate: MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or x Resolution: bits Digital Interpolar Interpolation Range: 2x 65,536x in two stages of 2x 256x Front Panel Analog Signal Outputs Quantity: Four outputs Output Type: Transformer-coupled, front panel female SSMC connecrs Full Scale Output: Programmable 20 dbm (0.063 Vp-p) +4 dbm (1.0 Vp-p) in steps Full Scale Output Programming: 1.0x(G+1)/ Vp-p, where 4-bit integer G = 0 15 Clock Synthesizer Clock Source: Selectable onboard programmable VCXO, front panel external clock or µsync timing buses Synchronization: Clocks can be locked a front panel 5 or 10 MHz system reference External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz sample clock or 5 or 10 MHz system reference External Trigger Input Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin µsync bus connecr includes, clock, reset and gate/ trigger inputs and outputs, CML Field Programmable Gate Array Xilinx Virtex-6 XC6VLX240T-2, XC6VLX365T-2, XC6VSX315T-2, or XC6VSX475T-2 Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option -105: Installs the P connecr configurable as one 8X or two gigabit serial links the : Four memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 or x8; Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard module, 2.91 in. x 5.87 in. Model U cpci Model U cpci 41

42 Model e 790: 7 9 : L-Band d T uner r with t h 2-Channel C nel l MHz / - C Model 790 is a member of the Cobalt family of high performance modules based on the Xilinx Virtex-6. A 2-Channel highspeed data converter, it is suitable for connection directly the port of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes an L-Band tuner, two s and four banks of memory. In addition supporting PCI Express Gen. 2 as a native interface, the Model 790 includes general purpose and gigabit serial connecrs for applicationspecific I/O. Featurese t s Accepts signals 925 MHz 2175 MHz Programmable LNA boosts LNB (low-noise block) antenna signal levels with up 80 db gain Programmable analog downconverter provides I + Q baseband signals with bandwidths ranging 4 40 MHz Two 200 MHz -bit s Supports Xilinx Virtex-6 LXT and SXT s 2 GB of or 32 MB of QDRII+ Sample clock synchronization an external system reference PCI Express (Gen. 1 & 2) interface, up x8 Clock/sync bus for multimodule synchronization Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O Contact Pentek for availability of rugged and conduction-cooled versions T unerr A front panel SSMC connecr accepts L-Band signals between 925 MHz and 2175 MHz an antenna LNB (low noise block). A Maxim MAX2112 tuner directly converts these L-Band signals baseband using a broadband I/Q downconverter. The device includes an variablegain LNA (low noise amplifier), a PLL (phase- locked loop) synthesized local oscillar, quadrature (I + Q) downconverting mixers, baseband lowpass filters with programmable cuff frequency, and variable-gain baseband amplifiers. The fractional-n PLL synthesizer locks its VCO an on-board crystal, the timing generar output, or an Sample Clk / Reference Clk In Trigger 1 Trigger 2 TTL Gate / Trig TTL Sync / PPS Sample Clk Ref In Gate A Gate B Sync / PPS A Sync / PPS B Timing Bus TIMING Clock / Sync / Gate / PPS VCXO Ref QDRII+ Clock/Sync QDRII+ QDRII+ option 150 option 155 Ref In XTAL OSC Option 100 VIRTEX-6 LX130T, LX240T, LX365T, SX315T or SX475T QDRII+ 200 MHz -BIT QDRII+ QDRII+ option 0 option 5 Banks 1&2 Banks 3&4 external reference input between 12 and 30 MHz. Together, the baseband amplifiers and the LNA offer a programmable-gain range of more than 80 db. An integrated lowpass filter with variable bandwidth provides bandwidths ranging 4 40 MHz, programmable with 8 bits of resolution. ConvertersC n e e The analog baseband I and Q analog tuner outputs are then applied two Texas Instruments ADS MHz, -bit converters. The digital outputs are delivered in the Virtex-6 for signal processing, data capture or for routing other module resources. I In MAX2112 Ref Out Q 200 MHz -BIT Config 64 MB GC Control 8X x8 P15 12-BIT IC 2 2 Gigabit Serial I/O (option 105) P LVDS 40 (option 104) P14 PMC 42

43 Installed s l l IP Modules u Model l 790: 6 0 L-Band F T uner r with 2-Channel 2 l 2000 MHz z / - The 790 facry-installed functions include two acquisition IP modules. IP modules for either or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facryinstalled functions and enable the 790 operate as a complete turnkey solution without the need develop any IP. Acquisition q u io IP P Modules d e The 790 features two Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data either of the two s or a test signal generar Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. (I) (Q) TEST SIGNAL INPUT MULTIPLEXER PACKING & FLOW PACKING & FLOW Bank 1 META Bank 2 META IP MODULE 1 IP MODULE 2 VIRTEX-6 FLOWA DETAIL INTEACE (supports user installed IP) Bank 1 Bank 2 Bank 3 Bank 4 8X 40 Gigabit Serial I/O 43

44 Model o l 790: 1 9 : L-Band T uner r with h 2-Channel l 2000 MHz A - C Also A Availablei e SpecificationsS e Model U cpci Model x8 PCI Express Model U VPX COTS and rugged Model U cpci Front Panel Analog Signal Input Connecr: Front panel female SSMC Impedance: 50 ohms L-Band Tuner Type: Maxim MAX2112 Input Frequency Range: 925 MHz 2175 MHz Monolithic VCO Phase Noise: -97 dbc/hz at 10 khz Fractional-N PLL Synthesizer: freq VCO = (N.F) x freq REF where integer N = and fractional F is a 20-bit binary value PLL Reference (freq REF ): Front panel SSMC connecr or on-board 27 MHz crystal (Option -100), MHz LNA Gain: 0 65 db, controlled by a programmable 12-bit converter Baseband Amplifier Gain: 0 15 db, in 1 db steps Baseband Low Pass Filter: Cuff frequency programmable 4 40 MHz with 8-bit resolution Dynamic Range: -75 dbm 0 dbm Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz 200 MHz Resolution: bits Sample Clock Sources: On-board timing generar/synthesizer Clock Synthesizer Clock Source: Selectable onboard programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or, for the clock Timing Generar External Clock Input Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Generar Bus: 26-pin front panel connecr LVPECL bus includes, clock/sync/gate/pps inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Input Quantity: 2 Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, XC6VLX365T, XC6VSX315T, or XC6VSX475T Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option -105: Installs the P connecr configurable as one 8X or two gigabit serial links the Option 150 or 0: Two 8 MB QDRII+ memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard module, 2.91 in. x 5.87 in. 44

45 Performance Graphs Performance: Models 720, 71720, 721, 760,71760, 761, 762 Spurious Free Dynamic Range Spurious Pick-up f in = 70 MHz, f s = 200 MHz, Internal Clock Two-Tone SFDR f s = 200 MHz, Internal Clock Two-Tone SFDR f 1 = 30 MHz, f 2 = 70 MHz, f s = 200 MHz Adjacent Channel Crosstalk Crosstalk f 1 = 69 MHz, f 2 = 71 MHz, f s = 200 MHz Input Frequency Response f in Ch2 = 70 MHz, f s = 200 MHz, Ch 1 shown f s = 200 MHz, Internal Clock Performance: Models 720, 721 Spurious Free Dynamic Range Spurious Free Dynamic Range f out = 70 MHz, f s = 200 MHz, Internal Clock f out = 120 MHz, f s = 400 MHz, External Clock 45

46 Model l 711: 1 1 : Quad Serial S e FPDP P Interface I e r - C Model 711 is a member of the Cobalt family of high performance modules based on the Xilinx Virtex-6. A multichannel, gigabit serial interface, it is ideal for interfacing serial FPDP data converter boards or as a chassis--chassis data link. The 711 is fully compatible with the VITA 17.1 Serial FPDP specification. Its built-in data transfer features make it a complete turnkey solution. For users who require application-specific functions, the 711 serves as a flexible platform for developing and deploying cusm processing IP. In addition supporting PCI Express as a native interface, the Model 711 includes a general-purpose connecr for application-specific I/O. Serial e a l FPDP P InterfaceI t The 711 is fully compatible with the VITA 17.1 Serial FPDP specification. With the capability support , 2.125, 2.5, 3.125, and 4.25 Gbaud link rates and the option for multimode and single-mode optical interfaces, the board can work in virtually any system. Programmable modes include: flow control in both receive and transmit directions, CRC support, and copy/loop modes. Featuresa r Complete serial FPDP solution Fully compliant with VITA 17.1 specification Up 2 GB of PCI Express interface up x8 LVDS connections the Virtex-6 for cusm I/O CH 1 CH 2 CH 3 CH 4 RX TX RX TX RX TX RX TX FIBER OPTIC TRANSCEIVER FIBER OPTIC TRANSCEIVER FIBER OPTIC TRANSCEIVER FIBER OPTIC TRANSCEIVER Contact Pentek for availability of rugged and conduction-cooled versions VIRTEX-6 LX240T, LX365T, SX315T or SX475T LVDS Banks1&2 Banks3&4 option 155 option 5 Config 64 MB 8X x8 40 (option 104) P15 P14 PMC 46

47 Model o l 711: 1 : Quad Serial S e FPDP P Interface e - C Also o A vailablea b Model x8 PCI Express Model U VPX COTS and rugged Installed n t l l d IP I Modules o u l s Four identical serial FPDP interfaces are installed in the. The interfaces are fully compatible with the VITA 17.1 serial FPDP specification. Each interface includes a serial FPDP TX and a serial FPDP RX engine. These are enhanced with DMA engines for efficient transfers and the board. p c icat n Specifications Front Panel Serial FPDP Inputs/Outputs Fiber Optic Connecr Type: LC Laser: 850 nm (standard, other options available) Copper Connecr Type: Micro Twinax Fiber Optic or Copper Link Rates: , 2.125, 2.5, or 4.25 Gbaud (copper rate depends on cable langth) Fiber Optic or Copper Data Transfer Rates: 105, 210, 247, 309 or 420 MB/sec (depending on link rate) per serial FPDP port Field Programmable Gate Array: Xilinx Virtex-6 XC6VLX240T, XC6VLX365T, XC6VSX315T, or XC6VSX475T Cusm I/O Option -104: Installs the PMC P14 connecr with 20 LVDS pairs the Option 155 or 5: Two memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Std module, 2.91 in. x 5.87 in. optional buffer SERIAL FPDP RX ENGINE CH 1 RX PACKET DECONSTRUCT OPTIONAL CRC CHECK 2K x 32 RX FIFO 32K x 32 FIFO Model U cpci Model U cpci CH 1 TX DISPARITY CALCULATE M U X SERIAL FPDP TX ENGINE OPTIONAL CRC 64 x 32 COPY MODE RX FIFO PACKET CONSTRUCT RATE BALANCE IDLE INSERT/DELETE 2K x 32 TX FIFO Copy mode data path K x 32 FIFO SERIAL FPDP CHANNEL 1 optional buffer INTEACE 8X RX CH 2 TX SERIAL FPDP CHANNEL 2 RX CH 3 SERIAL FPDP CHANNEL 3 TX RX CH 4 SERIAL FPDP CHANNEL 4 TX optional buffer optional buffer VIRTEX-6 FLOW DETAIL 47

48 Complementary Products Model l 7192: 1 2 High-Speed e e d Synchronizer nize and Distribution t r ion Board - PMC/P C C Featuresa r Synchronizes up four separate high-speed Cobalt or Onyx I/O modules Synchronizes sampling and data acquisition for multichannel systems Synchronizes gating and triggering functions Clock rates up 1.8 GHz Front panel MMCX connecrs for input signals Front panel µsync connecrs compatible with a range of Pentek Cobalt and Onyx modules The Model 7192 High-Speed Synchronizer and Distribution Board synchronizes multiple Pentek Cobalt or Onyx modules within a system. It enables synchronous sampling and timing for a wide range of multichannel high-speed data acquisition, DSP, and software radio applications. Up four modules can be synchronized using the 7192, with each receiving a common clock along with timing signals that can be used for synchronizing, triggering and gating functions. Input n p SignalsS n Model 7192 provides three front panel MMCX connecrs accept input signals external sources: one for clock, one for gate or trigger and one for a synchronization signal. Clock signals can be applied an external source such as a high performance sine-wave generar. Gate/trigger and sync signals can come an external system source. In addition the MMCX connecr, a reference clock can be accepted through the first front panel µsync output connecr, allowing a single Cobalt or Onyx board generate the clock for all subsequent boards in the system. Sample Clk / Reference Clk In PROGRAMMABLE VCXO Clk In Ref In PLL & DIVIDER :N N Output t Signals S g n s The 7192 provides four front panel µsync output connecrs, compatible with a range of high-speed Pentek Cobalt and Onyx modules. The µsync signals include a reference clock, gate/ trigger and sync signals and are distributed through matched cables, simplifying system design. Clock Signals S g s The 7192 can accept a user supplied external clock on its front panel MMCX connecr. As an alternative the external clock, the 7192 can use its on-board VCXO (programmable voltage-controlled crystal oscillar) as the clock source. The VCXO can operate alone or be locked a system reference clock signal delivered the front panel reference clock input. The external or onboard clock can operate at full rate or be divided and used register all sync and gate/trigger signals as well as providing a reference clock all connected modules. In addition, the clock is available at the Clock Out MMCX as a sample or reference clock for other boards in the system. TWSI Clock / Calibration Out Sync 1 Reference Clk In * TWSI Control In Gate / Trigger Out Sync Out Reference Clk Out Sync 2 Gate / Trigger In Sync In Clk/ Ref In Trig/ Gate In Sync In BUFFER & PROGRAM DELAYS Sync 3 Sync 4 Gate / Trigger Out Sync Out Reference Clk Out Gate / Trigger Out Sync Out Reference Clk Out * For 740 calibration Gate / Trigger Out Sync Out Reference Clk Out 48

49 Complementary Products Model o l 7192: 1 2 High-Speed d Synchronizer y and Distribution D t r i ion Board o d - PMC/ C X C Also o A vailable a b Model U cpci Model 7892 x8 PCI Express Model U VPX COTS and rugged Model U cpci Gate t and n Synchronization y c r n t n Signals The 7192 features separate inputs for gate/trigger and sync signals. A programmable delay allows the user make timing adjustments on the gate/trigger and sync signals before they are sent buffers for output through the µsync output connecrs. Calibrationa t n The 7192 features a calibration output specifically designed work with the Models 740 or GHz modules and provide a signal reference for phase adjustment across multiple s. Programmingg ra The 7192 allows programming of operating parameters including: VCXO frequency, clock dividers, and delays that allow the user make timing adjustments on the gate and sync signals. These adjustments are made before they are sent buffers for output through the µsync connecrs. The 7192 is programmed via a TWSI control interface on the first µsync connecr. The control interface is compatible with the front panel µsync connecrs of all high-speed Cobalt and Onyx modules, thereby providing a single cable connection that carries both control and timing signals. Supported u o e Productsd u t The 7192 supports all high-speed models in the Cobalt family including the GHz and, the GHz and the 770 Four-channel 1.25 GHz, -bit. The 7192 will also support high-speed models in the Onyx family as they become available. Specifications c i a io Front Panel Sample Clock/Reference Input Connecr Type: MMCX Input Impedance: 50 ohms Input Level: 0 dbm +10 dbm, sine wave Sample Clock Frequency: 100 MHz 2 GHz Reference Frequency: MHz Front Panel Gate/Trigger & Sync Inputs Connecr Type: MMCX Input Level: LVTTL Front Panel µsync Inputs/Outputs Quantity: 4 Connecr Type: 19-pin µhdmi Signal Level: CML Signals (µsync connecr 1): Reference Clock In, TWSI control In, Reference Clock Out, Gate/Trigger Out, Sync Out Signals (µsync connecrs 2 4): Reference Clock Out, Gate/Trigger Out, Sync Out Front Panel Clock / Calibration Output Connecr Type: MMCX Output Impedance: 50 ohms Output Level: +6 dbm nominal, sine wave Sample Clock Frequency: 100 MHz 1.8 GHz Programmable VCXO: Frequency Ranges: MHz, MHz, and MHz Tuning Resolution: 32 bits Unlocked Accuracy: +20 ppm PLL, Divider & Jitter Cleaner Type: Texas Instruments CDCM7005 Frequency Dividers: 1, 2, 3, 4, 6, 8 and PMC/ Interface: Power only on PMC P1 or P15 Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard PMC module, 2.91 in. x 5.87 in. 49

50 Complementary Products Model l 9192: 1 2 Rack-mount o High-Speed d System y e Synchronizer S n o r Unit Featuresa r Synchronizes up twelve separate high-speed Cobalt or Onyx I/O modules Synchronizes sampling and data acquisition for multichannel systems Synchronizes gating and triggering functions Clock rates up 1.8 GHz Rear panel SMA connecrs for input signals Rear panel µsync connecrs compatible with a range of Pentek Cobalt and Onyx modules The Model 9192 Rack-mount High-Speed System Synchronizer Unit synchronizes multiple Pentek Cobalt or Onyx modules within a system. It enables synchronous sampling and timing for a wide range of multichannel high-speed data acquisition, DSP, and software radio applications. Up twelve boards can be synchronized using the 9192, with each receiving a common clock along with timing signals that can be used for synchronizing, triggering and gating functions. Input n p Signalsn Model 9192 provides four rear panel SMA connecrs accept input signals external sources: two for clock, one for gate or trigger and one for a synchronization signal. Clock signals can be applied an external source such as a high performance sine-wave generar. Gate/trigger and sync signals can come an external system source. In addition the SMA connecr, a External Clk In reference clock can be accepted through the first rear panel µsync output connecr, allowing a single Cobalt or Onyx board generate the clock for all subsequent boards in the system. Output t SignalsS g n s The 9192 provides four rear panel µsync output connecrs, compatible with a range of high-speed Pentek Cobalt and Onyx boards. The µsync signals include a reference clock, gate/ trigger and sync signals and are distributed through matched cables, simplifying system design. Clock Signals S g s The 9192 can accept a user supplied external clock on its rear panel SMA connecr. As an alternative the external clock, the 9192 can use its onboard VCXO (programmable voltage controlled crystal oscillar) as the clock source. The VCXO can operate Sample Clk / Reference Clk In USB USB-TO-TWSI INTEACE PROGRAMMABLE VCXO Clk In Ref In PLL & DIVIDER :N :N CLOCK SPLITTER TWSI Clock Out 1 Sync 1 Reference Clk In * TWSI Control In Gate / Trigger Out Sync Out Reference Clk Out Sync 2 Clock Out 2 Clock Out 3 through Clock Out 11 Clock Out 12 Gate / Trigger In Sync In Clk Ref In Trig/ Gate In Sync In BUFFER & PROGRAM DELAYS Gate / Trigger Out Sync Out Reference Clk Out Sync 3 through Sync 11 Sync 12 * For 740 calibration Gate / Trigger Out Sync Out Reference Clk Out 50

51 Complementary Products Model d e 9192: 9 9 : Rack-mount k High-Speed h e System s Synchronizer y ni Unit alone or be locked a system reference clock signal delivered the rear panel reference clock input. The on-board or external clock can operate at full rate or can be divided and used register all sync and gate/ trigger signals as well as providing a reference clock all connected boards. In addition, the clock is available at twelve Clock Out SMAs as a sample or reference clock for other boards in the system. Gate t a and Synchronization y c r n t n Signals The 9192 features separate inputs for gate/trigger and sync signals. A programmable delay allows the user make timing adjustments on the gate/trigger and sync signals before they are sent buffers for output through the µsync output connecrs. Calibrationa t n The 9192 features twelve calibration outputs specifically designed work with the 740 or GHz board and provide a signal reference for phase adjustment across multiple s. Programmingg ra n The 9192 allows programming of operation parameters including: VCXO frequency, clock dividers, and delays that allow the user make timing adjustments on the gate and sync signals. These adjustments are made before they are sent buffers for output through the µsync connecrs. The 9192 is programmed via a rear panel USB connecr or a TWSI control interface on the first µsync connecr. The control interface is compatible with the front panel µsync connecrs of all high-speed Cobalt and Onyx modules, thereby providing a single cable connection that carries both control and timing signals. Supported u o e Productsd u t The 9192 supports all high-speed models in the Cobalt family including the GHz and, the GHz and the 770 Four-channel 1.25 GHz, -bit. The 9192 will also support high-speed models in the Onyx family as they become available. Specifications c i a io Front Panel Sample Clock/Reference Input Connecr Type: SMA Input Impedance: 50 ohms Input Level: 0 dbm +10 dbm, sine wave Sample Clock Frequency: 100 MHz 2 GHz Reference Frequency: MHz Rear Panel Gate/Trigger & Sync Inputs Connecr Type: SMA Input Level: LVTTL Rear Panel µsync Inputs/Outputs Quantity: 12 Connecr Type: 19-pin µhdmi Signal Level: CML Signals (µsync connecr 1): Reference Clock In, TWSI control In, Reference Clock Out, Gate/Trigger Out, Sync Out Signals (µsync connecrs 2-12): Reference Clock Out, Gate/Trigger Out, Sync Out Rear Panel Clock / Calibration Outputs Quantity: 12 Connecr Type: SMA Output Impedance: 50 ohms Output Level: +6 dbm nominal at 1400 MHz, sine wave Sample Clock Frequency: 100 MHz 1.8 GHz Programmable VCXO: Frequency Ranges: MHz, MHz, and MHz Tuning Resolution: 32 bits Unlocked Accuracy: +20 ppm PLL, Divider & Jitter Cleaner Type: Texas Instruments CDCM7005 Frequency Dividers: 1, 2, 3, 4, 6, 8 and Power: 120VAC Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Standard 1U Rack-mount, 19 in. x 1.75 in. 51

52 Complementary Products Model l 7893: 8 3 System S t e Synchronizer r and Distribution i r ib Board o - I e Model 7893 System Synchronizer and Distribution Board synchronizes multiple Pentek Cobalt and Onyx boards within a system. It enables synchronous sampling, playback and timing for a wide range of multichannel high-speed data acquisition, DSP and software radio applications. Up eight boards can be synchronized using the 7893, each receiving a common clock up 800 MHz along with timing signals that can be used for synchronizing, triggering and gating functions. For larger systems, up eight 7893 s can be linked gether provide synchronization for up 64 Cobalt or Onyx boards. single Cobalt or Onyx board generate the timing and clock signals for the 7893 for distribution of up eight additional boards. This input can also be used link multiple 7893 s for larger systems. Output t Signals S g n s The 7893 provides eight timing bus output connecrs for distributing all needed timing and clock signals the front panels of Cobalt and Onyx boards via ribbon cables. The 7893 locks the Gate/Trigger and Sync/PPS signals the system s sample clock. The 7893 also provides four front panel SMA connecrs for distributing sample clocks other boards in the system. Featuresa r Synchronizes up eight separate Cobalt or Onyx boards Up eight 7893s can be linked gether synchronize up 64 boards Synchronizes sampling, data acquisition and playback for multichannel systems Synchronizes gating and triggering functions Onboard programmable sample clock generar Output clock rates up 800 MHz Front panel SMA connecrs for TTL input signals and clock outputs Single-slot format Input p Signalsa The Model 7893 provides four front panel SMA connecrs accept LVTTL input signals external sources: two for Sync/PPS and one for Gate/Trigger. In addition the synchronization signals, a front panel SMA connecr accepts sample clocks up 800 MHz or, in an alternate mode, accepts a 10 MHz reference clock lock an onboard VCXO sample clock source. The 7893 also accepts the 26-pin Timing Bus connecr used on Cobalt and Onyx boards. This input allows a Sample C k / Reference Clk In Sample Clk A Sample Clk B Gate / Trig A Gate / Trig B Sync / PPS A Sync / PPS B Timing Bus In USB USB INTEACE N CLK IN PLL & DIVIDER N : N N N REF CLK IN Control USB Gate / Trig USB Sync / PPS VOLTAGE PROGRAM VCXO Clock Signals S g s The 7893 can accept a clock either the front panel SMA connecr or the timing bus input connecr. In addition, the board is equipped with a programmable onboard VCXO clock generar which can free run or be locked a user supplied, 10 MHz, typical, system reference. In all cases, the sample clock can be divided by 1, 2, 4, 8 or prior distribution the Clock Out SMAs or the timing bus output connecrs. Sample Clk A Sample Clk B Sample C k A Sample C k B Clock Out 1 Clock Out 2 Clock Out 3 Clock Out 4 Timing Bus Out 1 Sample C k A Sample Clk B Gate / Trig A Gate / Trig B Sync / PPS A Sync / PPS B TTL Gate / Trig In USB Gate / Trig Gate / Trig A Gate / Trig B BUFFER & PROGRAM DELAYS Timing Bus Out 2 through Timing Bus Out 7 TTL Sync / PPS A In TTL Sync / PPS B In USB Sync / PPS Sync / PPS A Sync / PPS B Timing Bus Out 8 Sample C k A Sample Clk B Gate / Trig A Gate / Trig B Sync / PPS A Sync / PPS B 52

53 Complementary Products Model 7893: 7 9 : System y s e Synchronizer S r and Distribution t ibuti i Board B r d - USB Interface e c The 7893 is programmed via a USB interface. In addition status and control, the USB interface can be used generate Gate/Trigger and Sync/PPS signals for distribution all connected boards. Physical y i a Characteristicsa a e ic The 7893 is a single-slot size board which can be mounted in any PCI or slot. The board receives power a standard six-pin power connecr and uses the PCI or slot solely for physical mounting, with no electrical connections. Supported u o e Productsd The 7893 supports a wide range of products in the Cobalt family including the and three-channel, 200 MHz transceivers, the and two-channel, 500 MHz transceivers, the 78660, and four-channel 200 MHz s, and the L-Band Tuner. The 7893 also supports the Onyx four-channel 200 MHz and will support all complementary models in the Onyx family as they become available. Specifications p c ica io Sample Clock/Reference Clock Input Type: Front panel female SMC connecr Signal: Sine wave, dbm, AC-coupled, 50 ohms, accepts MHz sample clock or MHz PLL system reference, typically 10 MHz TTL Gate/Trigger Input Type: Front panel female SMC connecr Signal: LVTTL Function: Programmable functions include gate and trigger TTL Sync/PPS Input A Type: Front panel female SMC connecr Signal: LVTTL Function: Programmable functions include sync and PPS TTL Sync/PPS Input B Type: Front panel female SMC connecr Signal: LVTTL Function: Programmable functions include sync and PPS Timing Bus In Type: One rear 26-pin connecr Signals: LVPECL bus includes: Sample Clock A & B In, Gate/Trigger A & B In, and Sync/PPS A & B In Clock Synthesizer Clock Source: Selectable onboard programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference (front panel Reference Clock Input), typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for each of five on-board clock buses. Sample Clock Output Type: Four front panel female SMC connecrs, each can be independently divided Output Level: +9 dbm, nominal, sine wave Timing Bus Out Type: Eight rear 26-pin connecrs Signals: LVPECL bus includes: Sample Clock A & B Out, Gate/Trigger A & B Out, and Sync/PPS A & B Out Control: Rear USB input for connecting motherboard on-board USB 8-pin header Power: Rear 8-pin connecr compatible with power connecrs Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncond. Size: Half-length card, 4.38 in. x 7.13 in. 53

54 Coming Soon! Model o l 71750: 1 5 : T ransceiver a r with t h T wo s, A, DUC,, Two T wo s / s - C Featuresa r In In Out Out Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT s Two 500 MHz 12-bit s One digital upconverter Two 800 MHz -bit s 4 GB of Sample clock synchronization an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1, 2, and 3) interface up x8 Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-7 for cusm I/O Sample Clk / Reference Clk In TTL PPS/Gate/Sync TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate Gate Sync / PPS Sync / PPS Timing Bus TIMING BUS Clock / Sync / Gate / PPS VCXO CONFIG Clock/Sync Bus Clock/Sync Bus Config Bus 500 MHz 12-BIT GATEXPRESS CONFIGURATION MANAGER Gen. 3 x8 Gen. 3 x8 P MHz 12-BIT VIRTEX-7 VX330T, VX485T or VX690T Gigabit Serial I/O (option 105) P LVDS (option 104) P14 PMC 800 MHz 800 MHz -BIT -BIT DIGITAL UPCONVERTER Model o l GHz or 1.8 GHz, 12-bit 2 - b with h DDCs D s and Beamformer err - C In In Featuresa r Ideal radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT s One-channel mode with 3.6 GHz, 12-bit Two-channel mode with 1.8 GHz, 12-bit s 2 GB of Sync bus for multimodule synchronization PCI Express Gen. 2 interface x8 Optional user-configurable gigabit serial interface Optional LVDS connections the Virtex-6 for cusm I/O Sample Clk TTL PPS/Gate/Sync TIMING BUS Clock/Sync Bus 3.6 GHz (1 Channel) or Gate In Reset In Clock / Sync / Gate / PPS 1.8 GHz (2 Channel) 12-Bit Ref Clk In Ref Clk Out Sync Bus VIRTEX-6 LX130T, LX240T, LX365T, SX315T or SX475T Banks 1&2 Banks 3&4 Config 64 MB 8X x8 P15 Gigabit Serial I/O (option 105) P LVDS 40 (option 104) P14 PMC 54

55 Cusmer Information Placing an Order When placing purchase orders for Pentek products, please provide the model numbers and descriptions used in this catalog. You may place your orders by letter, telephone, or fax; you should confirm a verbal order by mail, or fax. All orders should specify a purchase order number, bill and ship- address, method of shipment, and a contact name and telephone number. U.S. orders should be made out Pentek, Inc. and may be placed directly at our office address, or c/o our authorized sales representative in your area. International orders may be placed with us, or with our authorized distribur in your country. They have pricing and availability information and they will be pleased assist you. Prices and Price Quotations All prices are F.O.B. facry in U.S. dollars. Shipping charges and applicable import, federal, state or local taxes, are paid by the purchaser. We re glad respond your request for price quotation just contact the corporate office, or your local representative. Price and delivery quotations are valid for 30 days, unless otherwise stated. Quantity discounts for large orders are available and will be included in our price quotation, if applicable. Terms Terms are Net 30 days for accounts with established credit; until credit is established, we require prepayment, or will ship C.O.D. Shipping For new orders, we normally ship UPS ground with shipping charges prepaid and added our invoice. If you are in a hurry, we will ship UPS Red, UPS Blue, FedEx, or the carrier of your choice, as you request. Order Cancellation and Returns All orders placed with Pentek are considered binding and are subject cancellation charges. Hardware products included in this catalog may be returned within 30 days after receipt, subject a rescking charge. Before returning a product, please call Cusmer Service obtain a Return Material Authorization (RMA) number. Software purchases are final and we cannot allow returns. Warranty Pentek warrants its products conform published specifications and be free defects in materials and workmanship for a period of one year the date of delivery, when used under normal operating conditions and within the service conditions for which they were furnished. The obligation of Pentek arising a warranty claim shall be limited repairing or, optionally, replacing without charge any product which proves be defective within the term and scope of the warranty. Pentek must be notified of the defect or nonconformity within the warranty period. The affected product must be returned with shipping charges and insurance prepaid. Pentek will pay shipping charges for the return of product buyer, except for products returned outside of the USA. Limitations of Warranty This warranty does not apply products which have been repaired or altered by anyone other than Pentek or its authorized representatives. The warranty does not extend products that have been damaged by misuse, neglect, improper installation, unauthorized modification, or extreme environmental conditions. Pentek specifically disclaims merchantability or fitness for a particular purpose. We will not be held liable for incidental or consequential damages arising the sale, use, or installation of any of our products. Under any circumstances Pentek s liability under this warranty will not exceed the purchase price of the product. Extended Warranty You may purchase an extended warranty on our hardware products for a fee of 1% of the list price per month of coverage, or 10% of the list price per year of coverage. All Pentek software products (excluding 3rd-party products) include free maintenance and free upgrades for one year. Extended software maintenance is available for one, two, and three years, starting after the first year. Service vice and Repair Before returning a product for service and repair, please contact Cusmer Service obtain a Return Material Authorization (RMA) number and have the following information available: model number, serial number, name and address of person returning the product and a description of the problem experienced. Carefully package the product in its original antistatic material, if it is still available, and ship it us: prepaid (if within the US) or free domicile DDP (if outside the US). Show the RMA number on the outside of the package and include a written description of the malfunction. When the work is completed, we will return the product you free of charge, along with a statement of work done, if under warranty. Out-of-warranty work will be charged on a material and service time basis, and we will be happy quote you a cost estimate for the repair and return shipping before proceeding. Copyright 2011, 2012 Pentek, Inc. All rights reserved. Contents of this publication may not be reproduced without written permission. Specifications and prices are subject change without notice. Pentek, ReadyFlow, GateFlow, SystemFlow, Cobalt and Onyx are tradenmarks or registered trademarks of Pentek, Inc. Other trademarks are properties of their respective owners. Printed in U.S.A. Worldwide distribution and support T-Cobalt/Onyx

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