FEATURES DESCRIPTIO. LTC1421/LTC Hot Swap Controller APPLICATIO S TYPICAL APPLICATIO

Transcription

1 LTC/LTC-. Hot Swap Controller FEATURES Allows Safe Board Insertion and Removal from a Live Backplane System Reset and Power Good Control Outputs Programmable Electronic Circuit Breaker User Programmable Supply Voltage Power-Up Rate High Side Driver for Two External N-Channels Controls Supply Voltages from V to V Connection Inputs Detect Board Insertion or Removal Undervoltage Lockout Power-On Reset Input APPLICATIO S U Hot Board Insertion Electronic Circuit Breaker, LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. DESCRIPTIO U The LTC /LTC-. are Hot Swap TM controllers that allow a board to be safely inserted and removed from a live backplane. Using external N-channel pass transistors, the board supply voltages can be ramped up at a programmable rate. Two high side switch drivers control the N- channel gates for supply voltages ranging from V to V. A programmable electronic circuit breaker protects against shorts. Warning signals indicate that the circuit breaker has tripped, a power failure has occurred or that the switch drivers are turned off. The reset output can be used to generate a system reset when the power cycles or a fault occurs. The two connect inputs can be used with staggered connector pins to indicate board insertion or removal. The power-on reset input can be used to cycle the board power or clear the circuit breaker. The trip point of the ground sense comparator is set at 0.V for LTC and. for LTC-.. The LTC/LTC-. are available in -pin SO and SSOP packages. TYPICAL APPLICATIO U V EE V DD FAULT POR GND DATA BUS STAGGERED CONNECTOR R k D C µf CON AUX FAULT POR CON R 0.00Ω SETLO GATELO V OUTLO HI GND Q MTB0N0E 0 LTC DISABLE R 0.0Ω 9 BEA BEB GND QS QuickSwitch C 0.µF Q / Si9DY 0k SETHI GATEHI V OUTHI RAMP CPON COMP COMP REF FB COMPOUT PWRGD C 0.µF 0 9 Q / Si9DY R 0k % µf DATA BUS R k % R 0k % R.k % QuickSwitch IS A REGISTERED TRADEMARK OF QUALITY SEMICONDUCTOR CORPORATION. C LOAD C LOAD C LOAD µp I/O I/O TA0 V EE V A V DD V A A BACKPLANE PC BOARD

2 LTC/LTC-. ABSOLUTE MAXIMUM RATINGS (Note ) W W W Supply Voltage (, HI, AUX )....V Input Voltage (Analog Pins)... 0.V to (HI 0.V) Input Voltage (Digital Pins)... 0.V to.v Output Voltage (Digital Pins).. 0.V to ( 0.V) Output Voltage (CPON)....V to ( 0.V) Output Voltage (V OUTLO, V OUTHI )... 0.V to.v Output Voltage (GATELO, GATEHI)... 0.V to 0V Operating Temperature Range LTCC... 0 C to 0 C LTCI... 0 C to C Storage Temperature Range... C to 0 C Lead Temperature (Soldering, 0 sec) C U PACKAGE/ORDER I FOR CON CON POR FAULT DISABLE PWRGD REF CPON 9 RAMP 0 FB GND TOP VIEW AUX SETLO GATELO 0 V OUTLO 9 HI SETHI GATEHI V OUTHI COMPOUT COMP COMP W U ATIO ORDER PART NUMBER U LTCCG LTCCSW LTCCG-. LTCCSW-. LTCIG LTCISW LTCIG-. LTCISW-. G PACKAGE -LEAD PLASTIC SSOP SW PACKAGE -LEAD PLASTIC SO T JMAX = C, θ JA = 00 C/W (G) T JMAX = C, θ JA = C/W (SW) Consult factory for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. HI = V, = unless otherwise noted (Note ). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DC Characteristics I CCLO Supply Current CON = CON = GND, POR =. ma I CCHI HI Supply Current CON = CON = GND, POR = 0. ma V LKO Undervoltage Lockout and HI...0 V V LKH Undervoltage Lockout Hysteresis and HI 00 mv V REF Reference Output Voltage No Load.0.. V V LNR Reference Line Regulation V V, No Load mv V LDR Reference Load Regulation I O = 0mA to ma, Sourcing Only mv I RSC Reference Short-Circuit Current V REF = 0V ma V COF Comparator Offset Voltage 0V V CM (.V) ±0 mv V CPSR Comparator Power Supply Rejection 0V V CM (.V), V V mv/v V CHST Comparator Hysteresis 0V V CM (.V) mv V RST Reset Voltage Threshold (V OUTLO ) FB = V OUTLO V FB = Floating.0.. V FB = GND...0 V V RHST Reset Threshold Hysteresis (V OUTLO ) FB = V OUTLO mv FB = Floating mv FB = GND mv R FB FB Pin Input Resistance 0V V FB 9 kω V CB Circuit Breaker Trip Voltage V CB = ( V SETLO ) or V CB = (HI V SETHI ) mv V TRIP Output Voltage for Re-Power-Up LTC (Note ) 0. V LTC-. (Note ). V

3 LTC/LTC-. ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. HI = V, = unless otherwise noted (Note ). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I RAMP RAMP Pin Output Current Charge Pump On, V RAMP = 0.V µa I CP Charge Pump Output Current Charge Pump On, GATEHI = 0V 00 µa GATELO = 0V 00 µa V GATEHI GATEHI N-Channel Gate Drive V GATEHI V OUTHI V V GATELO GATELO N-Channel Gate Drive V GATELO V OUTLO 0 V V AUXVCC Auxiliary Output Voltage =, Unloaded. V V IL Input Low Voltage CON, CON, POR 0. V V IH Input High Voltage CON, CON, POR V I IN Input Current CON, CON, POR = GND µa V OL Output Low Voltage, COMPOUT, PWRGD, DISABLE, FAULT, 0. V I O = ma CPON, I O = ma. V V OH Output High Voltage DISABLE, I O = ma V CPON, I O = ma. V I PU Logic Output Pull-Up Current, PWRGD, FAULT = GND µa AC CHARACTERISTICS t CON or CON to CPON Figure, C L = pf 0 0 ms t PWRGD to Figure, R L = 0k to, C L = pf ms ms t PWRGD to DISABLE Figure, C L = pf ms ms t POR to CPON Figure, C L = pf 0 0 ms t PWRGD to Figure, R L = 0k to, C L = pf µs t POR to CPON Figure, C L = pf 0 ns t CON or CON to CPON Figure, C L = pf 0 ns t 9 Short-Circuit Detect to FAULT Figure, R L = 0k to, C L = pf 0 µs SETLO = 0mV to 00mV t 0 Short-Circuit Detect to CPON Figure, C L = pf 0 µs SETLO = 0mV to 00mV t POR to FAULT Figure, R L = 0k to, C L = pf 0 ns t CHL Comparator High to Low COMP =.V, 0mV Overdrive µs R L = 0k to, C L = pf t CLH Comparator Low to High COMP =.V, 0mV Overdrive. µs R L = 0k to, C L = pf Note : Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note : All currents into device pins are positive; all currents out of device pins are negative. All voltages are reference to ground unless otherwise specified. Note : After power-on reset, the V OUTLO and V OUTHI have to drop below the V TRIP point before the charge pump is restarted. Note : After power-on reset, the V OUTLO has to drop below the V TRIP point before the charge pump is restarted.

4 LTC/LTC-. TYPICAL PERFORMANCE CHARACTERISTICS U W Reference Voltage vs Temperature Gate Voltage vs Temperature Reference Voltage vs Source Current REFERENCE VOLTAGE (V) = HI = V GATE VOLTAGE (V) 0 9 = HI = V GATEHI GATELO REFERENCE VOLTAGE (V) = HI = V TEMPERATURE ( C) TEMPERATURE ( C) SOURCE CURRENT (ma) G0 G0 G0 GATELO Voltage vs Voltage GATEHI Voltage vs HI Voltage I CCLO Supply Current vs Temperature GATELO VOLTAGE (V) 0 HI = V GATEHI VOLTAGE (V) 0 = ICCLO SUPPLY CURRENT (µa) = HI = V 0 0 VOLTAGE (V) 0 0 HI VOLTAGE (V) TEMPERATURE ( C) G0 G0 G0 I CCHI SUPPLY CURRENT (µa) I CCHI Supply Current vs Temperature = HI = V VOLTAGE (mv) V OL vs I SINK = HI = V COMPOUT PWRGD FAULT CPON VOLTAGE (V) CPON Voltage vs Sink Current (Charge Pump Off) = HI = V TEMPERATURE ( C) 0 0 SINK CURRENT (ma) SINK CURRENT (ma)..0 G0 G0 G09

5 LTC/LTC-. TYPICAL PERFORMANCE CHARACTERISTICS U W CPON VOLTAGE (V) CPON Voltage vs Source Current (Charge Pump On) = HI = V ICCLO SUPPLY CURRENT (ma) I CCLO Supply Current vs Voltage HI = V SOURCE CURRENT (ma) VOLTAGE (V) G0 G PIN FUNCTIONS U U U CON (Pin ): TTL Level Input with a Pull-Up to. Together with CON, it is used to indicate board connection. The pin must be tied to ground on the host side of the connector. When using staggered connector pins, CON and CON must be the shortest and must be placed at opposite corners of the connector. Board insertion is assumed after CON and CON are both held low for 0ms after power-up. CON (Pin ): TTL Level Input with a Pull-Up to. Together with CON it is used to indicate board connection. POR (Pin ): TTL Level Input with a Pull-Up to. When the pin is pulled low for at least 0ms, a hard reset is generated. Both V OUTLO and V OUTHI will turn off at a controlled rate. A power-up sequence will not start until the POR pin is pulled high. If POR is pulled high before V OUTLO and V OUTHI are fully discharged, a power-up sequence will not begin until the voltage at V OUTLO and V OUTHI are below V TRIP. The electronic circuit breaker will be reset by pulling POR low. FAULT (Pin ): Open Drain Output to GND with a Weak Pull-Up to. The pin is pulled low when an overcurrent fault is detected at V OUTLO or V OUTHI. DISABLE (Pin ): CMOS Output. The signal is used to disable the board s data bus during insertion or removal. PWRGD (Pin ): Open Drain Output to GND with a Weak Pull-Up to. The pin is pulled low immediately after V OUTLO falls below its reset threshold voltage. The pin is pulled high immediately after V OUTLO rises above its reset threshold voltage. (Pin ): Open Drain Output to GND with a Weak Pull-Up to. The pin is pulled low when a reset condition is detected. A reset will be generated when any of the following conditions are met: Either CON or CON is high, POR is pulled low, or HI are below their respective undervoltage lockout thresholds, PWRGD goes low or an overcurrent fault is detected at V OUTLO or V OUTHI. will go high 00ms after PWRGD goes high. On power failure, will go low µs after PWRGD goes low. REF (Pin ): The Reference Voltage Output. V OUT =.V ±%. The reference can source up to ma of current. A µf bypass capacitor is recommended. CPON (Pin 9): CMOS Output That Can Be Pulled Below Ground. CPON is pulled high when the internal charge pumps for GATELO and GATEHI are turned on. CPON is pulled low when the charge pumps are turned off. The pin can be used to control an external MOSFET for a to V supply.

6 LTC/LTC-. PIN FUNCTIONS U U U RAMP (Pin 0): Analog Power-Up Ramp Control Pin. By connecting an external capacitor between the RAMP and GATEHI, a positive linear voltage ramp on GATEHI and GATELO is generated on power-up with a slope equal to 0µA/C RAMP. A 0k resistor in series with the capacitor enhances the ESD performance at the GATEHI pin. FB (Pin ): Analog Feedback Input. FB is used to set the reset threshold voltage on. For a supply leave FB floating. For a.v supply, short FB to. GND (Pin ): Ground COMP (Pin ): Noninverting Comparator Input. COMP (Pin ): Inverting Comparator Input. COMPOUT (Pin ): Open Drain Comparator Output. V OUTHI (Pin ): High Supply Voltage Output. This must be the higher of the two supply voltage outputs. GATEHI (Pin ): The High Side Gate Drive for the High Supply N-Channel. An internal charge pump guarantees at least V of gate drive. The slope of the voltage rise at GATEHI is set by the external capacitor connected between GATEHI and RAMP. When the circuit breaker trips, GATEHI is immediately pulled to GND. SETHI (Pin ): The Circuit Breaker Set Pin for the High Supply. With a sense resistor placed in the supply path between HI and SETHI, the circuit breaker will trip when the voltage across the resistor exceeds 0mV for more than 0µs. To disable the circuit breaker, HI and SETHI should be shorted together. HI (Pin 9): The Positive Supply Input. This must be the higher of the two input supply voltages. An undervoltage lockout circuit disables the chip until the voltage at HI is greater than.. V OUTLO (Pin 0): Low Supply Voltage Output. This must be the lower of the two supply voltage outputs. GATELO (Pin ): The High Side Gate Drive for the Low Supply N-Channel Pass Transistor. An internal charge pump guarantees at least 0V of gate drive. The slope of the voltage rise at GATELO is set by the external capacitor connected between GATEHI and RAMP. When the circuit breaker trips GATELO is immediately pulled to GND. SETLO (Pin ): The Circuit Breaker Set Pin for the Low Supply. With a sense resistor placed in the supply path between and SETLO, the circuit breaker will trip when the voltage across the resistor exceeds 0mV for more than 0µs. To disable the circuit breaker, and SETLO should be shorted together. (Pin ): The Positive Supply Input. must be equal to or lower voltage than HI. An undervoltage lockout circuit disables the chip until the voltage at is greater than.. AUX (Pin ): The supply input for the GATELO and GATEHI discharge circuitry. Connect a µf capacitor to ground. AUX is powered from via an internal Schottky diode and series resistor.

7 LTC/LTC-. BLOCK DIAGRAM W AUX SETLO HI SETHI GATELO RAMP GATEHI V OUTHI V OUTLO 0mV 0mV AUX CHARGE PUMP N N CP CP CP UNDERVOLTAGE LOCKOUT V TRIP.k CP.k FB 9 CPON.k.V REFERENCE REF FAULT 0µA 0µA PWRGD CON CON POR DISABLE DIGITAL CONTROL TIMING CP 0µA COMPOUT GND COMP COMP BD SWITCHI G TI E WAVEFOR S U W W t t t t t 9 t t t CON SETLO CON FAULT CPON CPON PWRGD PWRGD DISABLE POR F0 POR F0 t 0 t t t t Figure. Nominal Operation Switching Waveforms Figure. Fault Detection Switching

8 LTC/LTC-. Hot Circuit Insertion When circuit boards are inserted into a live backplane, the supply bypass capacitors on the board can draw huge transient currents from the backplane power bus as they charge up. The transient currents can cause permanent damage to the connector pins and cause glitches on the system supply, causing other boards in the system to reset. At the same time, the system data bus can be disrupted when the board s data pins make or break connection. The LTC is designed to turn a board s supply voltages on and off in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. The chip also provides a disable signal for the board s data bus buffer during insertion or removal and provides all the necessary supply supervisory functions for the board. Power Supply Ramping The power supplies on a board are controlled by placing external N-channel pass transistors in the power path (Figure ). R and R provide current fault detection. By ramping the gate of the pass transistor up at a controlled rate, the transient surge current (I = C dv/dt) drawn from the main backplane supply can be limited to a safe value when the board makes connection. V R Q 0 9 SETLO GATELO V OUTLO HI CON LTC RAMP 0 CON R Q SETHI GATEHI V OUTHI Figure : Supply Control Circuitry R RAMP F0 C LOAD C RAMP V OUTHI V OUTLO C LOAD When power is first applied to the chip, the gates of both N-channels, GATELO and GATEHI are pulled low. After the connection sense pins, CON and CON are both held low for at least 0ms, a 0µA reference current is connected from the RAMP pin to GND. The voltage at GATEHI begins to rise with a slope equal to 0µA/C RAMP (Figure ), where C RAMP is an external capacitor connected between the V CPON V 0V B V 0V V EE V ~ms t t Figure. Supplies Turning On ~ms SLOPE = 0µA/C RAMP B R k % 9 Fa V OUTHI V OUTLO RAMP and GATEHI pins. The voltage at the GATEHI pin is clamped one Schottky diode drop below GATELO. The ramp time for each supply is equal to: t = ( ) (C RAMP )/0µA. During power down the gates are actively pulled down by two internal NFETs. A negative supply voltage can be controlled using the CPON pin as shown in Figure. When the board makes connection, the transistor Q is turned off because it s gate is pulled low to V by R. CPON is also pulled to V. When the charge pump is turned on, CPON is pulled to and the gate of Q will ramp up with a time constant determined by R, R and C. When the charge pump is turned off, CPON goes into a high impedance state, the gate of Q is discharged to V EE with a time constant determined by R and C, and Q turns off. V FROM CONNECTOR C 0.0µF Q / MMDFN0HD R 0k % CPON LTC Figure. Negative Supply Control C LOAD V EE V A F0

9 LTC/LTC-. PWRGD and The LTC uses a.v bandgap reference, internal resistive divider and a precision voltage comparator to monitor V OUTLO (Figure ). The reset threshold voltage for V OUTLO is determined by the FB pin connection as summarized in Table. PWRGD Table V OUTLO PWRGD 0µA TIMING 0µA COMP.V Figure. Supply Monitor Block Diagram FEEDBACK PIN µs V OUTLO.k.k.k V OUTLO VOLTAGE Floating. V OUTLO.90V GND.V V V V V V V <µs 00ms <00ms 00ms FB REF F0 When the V OUTLO voltage rises above its reset threshold voltage, the comparator output goes low, and PWRGD is immediately pulled high to by a weak pull-up current source or external resistor (Figure, time points and ). After a 00ms delay, is pulled high. The weak pull-up current source to on PWRGD and have a series diode so the pins can be pulled above by an external pull-up resistor without forcing current back into. V F0 When V OUTLO drops below its reset threshold, the comparator output goes high, and PWRGD is immediately pulled low (time point ). After a µs delay, is pulled low. The delay allows the PWRGD signal to be used as an early warning that a reset is about to occur. If the PWRGD signal is used as a interrupt input to a microprocessor, a short power-down routine can be run before the reset occurs. If V OUTLO rises above the reset threshold for less than 00ms, the PWRGD output will trip, but the output is not affected (time point ). If V OUTLO drops below the reset threshold for less than µs, the PWRGD output will trip, but again the output will not be affected (time point ). Voltage Comparator The uncommitted voltage comparator (COMP) can be used to monitor output voltages other than V OUTLO. Figure a shows how the comparator can be used to monitor a V supply (V OUTHI ), while the supply (V OUTLO ) generates a reset when it dips below.. When the V supply drops below 0.V, COMPOUT will pull low. The FB pin is left floating. Figure b shows how the comparator can be used to monitor the supply (V OUTHI ) while the.v supply (V OUTLO ) generates a reset when it dips below.9v. When the supply drops below., COMPOUT will pull low. The FB pin is tied to V OUTLO. 0µA 0µA TIMING.V COMP 0.k.k COMP LTC.k F0a 0k % V 0k %.k % Figure. Power Monitor Waveforms Figure a. Monitor V, Reset at. 9

10 LTC/LTC-. Figure c shows how the comparator can be used to generate a reset when the V supply (V OUTHI ) drops below 0.V. The supply (V OUTLO ) also generates a reset when it dips below.. When the V supply drops below 0.V, COMPOUT will pull the FB pin low setting the internal threshold voltage for comparator to.v. Since V OUTLO is less than.v, PWRGD immediately goes low and a reset is generated µs later. Figure d shows how the comparator can be used to override the internal reset voltage for a supply on V OUTLO. 0µA 0µA TIMING COMP.V 0.k.k COMP LTC.k 0k % 0k %.k % A.k resistor is tied from the FB pin to V OUTLO, setting the internal threshold to about.9v. The new reset threshold voltage is set by the external resistive divider connected to COMP. When V OUTLO drops below the new threshold, COMPOUT pulls FB to ground, changing the internal threshold at COMP to.v and generating a reset. Finally, the comparator may be used to monitor a negative supply as shown in Figure e. The external resistor divider 0µA 0µA TIMING.V COMP 0.k.k COMP LTC.k F0d.k % V 0k %.k %.V F0b Figure d. Reset at. 0 0µA Figure b. Monitor, Reset.V at.9v 0µA TIMING.V COMP 0.k.k COMP LTC.k F0c V 0k %.k % Figure c. Reset V at 0.V, Reset at. Figure e. Monitor V at 0.V, Reset at. 0µA 0µA TIMING.V COMP 0.k.k COMP LTC.k F0e V V.k % 0k % 0k %

11 LTC/LTC-. is connected between REF (Pin ) and the negative supply and the trip point of Comparator set to GND. Soft Reset Generation A soft reset that doesn t cycle the supply voltage can be generated externally using Pin (FB) as shown in Figure 9. For a supply the FB pin is left floating to set the internal supply monitor trip voltage to.. However, if the FB pin is pulled to ground for more than µs via a push button or open-collector logic gate, the internal trip point will go to.v and the pin will pull low. will remain low for 00ms after the FB pin is released. The signal will also be pulled low when the voltage at the V OUTLO pin dips below. for more than µs. When using a.v supply, a k resistor must be connected from the FB pin to to set the internal trip point to.90v. sense resistor is greater than 0mV for more than 0µs. When the circuit breaker trips, both N-channel MOSFETs are quickly turned off, FAULT and PWRGD go low and is pulled low µs later. FAULT can be connected to a LED or a logic signal back to the host to indicate a faulty board. The chip will remain in the tripped state until a power-on reset is generated, or the power on HI and is cycled. If the circuit breaker feature is not used, short to SETLO and HI to SETHI. If more than 0µs of response time is needed to reject supply noise, an external resistor and capacitor can be added to the sense circuit as shown in Figure 0. R SENSE C F R F Q 0 / LS0 OPEN COLLECTOR.V R k R USED FOR.V SUPPLY ONLY FB SETLO GATELO V OUTLO LTC F0 LTC LOGIC Figure 0. Short-Circuit Protection Circuit FB µs Figure 9. Generating a Soft Reset Undervoltage Lockout On power-up, an undervoltage lockout circuit prevents the GATELO and GATEHI charge pumps from turning on until and HI have both exceeded.. Electronic Circuit Breaker The LTC features an electronic circuit breaker function that protects against short circuits or excessive currents on the supplies. By placing a sense resistor between the supply input and set pin of either supply, the circuit breaker will be tripped whenever the voltage across the GND 00ms F09 Auxiliary When a short circuit occurs on the board, it is possible to draw enough current to cause the backplane supply voltage to collapse. If the input supply voltage collapses to a low enough voltage and the LTC gate drive circuitry is unable to shut off the N-channel pass transistors, the system might freeze up in a permanent short condition. To prevent this from occurring, the gate discharge circuitry inside the LTC is powered from AUX, which is in turn powered from through an internal Schottky diode and current limiting resistor (Figure ). AUX µf 0k GATE DRIVE CIRCUITRY Figure. AUX Circuitry GATELO GATEHI LTC F

12 LTC/LTC-. When collapses, there is enough energy stored on the µf capacitor connected to AUX to keep the gate discharge circuitry alive long enough to fully turn off the external N-channels. DATA BUS CONNECTOR D D OUT Power N-Channel Selection The R DS(ON) of the external pass transistor must be low enough so that the voltage drop across it is about 00mV or less at full current. If the R DS(ON) is too high, the voltage drop across the transistor might cause the output voltage to trip the reset circuit. Table lists the transistors that are recommended for use with the LTC. Table. N-Channel Selection Guide CURRENT PART LEVEL (A) NUMBER MANUFACTURER DESCRIPTION 0 to MMDFN0E ON Semiconductor Dual N-Channel SO- R DS(ON) = 0.Ω to MMDFNOHD ON Semiconductor Dual N-Channel SO- R DS(ON) = 0.09Ω to MTB0N0 ON Semiconductor Single 0A N-Channel DD Pak R DS(ON) = 0.0Ω to 0 MTB0N0E ON Semiconductor Single N-Channel DD Pak R DS(ON) = 0.0Ω 0 to 0 MTBN0HD ON Semiconductor Single N-Channel DD Pak R DS(ON) = 0.009Ω SYSTEM DATA BUS BACKPLANE BOARD F Figure. Typical Logic Gate Loading the Data Bus CONNECTOR DISABLE R 0.00Ω LTC QS Q MTB0N0E 0 GND C LOAD BOARD DATA BUS Data Bus When a board is inserted or removed from the host, care must be given to prevent the system data bus from being corrupted when the data pins make or break contact. One problem is that the fully discharged input or output capacitance of the logic gates on the board will draw an inrush current when the data bus pins first make contact. The inrush current can temporarily corrupt the data bus, but usually will not cause long term damage. The problem can be minimized by insuring the input or output data bus capacitance is kept as small as possible. The second, and more serious problem involves the diodes to at the input and output of most logic families (Figure ). 0 GND F Figure : Buffering the Data Bus With the board initially unpowered, the input to the logic gate is at ground potential. When the data bus pins make contact, the bus line is clamped to ground through the input diode D to. Large amounts of current can flow through the diode and cause the logic gate to latch up and destroy itself when the power is finally applied. This

13 LTC/LTC-. can usually be prevented by using logic that does not include the clamping diodes such as the QSI FCTT family from Quality Semiconductor, or by using a data bus switch such as the 0-bit QS QuickSwitch also from Quality Semiconductor (Tel: ). The QuickSwitch bus switch contains an N-channel placed in series with the data bus. The switch is turned off when the board is inserted and then enabled after the power is stable. The switch inputs and outputs do not have a parasitic diode back to and have very low capacitance. The LTC is designed to work directly with the QuickSwitch bus switch as shown in Figure. The DISABLE signal is connected to the enable pins of the QS, and each switch is placed in series with a data bus signal. When the board is inserted, the DISABLE signal is pulled high, turning off the switches. After the board supply voltage ramps up and goes high, DISABLE will pull low enabling the switches. Board Insertion Timing When the board is inserted, GND pin makes contact first, followed by HI and (Figure, time point ). DISABLE is immediately pulled high, so the data bus switch is disabled. At the same time CON and CON make contact and are shorted to ground on the host side (time point ). Since most boards need to be rocked back and forth to get them in place, there is a period of time when only one side of the connector is making contact. CON and CON should be located at opposite ends of the connector. 0ms 00ms HI DISABLE CON CON CPON GATEHI V OUTHI GATELO V OUTLO V TH PWRGD FAULT POR F Figure. Board Insertion Timing

14 LTC/LTC-. When CON and CON are both forced to ground for more than 0ms, the LTC assumes that the board is fully connected to the host and power-up can begin. When and HI exceed the. undervoltage lockout threshold, the 0µA current reference is connected from RAMP to GND, the charge pumps are turned on and CPON is forced high (time point ). V OUTHI and V OUTLO begin to ramp up. When V OUTLO exceeds the reset threshold voltage, PWRGD will immediately be forced high (time point ). After a 00ms delay, will be pulled high and DISABLE will be pulled low, enabling the data bus (time point ). Ground Sense Comparator When POR is pulled low for more than 0ms, GATELO and GATEHI are pulled to ground and V OUTLO and V OUTHI will be discharged. If POR is pulled back high while V OUTLO and V OUTHI are still ramping down, the discharge will continue. When they drop below the V TRIP point, a powerup sequence will begin automatically. The trip point potential for LTC is set at 0.V and. for LTC-.. In applications, where either V OUTLO or V OUTHI might be forced above 00mV before power-up, the LTC-. should be used. This could occur when leakage through the body diode of the logic chips keeps V OUTLO high or in the case where logic lines are precharged. In other applications, where outputs need to drop to near ground potential before ramping up again to ensure proper initial state for the logic chips, the LTC should be used. Power-On Reset Timing The POR input is used to completely cycle the power supplies on the board or to reset the electronic circuit breaker feature. The POR pin can be connected to a grounded push button, toggle switch or a logic signal from the host. When POR is pulled low for more than 0ms, a power-on reset sequence begins (Figure, HI 0ms 00ms µs DISABLE CON CON CPON GATEHI V OUTHI GATELO V OUTLO V TH V TH PWRGD FAULT POR F Figure. Power-On Reset Timing

15 LTC/LTC-. time point ). Pulses less than 0ms on POR are ignored. CPON goes low. Both GATEHI and GATELO will be actively pulled down to GND. When V OUTLO drops below its reset threshold voltage, PWRGD will immediately pull low (time point ) followed by and DISABLE µs later (time point ). Both supplies will be discharged to ground and stay there until POR is pulled high. The circuit breaker can be reset by pulling POR low. After POR is low for more than 0ms, the chip will immediately try to power up the supplies once the outputs are below the V TRIP point. Circuit Breaker Timing The waveforms for the circuit when a short occurs on either supply during board insertion are shown in Figure. Time points to are the same as the board insertion example, but at time point, a short circuit is detected on one of the supplies. The charge pumps are immediately turned off, the outputs V OUTHI and V OUTLO are actively pulled to GND and the CPON and FAULT pins are pulled low. At time point, the circuit breaker is reset by pulling POR low. After POR has been low for 0ms (time point ), CPON and FAULT are pulled high, the 0µA reference current is connected to RAMP and the charge pumps are enabled. V OUTHI and V OUTLO ramp up at a controlled rate. When V OUTLO has exceeded its reset threshold, the PWRGD signal is pulled high (time point ). After a 00ms delay, is pulled high and DISABLE goes low. 9 0ms 0ms 00ms HI DISABLE CON CON CPON GATEHI V OUTHI GATELO V OUTLO V TH PWRGD FAULT POR F Figure. Circuit Breaker Timing

16 LTC/LTC-. Board Removal Timing When the board is removed from the host, the sequence happens in reverse (Figure ). Since CON and CON are the shortest pins, they break connection first and are internally pulled high (time point ). The charge pumps are turned off, CPON is pulled low. V OUTLO and V OUTHI are actively pulled down. When V OUTLO falls below its reset threshold (time point ) PWRGD is pulled low. To allow time for power fail information to be stored in nonvolatile memory, the falling edge of (time point ) is delayed by µs from the falling edged of PWRGD. Finally, the input supply pins HI and break contact (time point ). If staggered pins are not used, the board may be powered down prior to removal by switching the POR pin to ground with a toggle switch. µs HI DISABLE CON CON CPON GATEHI V OUTHI GATELO V OUTLO V TH PWRGD FAULT POR F Figure. Board Removal Timing

17 LTC/LTC-. Only Applications The LTC may be used in only applications as shown in Figure. A soft reset can be generated from the backplane via an open-collector inverter driving the FB (Pin ) or by a push button to ground. A hard power reset is generated from the backplane via an open-collector inverter driving the POR (Pin ). A hard reset cycles the power on the board or resets the electronic circuit breaker. The comparator is used to monitor the board supply voltage and will pull the POWERGOOD signal low as long as the supply remains above.. Note that a soft reset will not affect the POWERGOOD signal. The FAULT signal is also monitored to determine that the circuit breaker has tripped. V and V Applications The LTC may be used in V applications as shown in Figure 9. The LTC provides the hot insertion protection, while the supply is generated by a power R 0.00Ω W Q MTB0N0E R 0k C LOAD POWERGOOD FAULT SOFT HARD 0k 0k / LS00 C µf 0 9 LTC 0 C µf µf 9 S R k % R 0.k % LOGIC F BACKPLANE PC BOARD Figure. Only Application with Soft Reset V V V STAGGERED CONNECTOR D.V V S R.k W C.µF C µf 0 9 LTC C.µF 0 9 R 00Ω /W Q IRFR90 R k /W µf R k /W Q MPSA0 R 0k /W R 0Ω /W C 00µF 00V IN OUT ASTRODYNE ASD 0-S IN OUT CONTROL F9 A C 00µF V BACKPLANE PC BOARD Figure 9. V to Hot Swappable Supply

18 LTC/LTC-. module. The ground pin for the LTC is connected to V; Zener diode D and resistor R provide the positive supply for the chip. Bypass capacitor C is protected against inrush current by P-channel Q. When the board is inserted into the backplane, transistor Q is turned off by resistor R. When the connection sense pins, CON and CON have been connected to V for more than 0ms, CPON pulls high turning on Q and the gate of Q starts to pull low with a time constant determined by R, R and C. At the same time, the voltage at the input to the power module starts to ramp up. When the voltage across the inputs to the power module reaches the comparator trip level set by R and R, in this case V, the comparator output pulls high and turns on the supply. A cheaper solution is shown in Figure 0 using the LT 0HV switcher. Again P-channel transistor Q protects the bypass capacitors against inrush current and resistors R and R set the comparator trip voltage. The LT0HV is turned on via the V C pin. Resistors R, R and transistor Q provide a monitoring path for the signal which is level shifted up to through an optoisolator. The P-channel power FET is being replaced by an N-channel FET in Figure for the V application. Again, Zener Diode D and resistor R provide the positive supply for the chip. Capacitor C is to insure Q stays off when the board is being hot inserted into the backplane. The resistor divider R and R, along with the internal comparator, perform the undervoltage lock out function. Q would only be turned on when the input supply voltage is lower than V. The power module would then be turned on by the optoisolator, N, when the module s input voltage reaches V. Figure shows how to use the LTC with a V supply and a LT0CT step-down switcher. Resistors R and R set the turn-on threshold to V. All of the supervisory signals can be used without level shifting. Figure shows how to use the LTC with a supply and an LTC0CS synchronous step-down switching regulator to generate.v output at up to 0A for microprocessors. Resistors R, R and R9 set the turn-on voltage at.v and the turn-off at.. Pushbutton switch S provides users a way to reset the output while S is used to soft-reset the microprocessor only. Figure shows how to use the LTC with a supply and a V supply that is used to generate a ±V supply using a supply module. Resistors R and R are used to monitor the input voltage to the supply module. The module is prevented from turning on via the optoisolator until the input voltage reaches V. Zener diode D prevents the CPON pin of the LTC from being damaged by excessive voltage. Figure shows how to use the LTC to do overvoltage protection. Resistors R and R set the trip point at V. When the input supply voltage rises above V, Q is turned on and Q turned off while Q helps to discharge the output voltage. Figure shows how to use the LTC to control both the power-up and power-down sequence of the outputs. The output would be powered up first followed by the V output. At power-down sequence, the V output would go down first followed by the supply. Figure shows how to use the LTC to switch.v,, V and V supplies for PCI application. The rampup rate for.v, and V is determined by the ramp capacitor C while the V supply is controlled by R and C. The internal comparator is being used to do the overcurrent protection for Q with the trip point set by resistors R and R. The V supply does not have overcurrent protection. R0 is used to set the power good signal trip point at 0V. When the V output rises above 0V, the PCI controller gets a power good signal followed by after 00ms.

19 LTC/LTC-. D.V V S R.k W C.µF C µf Q IRFR90 L 00µH 0 9 LTC C.µF 0 9 R 00Ω /W R k /W Q MPSA0 C C.µF 0V C.µF 0V 00µF 00V D. C9 0.µF 0V D MBR00 D MBR00 Q N0 Q N0 F0 STAGGERED CONNECTOR V V V BACKPLANE PC BOARD R k /W µf R 0k /W R 0Ω /W R k /W VCC SW LT0HVCT GND FB VC R9 k /W Figure 0. V to Hot Swappable Supply Using the LT0HVCT R0.k /W R.k /W R.k /W R.k /W C C 000µF 000µF VCC A R 0k /W 9

20 LTC/LTC-. V STAGGERED CONNECTOR 0.µF R.k D.V 0.µF 9 LTC R 0k R 00Ω µf C 0.µF 00Ω 0A.k VICOR 00µF VI-J0-CY 00µF N GATE IN N V Q F BACKPLANE PC BOARD Figure. V to Hot Swappable Supply V FAULT POR STAGGERED CONNECTOR D.V S R.k /W C.µF C µf 0 9 LTC Q IRFR90 V IN V SW C R C.µF k 00µF /W LT0CT 0V V C FB GND 0 9 R 00Ω /W µf R k /W Q MPSA0 R 0k /W R 0Ω /W R9.k C 0.0µF F L 0µH D MBR R.k % R.k % C 00µF A BACKPLANE PC BOARD Figure. V to Hot Swappable Supply Using the LT0CT 0

21 LTC/LTC-. C µf V S 0 9 LTC 0 9 S C 0µF V C 0.µF V C 0µF V D N VCC P SHDN G COMP FB Q MTD0N0HL S: HARD POWER/CIRCUIT BREAKER S: SOFT LTC0 POWER-UP THRESHOLD:.V ON. OFF Q MTD0N0HL Q MTD0N0HL F STAGGERED CONNECTOR BACKPLANE PC BOARD R 0.00Ω W, % Q MTD0N0HL 0k C 0.µF V µf R 0Ω % R9.k % R 00k % R 0k % R0 0k % C0 µf V C 00pF CERAMIC C 0pF CERAMIC R.k % R Ω % GND G LTC0CS C 0.µF V Figure. to.v Hot Swappable Supply Using the LTC0CS.µH A C9 0µF 0V µp GND.V 0A IMAX = A

22 LTC/LTC-. STAGGERED CONNECTOR S C µf R 0.00Ω W Q MTB0N0E LTC 0 9 0k 0 9 C µf µf R 0Ω /W R.k /W Q N0 A R C LOAD k /W IN OUT C 0µF ASTRODYNE 00V ASD0-D IN OUT CONTROL C 00µF V C 00µF V V 0.A V 0.A V C 0.µF R k /W IRF0 R 0k /W F BACKPLANE PC BOARD Figure. and V to ±V Hot Swappable Supply k Q VN R 0.00Ω /W Ω Q MTB0N0E 00Ω 0k Q VN R.k C LOAD A STAGGERED CONNECTOR C µf S 0 9 LTC 0 C 0.µF µf R 0k µp GND F BACKPLANE PC BOARD Figure. Hot Swappable Supply with Overvoltage Protection

23 LTC/LTC-..V STAGGERED CONNECTOR C µf V S R 0.00Ω W Q MTB0N0E R 0.00Ω W k LTC 0.0µF 0 9 Q MTB0N0E R M %,/W 0k C 0.µF V 0 µf 9 R k % /W C 0.µF R 0k % /W R 00k % /W C LOAD C LOAD µp GND A.V A F BACKPLANE PC BOARD Figure. Power-Up and Power-Down Sequence Controller PACKAGE DESCRIPTION.0.** (0.0 0.) U Dimensions in inches (millimeters) unless otherwise noted. G Package -Lead Plastic SSOP (0.09) (LTC DWG # 0-0-0)..99 ( ).0.* (0. 0.) ( ) ( ) NOTE: DIMENSIONS ARE IN MILLIMETERS * DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.mm (0.00") PER SIDE ** DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.mm (0.00") PER SIDE 0. (0.0) BSC ( ) ( ) (0.0 0.) G SSOP ** (.9.9) (0. 0.) (..) SW Package -Lead Plastic Small Outline (Wide 0.00) (LTC DWG # 0-0-0) (0.90.) * (.90.00) TYP ( ) NOTE (0.0.0) 0.00 (.0) BSC (0. 0.) TYP NOTE:. PIN IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.00" (0.mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.00" (0.mm) PER SIDE NOTE ( ) ( ) S (WIDE) 09 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

24 LTC/LTC-. TYPICAL APPLICATION V 00mA.V.A A FAULT ON/OFF PCI POWER CONTROLLER POWER GOOD RST # SELECT BITS C µf V R.k R 0.00Ω % /W U Q IRF R 0Ω 0 LTC R 0.0Ω % W 9 Q / IRF0 R 0Ω R 0Ω 0k 0 9 R0 00k C 0.µF R.k µf R 0.00Ω % W R 00Ω % /W R.k % /W Q IRF PCI CONNECTOR V.A CIRCUIT BREAKER.V.A CIRCUIT BREAKER 0A CIRCUIT BREAKER GND LOGIC RST # BUS ENABLE DATA BUS V 00mA QuickSwitch ALL RESISTORS %, /W EXCEPT WHERE NOTED MOTHERBOARD OR BACKPLANE R 0k Q TP00T R 0k R9 0Ω Q / IRF0 C µf F V NO CIRCUIT BREAKER PCI PERIPHERAL Figure. PCI Power Controller RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC Dual High Side Switch Driver Short-Circuit Protection and Micropower Standby Operation LTC Hot Swap Controller in SO- System Reset Output with Programmable Delay LTC/LTC Single and Dual Protected High Side Switches Inrush Current Limited, Built-In A Short-Circuit Protection LT0L/LT0H Negative Voltage Hot Swap Controller in SO- Operates from 0V to 0V LT High Voltage Hot Swap Controller in SO- Operates from 9V to 0V LTC Fault Protected Hot Swap Controller Operates Up to., Protected to V LTCL/LTCH PCI-Bus Hot Swap Controller.V, and ±V in Narrow -Pin SSOP LTC -Channel Hot Swap Controller Operates from.v to V, Power Sequencing LTC Dual Hot Swap Controller Dual ON Pins for Supplies from V to Linear Technology Corporation 0 McCarthy Blvd., Milpitas, CA 90- (0)-900 FAX: (0) fc LT/LCG 00 K REV C PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 99