INPUT +1.8V TO 28V. Pin Configuration GATE

Transcription

1 9-8; Rev ; /7 Overvoltage Protectors with General Description The overvoltage protection (OVP) controllers protect low-voltage systems against high-voltage faults of up to +8V with an appropriate external pfet. When the input voltage exceeds the overvoltage lockout (OVLO) threshold, or falls below the undervoltage lockout (UVLO) threshold, these devices turn off the pfet to prevent damage to protected components and issue a flag to notify the processor of a fault condition. The typical overvoltage trip level is set to 7.8V (MAX93), 6.6V (MAX9), 5.65V (MAX95), and.6v (MAX96). The undervoltage trip level is set to.v (typ) for all devices. The input () is ESD protected to ±5kV HBM when bypassed to ground with a µf ceramic capacitor. All devices are offered in a small, 6-pin (.5mm x.mm) µdfn package and are specified over the extended - C to +85 C temperature range. Cell Phones Digital Still Cameras PDAs and Palmtop Devices MP3 Players TOP VIEW N.C Applications Pin Configuration N.C 6 5 Overvoltage Protection Up to +8V Features Preset 7.8V, 6.6V, 5.65V, and.6v Typical Overvoltage Trip Levels Preset.V Typical Undervoltage Trip Level ±.5% Accurate Overvoltage/Undervoltage Trip Levels Low 3µA (typ) Supply Current Drives ms Adapter Debounce Time Fault Flag Indicator 6-Pin (.5mm x.mm) µdfn Package PUT +.8V TO 8V μf Typical Operating Circuit P V IO OUTPUT MA93 MAX μdfn Ordering Information/Selector Guide PART P-PACKAGE OVLO (V) UVLO (V) TOP MARK PKG CODE MAX93ELT+* 6 μdfn 7.8. LB L6- MAX9ELT+ 6 μdfn 6.6. LC L6- MAX95ELT+ 6 μdfn LD L6- MAX96ELT+ 6 μdfn.6. LE L6- Note: All devices are specified over the - C to +85 C operating temperature range. +Denotes lead-free package. *Future Product contact factory for availability. Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATGS, to...-.3v to +3V to...-.3v to +6V Continuous Power Dissipation (T A = +7 C) 6-µDFN (derate.mw/ C above 7 C)...68mW Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Operating Temperature Range...- C to +85 C Junction Temperature...+5 C Storage Temperature Range C to +5 C Lead Temperature (soldering, s)...+3 C (V = +5V for MAX93/MAX9/MAX95, V = +V for MAX96, C = 5pF to, T A = - C to +85 C, unless otherwise noted. Typical values are at T A = +5 C.) (Note ) PARAMETER SYMBOL CONDITIONS M TYP MAX UNITS Input Voltage Range V.8 8. V Overvoltage Lockout Level OVLO V rising Overvoltage Lockout Hysteresis MAX MAX MAX MAX MAX93 65 MAX9 55 MAX95 5 MAX96 Undervoltage Lockout Level UVLO V falling V V mv Undervoltage Lockout Hysteresis mv MAX93/MAX9/MAX95 5 Supply Current I MAX µa Voltage High V OH V > 8V, I SOURCE =.ma Pulldown Current I PD = V 6.5 ma Low Voltage V OL I SK = ma. V Leakage Current I LKG V = 5.5V - + µa TIMG CHARACTERISTICS Debounce Time t DEB V UVLO < V < V OVLO, time for to go low (Figure ) V -. 3 ms V Gate Turn-on Time t GON (MAX93/MAX9/MAX95) or = 5V to.5v = V to.5v (MAX96) (Figure ) Gate Turn-Off Time t GOFF (MAX93/MAX9/MAX95) or from V to 7V (MAX96) to = V -.5V V rising at V/µs from 5V to 8V (Figure ).6 µs 5 µs Flag Assertion Delay t (MAX93/MAX9/MAX95) or from V to 7V (MAX96), to V =.V, V rising at V µs from 5V to 8V R = kω to 3V (Figure ).5 µs Note : All devices are % tested at +5 C. Electrical limits across the full temperature range are guaranteed by design and characterization.

3 Typical Operating Characteristics (V = +5V for MAX93/MAX9/MAX95, V = +V for MAX96 (pfet = Si699DQ), T A = +5 C, unless otherwise noted.) SUPPLY CURRENT (μa) 8 6 SUPPLY CURRENT vs. PUT VOLTAGE MAX95 MAX PUT VOLTAGE (V) MAX93 toc VOLTAGE (V) 8 6 VOLTAGE vs. PUT VOLTAGE MAX PUT VOLTAGE (V) MAX93 toc OUTPUT LOW VOLTAGE (mv) OUTPUT LOW VOLTAGE vs. SK CURRENT V CC = +3.3V V CC = +.5V V CC = +5.5V 6 8 SK CURRENT (μa) MAX93 toc3 5 SUPPLY CURRENT vs. TEMPERATURE MAX96 V CC = +V MAX93 toc POWER-UP RESPONSE MAX93 toc5 V POWER-UP RESPONSE MAX93 toc6 V SUPPLY CURRENT (μa) 3 A/div V OUT I V V TEMPERATURE ( C). ms.ms OVERVOLTAGE RESPONSE MAX93 toc7 POWER-UP OVERVOLTAGE RESPONSE MAX93 toc8 V V ma/div I V V.μs.ms 3

4 P NAME FUNCTION Ground 3 Pin Description Voltage Input. is both the power-supply input and the overvoltage/undervoltage sense input. Bypass to with a µf ceramic capacitor as close as possible to the device to enable ±5kV (HBM) ESD protection on. Fault Indication Open-Drain Output. deasserts high during undervoltage and overvoltage lockout conditions. asserts low during normal operation. pfet Gate Drive Output. is driven high during a fault condition to turn off the external pfet. When V UVLO < V < V OVLO, is driven low and the external pfet is turned on. 5, 6 N.C. No Connection. Not internally connected. Leave N.C. unconnected. DRIVER Functional Diagram OVLO AND UVLO DETECTOR CONTROL LOGIC AND TIMER V OVLO V V UVLO t DEB t DEB tgoff t GOFF V -.5V V -.5V O.5V O.5V t GON t GON t t 3V V Figure. Timing Diagram

5 V < V UVLO Figure. State Machine STANDBY = HIGH = HIGH V UVLO < V < V OVLO TIME STARTS COUNTG t = ms ON = LOW = LOW V > V OVLO Detailed Description The overvoltage protection controllers protect low-voltage systems against highvoltage faults of up to +8V when used with a -3V pfet. When the input voltage exceeds the OVLO threshold, these devices turn off the external pfet to prevent damage to protected components. The typical overvoltage trip level is set to 7.8V (MAX93), 6.6V (MAX9), 5.65V (MAX95), and.6v (MAX96). When the supply drops below the UVLO threshold, the devices turn off the external pfet. is ESD protected to +5kV (Human Body Model) when bypassed with a µf ceramic capacitor to ground. Undervoltage Lockout (UVLO) The have a fixed.v (typ) UVLO level. When V is less than V UVLO, is high and is high. Overvoltage Lockout (OVLO) The MAX93 has a 7.8V (typ) OVLO; the MAX9 has a 6.6V (typ) OVLO; the MAX95 has a 5.65V (typ) OVLO; and the MAX96 has a.6v (typ) OVLO. When V is greater than VOVLO, is high and is high. Output The open-drain output is used to signal to the host system that there is a fault with the input voltage. goes high during an overvoltage or undervoltage fault. Connect a pullup resistor from to the logic I/O voltage of the host system. ADAPTER WITH BUILT- BATTERY CHARGER PUT MAX96 Device Operation The have an on-board state machine to control device operation. A flowchart is shown in Figure. At initial power up, if V < V UVLO or if V > V OVLO, both and are high. When V UVLO < V < V OVLO, an internal timer starts counting and the device enters its on state after a ms delay. At any time if V drops below V UVLO or above V OVLO, both and transition high. Application Information MAX96 Application In a typical application for the MAX96, an external adapter with built-in battery charger is connected to and a battery is connected to the drain of the external FET. When the adapter is unplugged, is directly connected to the battery through the external FET. Since the battery voltage is typically greater than V UVLO, the voltage stays low and the device remains powered by the battery. MOSFET Selection The are designed for use with either a single pfet or dual pfets in parallel. MOSFETs with R DS(ON) specified for a V GS of -.5V are recommended. For input supplies near the UVLO maximum of.5v, use a MOSFET specified for a lower V GS voltage. Also, the V DS must be -3V and the V GS (max) must be higher than the VOVLO (max) for the MOSFET to withstand the full +8V input range of the. 3 V I OUTPUT LITHIUM ION BATTERY Figure 3. MAX96 Typical Operating Circuit P + - SYSTEM LOADS 5

6 Table. MOSFETS Suggestions HIGH- VOLTAGE DC SOURCE PART CONFIGURATON/ PACKAGE V DS MAX (V) R ON MAX (mω) at V GS = -.5V Si3993DV Dual/TSOP each Si33DH Single/SOT Si3983DV Dual/TSOP-6 - each Si3DH Single/SOT Si5933DC Dual/6-8 - each Si699DQ Dual/TSSOP each R C MΩ CHARGE-CURRENT LIMIT RESISTOR Cs pf R D.5kΩ DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST AMPERES I P % 9% 36.8% % t RL Ir TIME t DL CURRENT WAVEFORM MANUFACTURER Vishay Siliconix PEAK-TO-PEAK RGG (NOT DRAWN TO SCALE) Figure. Human Body ESD Test Model Figure 5. Human Body Model Current Waveform Bypass Consideration For most applications, bypass to with a µf ceramic capacitor. If the power source has significant inductance due to long lead length, take care to prevent overshoots due to the LC tank circuit and provide protection if necessary to prevent exceeding the 3V absolute maximum rating on. Human Body Model Figure shows the Human Body Model and Figure 5 shows the current waveform it generates when discharged into a low impedance. This model consists of a pf capacitor charged to the ESD voltage of interest that is then discharged into the device through a.5kω resistor. ESD Test Conditions The are ESD protected to ±5kV (typ) Human Body Model on when is bypassed to ground with a µf ceramic capacitor as close as possible to. PROCESS: BiCMOS Chip Information 6

7 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to P MARK TOPMARK AA D TOP VIEW E 5 b SECTION A-A A A SIDE VIEW A L L 3 e 3 A 5 BOTTOM VIEW COMMON DIMENSIONS M. NOM. MAX. A A A D E L L L b.7..3 e.5 BSC. Pkg. Code L6-, L6- A 6 b L P.75x5 6L UDFN.EPS -DRAWG NOT TO SCALE- TITLE: PACKAGE OUTLE, 6L udfn,.5x.x.8mm -7 E APPROVAL DOCUMENT CONTROL NO. REV. TABLE Translation Table for Calendar Year Code Calendar Year Legend: Marked with bar Blank space - no bar required TABLE Translation Table for Payweek Binary Coding Payweek Legend: Marked with bar Blank space - no bar required -DRAWG NOT TO SCALE- TITLE: PACKAGE OUTLE, 6L udfn,.5x.x.8mm -7 E APPROVAL DOCUMENT CONTROL NO. REV. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.