G12 -p ATA V, 5-Volt Tolerant, Fail-Safe I/O Buffer Datasheet

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1 G12 -p ATA V, 5-Volt Tolerant, Fail-Safe I/O Buffer Datasheet The ATA100 I/O buffer provides on-chip input/output (I/O) signaling for application-specific integrated circuit (ASIC) chips implemented in the LSI Logic G12 -p 0.13 µm process technology. The buffer operates at data transfer rates of up to 100 Mbytes/s in ATA 1 applications. An ATA100 bus system of I/O buffers consists of the following cell types: Cell Type Name Function Buffer ata100f5fsls33 Bidirectional signaling Bias atabiasls33 Sets operating level of buffer cells Support atacornerls33 atapvddio33 atapvssio33 atapvdd33 atapvss33 atadvddls33 atadvdd2ls33 ATA100 corner cell 3.3 V I/O power pad cell 3.3 V I/O ground pad cell 1.8 V core power pad cell 1.8 V core ground pad cell 3.3 V ESD protection cell 1.8 V ESD protection cell An ATA100 bus system with one atabiasls33 bias cell may include up to forty ata100f5fsls33 bidirectional buffer cells. Features and Benefits 3.3 V I/O operation Programmable driver slew rate 100 Mbytes/s data transfer Minimum 4 ma current drive 5-Volt tolerant into a 25 pf load at 26.3 MHz Fail-safe at high voltages 1.8 V internal signaling for reduced power consumption Feedthrough protection Uses two standard I/O slots 20 µa maximum leakage current 1. Advanced Technology Attachment protocol established by Technical Committee 13 (T13) of the National Committee on Information Technology Standards (NCITS) under the auspices of the American National Standards Institute (ANSI). May Copyright 2001 by LSI Logic Corporation. All rights reserved.

2 General Description One application of the ATA100 buffer is for storage devices such as hard disk and optical drives that attach to the popular IDE 1 bus. In a 16-bit wide IDE bus application transferring data on both clock edges, for example, the ATA100 bus system transfers data at 100 Mbytes/s with a 25 MHz clock. Maximum clock frequency for the buffer is 26.3 MHz. The ATA100 buffer includes level translation circuitry. It receives 1.8 V level signals from the ASIC circuitry and produces 3.3 V level output at the I/O pad. Similarly, it receives off-chip input at 3.3 volts and translates it to 1.8 volts for the internal ASIC application. Power saving features minimize power consumption. The ATA100 buffer is 5-volt tolerant and fail-safe and protects against voltage feedthrough as follows: Voltage Tolerance Although the off-chip I/O signaling normally operates at 3.3 V, external circuitry may cause higher voltages, typically 5 volts, to appear at the chip I/O pad. Circuit and process techniques ensure that such DC or transient voltages do not damage the buffer circuitry. Safe from Failure The buffer will not fail if a high voltage persists at the I/O pad even with the V DD supply removed. Under such conditions the buffer can survive without degradation for up to ten years. Feedthrough Protection In the absence of a V DD supply and with high voltage applied at the I/O pad, the low, maximum 20 µa leakage current of the buffer prevents voltage feedthrough from powering up the ASIC. The ata100f5fsls33 Buffer Cell The ata100f5fsls33 buffer cell (Figure 1) contains a receiver, a 3-state driver with programmable slew rate, and test circuitry. The driver slew 1. Integrated Drive Electronics 2 G12-p ATA V, 5-Volt Tolerant, Fail-Safe I/O Buffer

3 rate depends on the bias current from the bias cell. Refer to The atabiasls33 Bias Cell section for programming the slew rate. Figure 1 TN EN ata100f5fsls33 Block Diagram Chip I/O Pad A Driver IO IBIAS IDDTN Z Receiver PO Signal Descriptions Built-in NAND-tree logic gates and IDDTN control for IDDQ leakage testing enable use of the standard LSI Logic test methodology. Table 1 describes the ata100f5fsls33 connections. PI Table 1 ata100f5fsls33 Connections Signal Direction Description A IN Data input to driver from ASIC circuitry EN IN Enable 3-state output mode: 0 = Normal mode 1 = Disable driver with output in high-impedance mode IBIAS IN Bias current input from bias cell IDDTN IN 0 = Power down entire cell 1 1 = Normal mode PI IN NAND-tree parametric test input TN IN Alternate or test connection to enable 3-state output mode: 0 = Disable driver with output in high-impedance mode 1 = Normal mode IO IN/OUT Input/output pad PO OUT NAND-tree parametric test output Z OUT Receiver buffer output to ASIC circuitry 1. Used for production IDDQ leakage test G12-p ATA V, 5-Volt Tolerant, Fail-Safe I/O Buffer 3

4 Receiver Truth Table Table 2 describes the ata100f5fsls33 receiver behavior. Table 2 Receiver Truth Table Inputs Outputs IDDTN IO PI Z PO 0 1 High Impedance X Factory IDDQ test setting 2. Don t care state, X = 0 or 1 Driver Truth Table Table 3 describes the ata100f5fsls33 driver behavior. Table 3 Driver Truth Table IDDTN A TN EN IO 0 1 X 2 X X High Impedance Factory IDDQ test setting 2. Don t care state, X = 0 or 1 Storage Application Example 1 X X 1 High Impedance 1 X 0 X High Impedance The DASP 1 line in a disk controller requires a driver with an open-drain output. To configure the driver (Figure 2) in the ata100f5fsls33 cell, connect the A input to ground. This disables the VDD side of the output and produces an open-drain output (Figure 3). 1. Device active or slave present 4 G12-p ATA V, 5-Volt Tolerant, Fail-Safe I/O Buffer

5 Figure 2 Driver with 3-State Output Enable Circuit VDD TN A IO EN Figure 3 Driver Configured for Open-Drain Output IO EN TN For data input to the configured driver, use EN or TN. For example, send positive-logic data to EN and set TN = 1, the normal mode. Applying data, EN = 1 forces IO to the high-impedance state. With EN = 0, the IO output sinks current, which pulls the output LOW. Alternatively, send negative-logic data to TN and set EN = 0, the normal mode. Applying data, TN = 0 forces IO to the high-impedance state. With TN = 1, the IO output sinks current, which pulls the output LOW. Specifications The buffer adheres to the general specifications in Table 4. Table 5 describes the driver DC characteristics. Table 6 describes the receiver DC characteristics. Table 4 General Specifications Symbol Parameter Condition Min. Typ. Max. Unit V DD Supply voltage V T j Junction temperature C ESD Electrostatic discharge, human body model (HBM) MIL-STD-883C, Method KΩ 2000 V Electrostatic discharge, charged device model (CDM) ESD DS V G12-p ATA V, 5-Volt Tolerant, Fail-Safe I/O Buffer 5

6 Table 5 Driver DC Characteristics 1 Symbol Parameter Test Condition Min. Typ. Max. Units V DD Supply voltage V OL and high impedance output only V V OL Output, LOW I OL = 12 ma V V OH Output, HIGH I OH = 12 ma 2.4 V I OL Sink current V OL = 0.4 V maximum 4 ma I OH Source current V OH = 2.4 V minimum 4 ma I LU Latchup current 2 V<V PAD <+8V ±100 ma 1. Values apply over all voltage, temperature, and process conditions. Table 6 Receiver DC Characteristics 1 Symbol Parameter Test Condition Min. Typ. Max. Units V IL Threshold, HIGH-to-LOW V V IH Threshold, LOW-to-HIGH V V TH V TL Hysteresis 320 mv I LU Latch-up current 2 V<V PAD <+8V ±100 ma 1. Values apply over all voltage, temperature, and process conditions. The atabiasls33 Bias Cell The atabiasls33 bias cell (Figure 4) produces a reference current compensated for temperature, voltage, and process variations. The ata100f5fsls33 buffer cell requires this precision reference current to minimize any slew-rate variation. The bias cell can provide a reference current for up to 40 ata100f5fsls33 buffer cells. 6 G12-p ATA V, 5-Volt Tolerant, Fail-Safe I/O Buffer

7 Figure 4 atabiasls33 Block Diagram IDDTN DH DL I/O Pad for VDD Supply and External Bias Resistor Connection Bias Lines to I/O Buffer Cells IB0 IB1 IB2 atabiasls33 VDDABIAS RBIAS IB38 IB39 I/O Pad for External Bias Resistor Connection Signal Descriptions The bias cell requires an external bias resistor with a value of 10 kω ± 1%, ± 250 ppm/ C connected between VDDABIAS and RBIAS. Place the resistor on the board as close as possible to the RBIAS and VDDABIAS package pins. Table 7 describes the atabiasls33 connections. Table 7 atabiasls33 Connections Signal Direction Description DH, DL IN Sets driver slew rate (Table 8) in I/O buffer cell IDDTN IN 0 = Power down entire cell 1, set IB0 through IB39 to high-impedance 1 = Normal mode RBIAS IN Connection point for external bias resistor VDDABIAS IN 3.3 V isolated V DD supply; connection point for external bias resistor IB0 to IB39 OUT 1. Used for production IDDQ leakage test. Bias current outputs for up to 40 I/O buffer cells. Connects to IBIAS in the I/O buffer. Leave unconnected when not used. G12-p ATA V, 5-Volt Tolerant, Fail-Safe I/O Buffer 7

8 Slew Rate Control Table 8 describes the driver slew rate control settings. Table 8 Programmable Slew Rate for Buffer Driver Input Selection Target Slew Rate 1 DL DH Setting mv/ns 0 0 Nominal Nominal x 120% Nominal x 90% Nominal x 80% Measured between 10% and 90% of the signal minimum-to-maximum DC level and with capacitive load = 25 pf (Figure 5). Applies to rising and falling edges. Figure 5 Rise/Fall Test Circuit Input Driver Output 25 pf GND Support Type Cells Besides the ata100f5fsls33 buffer cell and the atabiasls33 bias cell, an ATA100 bus system requires the following support cells for the physical layout: atapvddio33 atapvdd33 atadvddls33 atacornerls33 atapvssio33 atapvss33 atadvdd2ls33 Refer to the LSI Logic field customer engineer (FCE) for technical details about these cells. 8 G12-p ATA V, 5-Volt Tolerant, Fail-Safe I/O Buffer

9 System Design Guidelines Placement To ensure good system-level operation, LSI Logic provides guidelines for cell placement in the ASIC, supplying power, and bias line layout. Cells in an ATA100 bus system occupy I/O slots along the I/O rings, the power buses circling the ASIC chip. The four power buses and the ZZIDTNZZ line cross the cells in the standard I/O slot locations. Table 9 shows the cell dimensions and the number of I/O slots used. Table 9 Cell Dimensions on the I/O Ring Cell Length into the Chip Width Along the I/O Ring Number of I/O slots ata100f5fsls µm µm 2 atabiasls µm µm 2 atacornerls µm µm atapvddio µm µm 1 atapvssio µm µm 1 atapvdd µm µm 1 atapvss µm µm 1 atadvddls µm µm > 1 atadvdd2ls µm µm > 1 For correct placement of the ATA100 cells, adhere to the following guidelines. Buffer Cells - Array the ata100f5fsls33 buffer cells close together on one side of the chip without intermixing other cells except the listed support cells. If required, the cells may wrap around a corner to a second side. Corner Cell - The bias and buffer cell dimensions into the chip exceed the standard I/O slot length. When placed close to the corner G12-p ATA V, 5-Volt Tolerant, Fail-Safe I/O Buffer 9

10 of a chip, these cells could intrude into the allocated space of I/O cells on the adjacent side. To prevent this condition, place an atacornerls33 cell at the affected corner position of the chip (Figure 6). Then, place any two of the other support cells as filler to further separate a bias or buffer cell from the corner cell. If the array wraps around a corner, extending along two sides of the chip, place two support cells as filler on the other side of the corner cell, too. Figure 6 Corner Cell Placement ASIC Filler Cells Buffer Cells Buffer Array Corner Cell Chip Edge Bias Cell - Place the atabiasls33 bias cell at the center of the buffer array. Place an atapvssio33 ground pad cell on each side of the bias cell as filler to separate it from other cells. For best performance, isolate the ATA100 buffer array, including the bias cell and associated support cells, from other I/O cells with power cuts on the I/O ring. Power For best system-level performance, adhere to the following power guidelines: Use one atapvddio33/atapvssio33 power-and-ground pad cell pair for every four buffer cells. Place a buffer cell no more than 8 slots away from a power pad and no more than 8 slots away from a ground pad. Place core power and ground cells, atapvdd33 and atapvss33, intermixed anywhere within the buffer array as required. 10 G12-p ATA V, 5-Volt Tolerant, Fail-Safe I/O Buffer

11 Bias Lines The atabiasls33 cell can provide bias currents for up to 40 ata100f5fsls33 buffer cells. To keep these currents quiet and stable, lay out the bias lines carrying these currents as follows: Distribute the lines from the bias cell symmetrically and in parallel to both sides of the buffer array uninterrupted on metal layer M1 and shielded by an overlapping grounded metal layer M2. Leave unused bias lines unconnected at the bias cell. Figure 7 illustrates the layout of the bias lines. Figure 7 Bias Line Layout Example Buffer Cell Uninterrupted M1 bias lines cross cell, shielded by a grounded M2 plate Bias Cell M1 bias lines fan out symmetrically to both sides of the array shielded with a grounded M2 plate Buffer Cell Uninterrupted M1 bias lines cross cell, shielded by a grounded M2 plate Shield Bias Lines G12-p ATA V, 5-Volt Tolerant, Fail-Safe I/O Buffer 11

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G12 -p 3.3 V, 4 ma, 5-Volt Tolerant, Fail-Safe, General Purpose I/O Buffers Datasheet

G12 -p 3.3 V, 4 ma, 5-Volt Tolerant, Fail-Safe, General Purpose I/O Buffers Datasheet LSI Logic Corporation provides the following driver/receiver input/output (I/O) cells for use as general purpose I/O