HC08AZ32TS/D Rev. 1.1 HC08AZ0 HC08AZ16 HC08AZ24 HC08AZ32 HC08AB0 HC08AB16 HC08AB24 HC08AB32. HCMOS Microcontroller Unit TECHNICAL SUMMARY

Transcription

1 HC08AZ32TS/D Rev.. HC08AZ0 HC08AZ6 HC08AZ24 HC08AZ32 HC08AB0 HC08AB6 HC08AB24 HC08AB32 HCMOS Microcontroller Unit TECHNICAL SUMMARY

2 HC08AZ32 HCMOS MICROCONTROLLER UNIT Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. 997 MOTOROLA, INC.

3

4 TABLE OF CONTENTS Paragraph Title Page SECTION GENERAL DESCRIPTION. Introduction Features Pin Assignments Power supply pins (V DD and V SS ) Oscillator pins (OSC and OSC2) External reset pin (RST) External interrupt pin (IRQ) Analog power supply pin (V DDA ) Analog ground pin (V SSA ) Analog ground pin (A VSS /VREFL) ADC voltage reference pin (VREFH) Analog supply pin (V DDAREF ) External filter capacitor pin (CGMXFC) Port A input/output (I/O) pins (PTA7 PTA0) Port B I/O pins (PTB7/ATD7 PTB0/ATD0) Port C I/O pins (PTC5 PTC0) Port D I/O pins (PTD7 PTD0) Port E I/O pins (PTE7/SPSCK PTE0/TxD) Port F I/O pins (PTF6 PTF0/TACH2) Port G I/O pins (PTG2/KBD2 PTG0/KBD0) Port H I/O pins (PTH/KBD4 PTH0/KBD3) CAN transmit pin (CANTx) CAN receive pin (CANRx) SECTION 2 MEMORY MAP 2. Introduction Memory section I/O section SECTION 3 RAM 3. Introduction Functional description HC08AZ32 TABLE OF CONTENTS MOTOROLA Rev.. i

5 SECTION 4 ROM 4. Introduction Functional description User ROM Security SECTION 5 EEPROM 5. Introduction Features Functional description EEPROM programming EEPROM erasing EEPROM block protection EEPROM redundant mode EEPROM configuration MCU configuration HC08AZ32 EEPROM security EEPROM control register (EECR) EEPROM non-volatile register (EENVR) and EEPROM array configuration register (EEACR) Low power modes WAIT mode STOP mode SECTION 6 CENTRAL PROCESSOR UNIT (CPU) 6. Introduction Features CPU registers Accumulator (A) Index register (H:X) Stack pointer (SP) Program counter (PC) Condition code register (CCR) Arithmetic/logic unit (ALU) CPU during break interrupts SECTION 7 SYSTEM INTEGRATION MODULE (SIM) 7. Introduction SIM bus clock control and generation Bus timing Clock start-up from POR or LVI reset MOTOROLA TABLE OF CONTENTS HC08AZ32 ii Rev..

6 7.2.3 Clocks in STOP and WAIT mode Reset and system initialization External pin reset Active resets from internal sources Power-on reset Computer operating properly (COP) reset Illegal opcode reset Illegal address reset Low-voltage inhibit (LVI) reset SIM counter SIM counter during power-on reset SIM counter during STOP mode recovery SIM counter and reset states Exception control Interrupts Hardware interrupts SWI instruction Reset Break interrupts Status flag protection in break mode Low-power modes WAIT mode STOP mode SIM registers SIM break status register (SBSR) SIM reset status register (SRSR) SIM break flag control register (SBFCR) SECTION 8 CLOCK GENERATOR MODULE (CGM) 8. Introduction Features Functional description Crystal oscillator circuit Phase-locked loop (PLL) circuit PLL circuits Acquisition and tracking modes Manual and automatic PLL bandwidth modes Programming the PLL Special programming exceptions Base clock selector circuit CGM external connections I/O Signals Crystal amplifier input pin (OSC) Crystal amplifier output pin (OSC2) External filter capacitor pin (CGMXFC) HC08AZ32 TABLE OF CONTENTS MOTOROLA Rev.. iii

7 8.4.4 PLL analog power pin (V DDA ) Oscillator enable signal (SIMOSCEN) Crystal output frequency signal (CGMXCLK) CGM base clock output (CGMOUT) CGM CPU interrupt (CGMINT) CGM registers PLL control register (PCTL) PLL Bandwidth control register (PBWC) PLL Programming register (PPG) Interrupts Special modes WAIT mode STOP mode CGM during break interrupts Acquisition/lock time specifications Acquisition/lock time definitions Parametric influences on reaction time Choosing a filter capacitor Reaction time calculation SECTION 9 MASK OPTIONS 9. Introduction Functional description SECTION 0 BREAK MODULE 0. Introduction Features Functional description Flag protection during break interrupts CPU during break interrupts DMA during break interrupts TIM and PIT during break interrupts COP during break interrupts Break module registers Break status and control register (BRKSCR) Break address registers (BRKH and BRKL) Low-power modes WAIT mode STOP mode SECTION MONITOR ROM (MON). Introduction MOTOROLA TABLE OF CONTENTS HC08AZ32 iv Rev..

8 .2 Features Functional description Entering monitor mode Data format Echoing Break signal Commands Baud rate SECTION 2 COMPUTER OPERATING PROPERLY MODULE 2. Introduction Functional description I/O Signals CGMXCLK STOP instruction COPCTL write Power-on reset Internal reset Reset vector fetch COPD (COP disable) COP Control register (COPCTL) Interrupts Monitor mode Low-power modes WAIT mode STOP mode COP module during break interrupts SECTION 3 LOW-VOLTAGE INHIBIT MODULE (LVI) 3. Introduction Features Functional description Polled LVI operation Forced reset operation False reset protection LVI Status Register (LVISR) LVI interrupts Low-power modes WAIT mode SECTION 4 EXTERNAL INTERRUPT MODULE (IRQ) 4. Introduction HC08AZ32 TABLE OF CONTENTS MOTOROLA Rev.. v

9 4.2 Features Functional description IRQI pin IRQ module during break interrupts IRQ status and control register (ISCR) SECTION 5 SERIAL COMMUNICATIONS INTERFACE MODULE (SCI) 5. Introduction Features Functional description Data format Transmitter Receiver Low-power modes Wait mode STOP mode SCI during break module interrupts I/O signals PTE2/TxD (transmit data) PTE/RxD (receive data) I/O registers SCI control register (SCC) SCI Control Register 2 (SCC2) SCI control register 3 (SCC3) SCI status register (SCS) SCI status register 2 (SCS2) SCI data register (SCDR) SCI baud rate register (SCBR) SECTION 6 SERIAL PERIPHERAL INTERFACE MODULE (SPI) 6. Introduction Features Pin name conventions and I/O register addresses Functional description Master mode Slave mode Transmission formats Clock phase and polarity controls Transmission format when CPHA = Transmission format when CPHA = Transmission initiation latency Error conditions Overflow error Mode fault error MOTOROLA TABLE OF CONTENTS HC08AZ32 vi Rev..

10 6.7 Interrupts Queuing transmission data Resetting the SPI Low-power modes WAIT mode STOP mode SPI during break interrupts I/O Signals MISO (Master in/slave out) MOSI (Master out/slave in) SPSCK (serial clock) SS (slave select) CGND (clock ground) I/O registers SPI control register (SPCR) SPI status and control register (SPSCR) SPI data register (SPDR) SECTION 7 TIMER INTERFACE MODULE A (TIMA) 7. Introduction Features Functional description TIMA counter prescaler Input capture Output compare Unbuffered output compare Buffered output compare Pulse width modulation (PWM) Unbuffered PWM signal generation Buffered PWM signal generation PWM initialization Interrupts Low-power modes Wait mode TIMA during break interrupts I/O Signals TIMA clock pin (PTD6/TACLK) TIMA channel I/O pins (PTF/TACH3-PTE2/TACH0) I/O registers TIMA status and control register (TASC) TIMA counter registers (TACNTH:TACNTL) TIMA counter modulo registers (TAMODH:TAMODL) TIMA channel status and control registers (TASC0 TASC3) TIMA channel registers (TACH0H/L TACH3H/L) HC08AZ32 TABLE OF CONTENTS MOTOROLA Rev.. vii

11 SECTION 8 TIMER INTERFACE MODULE B (TIMB) 8. Introduction Features Functional description TIMB counter prescaler Input capture Output compare Unbuffered output compare Buffered output compare Pulse Width Modulation (PWM) Unbuffered PWM signal generation Buffered PWM signal generation PWM initialization Interrupts Low-power modes WAIT mode TIMB during break interrupts I/O Signals TIMB clock Pin (PTD4/TBLCK) TIMB channel I/O pins (PTF5/TBCH PTF4/TBCH0) I/O Registers TIMB status and control register (TBSC) TIMB counter registers (TBCNTH:TBCNTL) TIMB counter modulo registers (TBMODH:TBMODL) TIMB channel status and control registers (TBSC0 TBSC) TIMB channel registers (TBCH0H/L TBCHH/L) SECTION 9 PROGRAMMABLE INTERRUPT TIMER (PIT) 9. Introduction Features Functional Description PIT counter prescaler Low-power modes WAIT mode STOP mode PIT during break interrupts I/O registers PIT status and control register (PSC) PIT counter registers (PCNTH:PCNTL) PIT Counter modulo registers (PMODH:PMODL) SECTION 20 ANALOG TO DIGITAL CONVERTOR (ADC) MOTOROLA TABLE OF CONTENTS HC08AZ32 viii Rev..

12 20. Introduction Features Functional description ADC port I/O pins Voltage conversion Conversion time Continuous conversion Accuracy and precision Interrupts Low power modes WAIT mode STOP mode I/O signals ADC analog power pin (V DDAREF ) ADC analog ground pin (A VSS /VREFL) ADC voltage reference pin (VREFH) ADC voltage in (ADVIN) I/O registers ADC status and control register (ADSCR) ADC data register (ADR) ADC clock register (ADCLKR) SECTION 2 KEYBOARD MODULE (KB) 2. Introduction Features Functional description I/O Registers Keyboard status and control register (KBSCR) Keyboard interrupt enable register (KBIER) Keyboard module during break interrupts SECTION 22 I/O PORTS 22. Introduction Port A Port A Data Register (PTA) Data direction register A (DDRA) Port B Port B data register (PTB) Data direction register B (DDRB) Port C Port C data register (PTC) Data direction register C (DDRC) Port D Port D data register (PTD) HC08AZ32 TABLE OF CONTENTS MOTOROLA Rev.. ix

13 Data direction register D (DDRD) Port E Port E data register (PTE) Data direction register E (DDRE) Port F Port F data register (PTF) Data direction register F (DDRF) Port G Port G data register (PTG) Data direction register G (DDRG) Port H Port H data register (PTH) Data direction register H (DDRH) SECTION 23 mscan08 CONTROLLER 23. Features External pins Message storage Background Receive structures Transmit structures Identifier acceptance filter Interrupts Interrupt acknowledge Interrupt vectors Protocol violation protection Low power modes mscan08 internal sleep mode CPU WAIT mode CPU STOP mode Programmable wake-up function Timer link Clock system Memory map Programmer s model of message storage Message Buffer outline Identifier registers (IDRn) Data length register (DLR) Data segment registers (DSRn) Transmit buffer priority registers (TBPR) Programmer s model of control registers Overview mscan08 module control register (CMCR0) mscan08 module control register (CMCR) mscan08 bus timing register 0 (CBTR0) MOTOROLA TABLE OF CONTENTS HC08AZ32 x Rev..

14 mscan08 bus timing register (CBTR) mscan08 receiver flag register (CRFLG) mscan08 Receiver Interrupt Enable Register (CRIER) mscan08 Transmitter Flag Register (CTFLG) mscan08 Transmitter Control Register (CTCR) mscan08 Identifier Acceptance Control Register (CIDAC) mscan08 Receive Error Counter (CRXERR) mscan08 Transmit Error Counter (CTXERR) mscan08 Identifier Acceptance Registers (CIDAR0-3) mscan08 Identifier Mask Registers (CIDMR0-3) APPENDIX A Devices Similar to the HC08AZ32 A. HC08AZ A- A.. Features A- A..2 MCU block diagram A- A..3 Pin assignments A- A..4 Pin descriptions A-3 A..4. Power supply pins(e VDD3 /E VDD and E VSS4 /E VSS ) A-3 A..4.2 External data pins (EDB7-EDB0) A-3 A..4.3 External address pins (EAB5-EAB0) A-4 A..4.4 Write control pin (WEB) A-4 A..4.5 Read control pin (REB) A-4 A..4.6 WAIT states clock pin (WSCLK) A-4 A..4.7 External chip-select pins (CS,CS0) A-4 A..5 Memory Section A-5 A..5. Memory Map A-5 A..6 ROM security A-5 A..7 LVI reset A-5 A..8 LVI power A-5 A..9 STOP mode recovery delay A-5 A..0 STOP instruction A-5 A.. COP module A-5 A..2 Reset vector source A-5 A..3 EEPROM security A-5 A..4 External Bus Interface (EBI) Module A-7 A..4. Introduction A-7 A..4.2 Features A-8 A..4.3 Module I/O signal descriptions A-9 A Internal Address - IAB[5:0] A-0 A Internal data - IDB[7:0] A-0 A Internal read/write - IRW A-0 A External access (External) A-0 A EBIEN - EBI enable A-0 A Internal WAIT state - IWS A-0 A External address bus - A[5:0] A-0 HC08AZ32 TABLE OF CONTENTS MOTOROLA Rev.. xi

15 A Chip-selects - CS, CS A- A External data bus - DB[7:0] A- A External read - REB A- A External write - WEB A- A WAIT state clock - WSCLK A- A..4.4 Functional description A- A..4.5 Externally controlled WAIT states A-3 A..4.6 EBI control registers A-9 A EBI control register A-9 A..4.7 CSC: A-20 A..4.8 EBI Chip-Select Register A-2 A..4.9 Electrical information A-22 A.2 HC08AZ A-27 A.2. Features A-27 A.2.2 Block diagram A-27 A.2.3 Pin assignments A-27 A.2.4 Memory section A-30 A.2.5 Memory map A-30 A.2.6 RAM A-30 A.2.7 ROM A-30 A.3 HC08AZ A-33 A.3. Features A-33 A.3.2 Block diagram A-33 A.3.3 Pin assignments A-33 A.3.4 Memory section A-36 A.3.5 Memory map A-36 A.3.5. RAM A-36 A ROM A-36 A.4 HC08AB A-39 A.4. Features A-39 A.4.2 Block diagram A-39 A.4.3 Pin assignments A-39 A.4.4 Memory section A-42 A.4.4. Memory map A-42 A RAM A-42 A ROM A-42 A.4.5 I/O section A-42 A.5 HC08AB A-45 A.5. Features A-45 A.5.2 MCU block diagram A-45 A.5.3 Pin assignments A-45 A.5.4 Pin descriptions A-48 A.5.4. Power supply pins(e VDD3 /E VDD and E VSS4 /E VSS ) A-48 A External data pins (EDB7-EDB0) A-48 A External address pins (EAB5-EAB0) A-48 A Write control pin (WEB) A-48 A Read control pin (REB) A-48 MOTOROLA TABLE OF CONTENTS HC08AZ32 xii Rev..

16 A WAIT states clock pin (WSCLK) A-48 A External chip-select pins (CS,CS0) A-48 A.5.5 Memory section A-49 A.5.5. Memory map A-49 A RAM A-49 A.5.6 I/O section A-49 A.5.7 ROM security A-49 A.5.8 LVI reset A-49 A.5.9 LVI power A-50 A.5.0 STOP mode recovery delay A-50 A.5. STOP instruction A-50 A.5.2 COP module A-50 A.5.3 Reset vector source A-50 A.5.4 EEPROM security A-50 A.5.5 External bus interface module A-50 A.6 HC08AB A-53 A.6. Features A-53 A.6.2 Block diagram A-53 A.6.3 Pin assignments A-53 A.6.4 Memory section A-56 A.6.4. Memory map A-56 A RAM A-56 A ROM A-56 A.6.5 I/O section A-56 A.7 HC08AB A-59 A.7. Features A-59 A.7.2 Block diagram A-59 A.7.3 Pin assignments A-59 A.7.4 Memory section A-62 A.7.4. Memory map A-62 A RAM A-62 A ROM A-62 A.7.5 I/O section A-62 HC08AZ32 TABLE OF CONTENTS MOTOROLA Rev.. xiii

17 MOTOROLA TABLE OF CONTENTS HC08AZ32 xiv Rev..

18 LIST OF FIGURES Figure Title Page - MCU block diagram QFP pin assignments (top view) Power supply bypassing Memory map Control, status, and data registers EEPROM control register (EECR) EEPROM array control register (EEACR) EEPROM non-volatile register (EENVR) CPU registers Accumulator (A) Index register (H:X) Stack pointer (SP) Program counter (PC) Condition code register (CCR) SIM block diagram CGM clock signals External reset timing Internal reset timing Sources of internal reset POR recovery Interrupt entry Interrupt processing Interrupt recovery Interrupt recognition example WAIT mode entry timing WAIT recovery from interrupt or break WAIT recovery from internal reset STOP mode entry timing STOP mode recovery from interrupt or break SIM break status register (SBSR) SIM reset status register (SRSR) SIM break flag control register (SBFCR) CGM Block Diagram CGM external connections CGM I/O Register Summary PLL control register (PCTL) PLL bandwidth control register (PBWC) PLL Programming register (PPG) Mask option register A (MORA) HC08AZ32 LIST OF FIGURES MOTOROLA Rev.. i

19 9-2 Mask option register B (MORB) Break module block diagram Break status and control register (BRKSCR) Break address registers (BRKH and BRKL) Monitor mode circuit Monitor data format Sample monitor waveforms Read transaction Break transaction COP block diagram COP control register (COPCTL) LVI module block diagram LVI Status Register (LVISR) IRQ module block diagram IRQ interrupt flowchart IRQ status and control register (ISCR) SCI module block diagram SCI data formats SCI transmitter SCI receiver block diagram Receiver data sampling SCI control register (SCC) SCI control register 2 (SCC2) SCI control register 3 (SCC3) SCI status register (SCS) Flag clearing sequence SCI status register 2 (SCS2) SCI data register (SCDR) SCI Baud Rate Register (SCBR) SPI I/O register summary SPI module block diagram Full-duplex master-slave connections Transmission format (CPHA = 0 ) CPHA/SS timing Transmission format (CPHA = ) Transmission start delay (master) Overflow condition with DMA service of SPRF Missed read of overflow condition Clearing SPRF when OVRF interrupt is not enabled SPI interrupt request generation SPRF/SPTE CPU interrupt timing CPHA/SS timing SPI control register (SPCR) SPI status and control register (SPSCR) SPI data register (SPDR) TIMA block diagram PWM period and pulse width MOTOROLA LIST OF FIGURES HC08AZ32 ii Rev..

20 7-3 TIMA status and control register (TASC) TIMA counter registers (TACNTH:TACNTL) TIMA counter modulo registers (TAMODH:TAMODL) TIMA channel status and control registers (TASC0 TASC3) CHxMAX Latency TIMA channel registers (TACH0H/L TACH3H/L) TIMB Block Diagram PWM period and pulse width TIMB status and control register (TBSC) TIMB counter registers (TBCNTH:TBCNTL) TIMB counter modulo registers (TBMODH:TBMODL) TIMB channel status and control registers (TBSC0 TBSC) CHxMAX latency TIMB channel registers (TBCH0H/L TBCHH/L) PIT Block Diagram PIT Status and Control Register (TSC) PIT counter registers (PCNTH:PCNTL) PIT Counter modulo registers (TMODH:TMODL) ADC block diagram ADC status and control register ADC data register ADC clock register Keyboard module block diagram Keyboard status and control register (KBSCR) Keyboard interrupt enable register (KBIER) Port A data register (PTA) Data direction register A (DDRA) Port A I/O Circuit Port B data register (PTB) Port B I/O circuit Data direction register B (DDRB) Port C data register (PTC) Data direction register C (DDRC) Port C I/O circuit Port D data register (PTD) Data direction register D (DDRD) Port D I/O circuit Port E data register (PTE) Port E I/O circuit Data direction register E (DDRE) Port F data register (PTF) Data direction register F (DDRF) Port F I/O circuit Port G data register (PTG) Data direction register G (DDRG) Port G I/O circuit Port H data register (PTH) HC08AZ32 LIST OF FIGURES MOTOROLA Rev.. iii

21 22-23 Data direction register H (DDRH) Port H I/O circuit The CAN system User model for Message Buffer organization Single 32 bit maskable identifier acceptance filter Dual 6 bit maskable acceptance filters Quadruple 8 bit maskable acceptance filters Sleep request/acknowledge cycle Clocking scheme Segments within the bit time CAN standard compliant bit time segment settings mscan08 memory map Message Buffer organisation Receive/Transmit Message Buffer extended identifier Standard identifier mapping Transmit buffer priority register (TBPR) mscan08 Control Register Structure Module control register 0 (CMCR0) Module control register (CMCR) Bus timing register Bus timing register Receiver flag register Receiver Interrupt Enable Register Transmitter Flag Register Identifier Acceptance Control Register Receive Error Counter Transmit Error Counter Identifier Acceptance Registers Identifier Mask Registers A- MCU Block Diagram A-2 A-2 00TQFP pin assignments (Top View) A-3 A-3 Memory map A-6 A-4 EBI Block Diagram A-9 A-5 Software controlled chip-select combinations A-2 A-6 Defining WAIT states for Ext addresses below $ A-5 A-7 Simple address space decode with different WAIT states A-7 A-8 WAIT state selection for multiple I/O peripherals A-8 A-9 EBI control register (EBIC) A-9 A-0 EBI control register (EBICS) A-2 A- High performance read timings A-22 A-2 High performance write timings A-23 A-3 Low noise mode read timings A-24 A-4 Low-noise mode write timings A-25 A-5 MCU block diagram A-28 A-6 QFP pin assignments A-29 A-7 Memory map A-3 A-8 MCU block diagram A-34 MOTOROLA LIST OF FIGURES HC08AZ32 iv Rev..