MC68HC908AS60/D REV 1 8M68HC08M HC08M68HC. MC68HC908AS60 Technical Data. HCMOS Microcontroller Unit

Transcription

1 68HC08M6 HC08M68HC MC68HC908AS60/D REV 1 8M68HC08M MC68HC908AS60 Technical Data HCMOS Microcontroller Unit

2 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Motorola and are registered trademarks of Motorola, Inc. DigitalDNA is a trademark of Motorola, Inc. Motorola, Inc., 2000

3 Technical Data MC68HC908AS60 List of Sections Section 1. General Description Section 2. Memory Map Section 3. Random-Access Memory (RAM) Section 4. FLASH-1 Memory Section 5. FLASH-2 Memory Section 6. EEPROM Section 7. EEPROM Section 8. Central Processor Unit (CPU) Section 9. System Integration Module (SIM) Section 10. Clock Generator Module (CGM) Section 11. Configuration Register (CONFIG-1) Section 12. Break Module Section 13. Monitor ROM (MON) Section 14. Computer Operating Properly (COP) Module Section 15. Low-Voltage Inhibit (LVI) Module Section 16. External Interrupt Module (IRQ) Section 17. Serial Communications Interface (SCI) MC68HC908AS60 Rev. 1.0 Technical Data MOTOROLA List of Sections 3

4 List of Sections Section 18. Serial Peripheral Interface (SPI) Section 19. Modulo Timer (TIM) Section 20. Input/Output (I/O) Ports Section 21. Byte Data Link Controller-Digital (BDLC-D) Section 22. Timer Interface Module A (TIMA-6) Section 23. Analog-to-Digital Converter (ADC-15) Section 24. Electrical Specifications Section 25. Mechanical Specifications Section 26. Ordering Information Index Technical Data MC68HC908AS60 Rev List of Sections MOTOROLA

5 Technical Data MC68HC908AS60 Table of Contents Section 1. General Description 1.1 Contents Introduction Features MCU Block Diagram Pin Assignments Power Supply Pins (V DD and V SS ) Oscillator Pins (OSC1 and OSC2) External Reset Pin (RST) External Interrupt Pin (IRQ) Analog Power Supply Pin (V DDA ) Analog Ground Pin (V SSA ) External Filter Capacitor Pin (CGMXFC) Port A Input/Output (I/O) Pins (PTA7 PTA0) Port B I/O Pins (PTB7/ATD7 PTB0/ATD0) Port C I/O Pins (PTC5 PTC0) Port D I/O Pins (PTD7 PTD0/ATD8) Port E I/O Pins (PTE7/SPSCK PTE0/TxD) Port F I/O Pins (PTF7 PTF0/TACH2) Port G I/O Pins (PTG2 PTG0) Port H I/O Pins (PTH1 PTH0) BDLC Transmit Pin (BDTxD) BDLC Receive Pin (BDRxD) MC68HC908AS60 Rev. 1.0 Technical Data MOTOROLA Table of Contents 5

6 Table of Contents Section 2. Memory Map 2.1 Contents Introduction Input/Output Section Section 3. Random-Access Memory (RAM) 3.1 Contents Introduction Functional Description Section 4. FLASH-1 Memory 4.1 Contents Introduction Functional Description FLASH-1 Control Register FLASH Charge Pump Frequency Control FLASH Erase Operation FLASH Program/Margin Read Operation FLASH Block Protection FLASH-1 Block Protect Register FLASH-2 Block Protect Register Low-Power Modes Wait Mode Stop Mode Section 5. FLASH-2 Memory 5.1 Contents Introduction Functional Description Technical Data MC68HC908AS60 Rev Table of Contents MOTOROLA

7 Table of Contents 5.4 FLASH Control Register FLASH Charge Pump Frequency Control FLASH Erase Operation FLASH Program/Margin Read Operation FLASH Block Protection FLASH Block Protect Register Low-Power Modes Wait Mode Stop Mode Section 6. EEPROM Contents Introduction Features Functional Description EEPROM Programming EEPROM Erasing EEPROM Block Protection EEPROM Redundant Mode MCU Configuration EEPROM Protection EEPROM Control Register EEPROM Non-Volatile Register and EEPROM Array Configuration Register Low-Power Modes Wait Mode Stop Mode MC68HC908AS60 Rev. 1.0 Technical Data MOTOROLA Table of Contents 7

8 Table of Contents Section 7. EEPROM Contents Introduction Features Functional Description EEPROM Programming EEPROM Erasing EEPROM Block Protection EEPROM Redundant Mode MCU Configuration MC68HC908AS60 EEPROM Protect EEPROM Control Register EEPROM Non-Volatile Register and EEPROM Array Control Register Low-Power Modes Wait Mode Stop Mode Section 8. Central Processor Unit (CPU) 8.1 Contents Introduction Features CPU Registers Accumulator (A) Index Register (H:X) Stack Pointer (SP) Program Counter (PC) Condition Code Register (CCR) Arithmetic/Logic Unit (ALU) Low-Power Modes Wait Mode Stop Mode Technical Data MC68HC908AS60 Rev Table of Contents MOTOROLA

9 Table of Contents 8.7 CPU During Break Interrupts Instruction Set Summary Opcode Map Section 9. System Integration Module (SIM) 9.1 Contents Introduction SIM Bus Clock Control and Generation Bus Timing Clock Startup from POR or LVI Reset Clocks in Stop Mode and Wait Mode Reset and System Initialization External Pin Reset Active Resets from Internal Sources Power-On Reset (POR) Computer Operating Properly (COP) Reset Illegal Opcode Reset Illegal Address Reset Low-Voltage Inhibit (LVI) Reset SIM Counter SIM Counter During Power-On Reset SIM Counter During Stop Mode Recovery SIM Counter and Reset States Program Exception Control Interrupts Hardware Interrupts SWI Instruction Reset Break Interrupts Status Flag Protection in Break Mode Low-Power Modes Wait Mode Stop Mode MC68HC908AS60 Rev. 1.0 Technical Data MOTOROLA Table of Contents 9

10 Table of Contents 9.8 SIM Registers SIM Break Status Register SIM Reset Status Register SIM Break Flag Control Register Section 10. Clock Generator Module (CGM) 10.1 Contents Introduction Features Functional Description Crystal Oscillator Circuit Phase-Locked Loop Circuit (PLL) Circuits Acquisition and Tracking Modes Manual and Automatic PLL Bandwidth Modes Programming the PLL Special Programming Exceptions Base Clock Selector Circuit CGM External Connections I/O Signals Crystal Amplifier Input Pin (OSC1) Crystal Amplifier Output Pin (OSC2) External Filter Capacitor Pin (CGMXFC) Analog Power Pin (V DDA ) Oscillator Enable Signal (SIMOSCEN) Crystal Output Frequency Signal (CGMXCLK) CGM Base Clock Output (CGMOUT) CGM CPU Interrupt (CGMINT) CGM Registers PLL Control Register PLL Bandwidth Control Register PLL Programming Register Interrupts Technical Data MC68HC908AS60 Rev Table of Contents MOTOROLA

11 Table of Contents 10.8 Low-Power Modes Wait Mode Stop Mode CGM During Break Interrupts Acquisition/Lock Time Specifications Acquisition/Lock Time Definitions Parametric Influences on Reaction Time Choosing a Filter Capacitor Section 11. Configuration Register (CONFIG-1) 11.1 Contents Introduction Functional Description Section 12. Break Module 12.1 Contents Introduction Features Functional Description Flag Protection During Break Interrupts CPU During Break Interrupts TIM During Break Interrupts COP During Break Interrupts Low-Power Modes Wait Mode Stop Mode Break Module Registers Break Status and Control Register Break Address Registers MC68HC908AS60 Rev. 1.0 Technical Data MOTOROLA Table of Contents 11

12 Table of Contents Section 13. Monitor ROM (MON) 13.1 Contents Introduction Features Functional Description Entering Monitor Mode Data Format Echoing Break Signal Commands Baud Rate Security Section 14. Computer Operating Properly (COP) Module 14.1 Contents Introduction Functional Description I/O Signals CGMXCLK STOP Instruction COPCTL Write Power-On Reset Internal Reset Reset Vector Fetch COPD COPL COP Control Register Interrupts Monitor Mode Technical Data MC68HC908AS60 Rev Table of Contents MOTOROLA

13 Table of Contents 14.8 Low-Power Modes Wait Mode Stop Mode COP Module During Break Interrupts Section 15. Low-Voltage Inhibit (LVI) Module 15.1 Contents Introduction Features Functional Description Polled LVI Operation Forced Reset Operation False Reset Protection LVI Status Register LVI Interrupts Low-Power Modes Wait Mode Stop Mode Section 16. External Interrupt Module (IRQ) 16.1 Contents Introduction Features Functional Description IRQ Pin IRQ Module During Break Interrupts IRQ Status and Control Register MC68HC908AS60 Rev. 1.0 Technical Data MOTOROLA Table of Contents 13

14 Table of Contents Section 17. Serial Communications Interface (SCI) 17.1 Contents Introduction Features Pin Name Conventions Functional Description Data Format Transmitter Character Length Character Transmission Break Characters Idle Characters Inversion of Transmitted Output Transmitter Interrupts Receiver Character Length Character Reception Data Sampling Framing Errors Baud Rate Tolerance Receiver Wakeup Receiver Interrupts Error Interrupts Low-Power Modes Wait Mode Stop Mode SCI During Break Module Interrupts I/O Signals PTE0/SCTxD (Transmit Data) PTE1/SCRxD (Receive Data) I/O Registers SCI Control Register SCI Control Register SCI Control Register SCI Status Register Technical Data MC68HC908AS60 Rev Table of Contents MOTOROLA

15 Table of Contents SCI Status Register SCI Data Register SCI Baud Rate Register Section 18. Serial Peripheral Interface (SPI) 18.1 Contents Introduction Features Pin Name and Register Name Conventions Functional Description Master Mode Slave Mode Transmission Formats Clock Phase and Polarity Controls Transmission Format When CPHA = Transmission Format When CPHA = Transmission Initiation Latency Error Conditions Overflow Error Mode Fault Error Interrupts Queuing Transmission Data Resetting the SPI Low-Power Modes Wait Mode Stop Mode SPI During Break Interrupts I/O Signals MISO (Master In/Slave Out) MOSI (Master Out/Slave In) SPSCK (Serial Clock) MC68HC908AS60 Rev. 1.0 Technical Data MOTOROLA Table of Contents 15

16 Table of Contents SS (Slave Select) V SS (Clock Ground) I/O Registers SPI Control Register SPI Status and Control Register SPI Data Register Section 19. Modulo Timer (TIM) 19.1 Contents Introduction Features Functional Description TIM Counter Prescaler Low-Power Modes Wait Mode Stop Mode TIM During Break Interrupts I/O Registers TIM Status and Control Register TIM Counter Registers TIM Counter Modulo Registers Section 20. Input/Output (I/O) Ports 20.1 Contents Introduction Port A Port A Data Register Data Direction Register A Port B Port B Data Register Data Direction Register B Technical Data MC68HC908AS60 Rev Table of Contents MOTOROLA

17 Table of Contents 20.5 Port C Port C Data Register Data Direction Register C Port D Port D Data Register Data Direction Register D Port E Port E Data Register Data Direction Register E Port F Port F Data Register Data Direction Register F Port G Port G Data Register Data Direction Register G Port H Port H Data Register Data Direction Register H Section 21. Byte Data Link Controller-Digital (BDLC-D) 21.1 Contents Introduction Features Functional Description BDLC Operating Modes Power Off Mode Reset Mode Run Mode Wait Mode Stop Mode Digital Loopback Mode Analog Loopback Mode MC68HC908AS60 Rev. 1.0 Technical Data MOTOROLA Table of Contents 17

18 Table of Contents 21.5 BDLC MUX Interface Rx Digital Filter Operation Performance J1850 Frame Format Start-of-Frame Symbol (SOF) In-Message Data Bytes (Data) Cyclical Redundancy Check Byte (CRC) End-of-Data Symbol (EOD) In-Frame Response Bytes (IFR) End-of-Frame Symbol (EOF) Inter-Frame Separation Symbol (IFS) Break (BREAK) Idle Bus (IDLE) J1850 VPW Symbols Logic Logic Normalization Bit (NB) Break Signal (BREAK) Start-of-Frame Symbol (SOF) End-of-Data Symbol (EOD) End-of-Frame Symbol (EOF) Inter-Frame Separation Symbol (IFS) Idle J1850 VPW Valid/Invalid Bits and Symbols Invalid Passive Bit Valid Passive Logic Valid Passive Logic Valid EOD Symbol Valid EOF and IFS Symbols Idle Bus Invalid Active Bit Valid Active Logic Valid Active Logic Valid SOF Symbol Valid BREAK Symbol Message Arbitration BDLC Protocol Handler Protocol Architecture Rx and Tx Shift Registers Rx and Tx Shadow Registers Technical Data MC68HC908AS60 Rev Table of Contents MOTOROLA

19 Table of Contents Digital Loopback Multiplexer State Machine X Mode Receiving a Message in Block Mode Transmitting a Message in Block Mode J1850 Bus Errors Summary BDLC CPU Interface BDLC Analog and Roundtrip Delay BDLC Control Register BDLC Control Register BDLC State Vector Register BDLC Data Register Low-Power Modes Wait Mode Stop Mode Section 22. Timer Interface Module A (TIMA-6) 22.1 Contents Introduction Features Functional Description TIMA Counter Prescaler Input Capture Output Compare Unbuffered Output Compare Buffered Output Compare Pulse-Width Modulation (PWM) Unbuffered PWM Signal Generation Buffered PWM Signal Generation PWM Initialization Interrupts Low-Power Modes Wait Mode Stop Mode MC68HC908AS60 Rev. 1.0 Technical Data MOTOROLA Table of Contents 19

20 Table of Contents 22.7 TIMA During Break Interrupts I/O Signals TIMA Clock Pin (PTD6/ATD14/TCLK) TIMA Channel I/O Pins (PTF3 PTF0/TACH2 and PTE3/TACH1 PTE2/TACH0) I/O Registers TIMA Status and Control Register TIMA Counter Registers TIMA Counter Modulo Registers TIMA Channel Status and Control Registers TIMA Channel Registers Section 23. Analog-to-Digital Converter (ADC-15) 23.1 Contents Introduction Features Functional Description ADC Port I/O Pins Voltage Conversion Conversion Time Continuous Conversion Accuracy and Precision Interrupts Low-Power Modes Wait Mode Stop Mode I/O Signals ADC Analog Power Pin (V DDAREF )/ADC Voltage Reference Pin (V REFH ) ADC Analog Ground Pin (V SSA )/ADC Voltage Reference Low Pin (V REFL ) ADC Voltage In (ADCVIN) Technical Data MC68HC908AS60 Rev Table of Contents MOTOROLA

21 Table of Contents 23.8 I/O Registers ADC Status and Control Register ADC Data Register ADC Input Clock Register Section 24. Electrical Specifications 24.1 Contents Maximum Ratings Functional Operating Range Thermal Characteristics Volt DC Electrical Characteristics Control Timing ADC Characteristics Serial Peripheral Interface (SPI) Timing CGM Operating Conditions CGM Component Information CGM Acquisition/Lock Time Information Timer Module Characteristics Memory Characteristics BDLC Transmitter VPW Symbol Timings BDLC Receiver VPW Symbol Timings Section 25. Mechanical Specifications 25.1 Contents Introduction Pin Plastic Leaded Chip Carrier Package Pin Quad Flat Pack MC68HC908AS60 Rev. 1.0 Technical Data MOTOROLA Table of Contents 21

22 Table of Contents Section 26. Ordering Information 26.1 Contents Introduction MC Order Numbers Index Index Technical Data MC68HC908AS60 Rev Table of Contents MOTOROLA

23 Technical Data MC68HC908AS60 List of Figures Figure Title Page 1-1 MCU Block Diagram for the MC68HC08ASxx Emulator MC68HC908AS60 (52-Pin PLCC) MC68HC908AS60 (64-Pin QFP) Power Supply Bypassing Memory Map Control, Status, and Data Registers FLASH-1 Control Register (FLCR1) Smart Programming Algorithm FLASH-1 Block Protect Register (FLBPR1) FLASH-2 Block Protect Register (FLBPR2) FLASH-2 Control Register (FLCR2) Smart Programming Algorithm EEPROM-1 Control Register (EECR1) EEPROM-1 Non-Volatile Register (EENVR1) EEPROM-1 Array Control Register (EEACR1) EEPROM-2 Control Register (EECR2) EEPROM-2 Non-Volatile Register (EENVR2) EEPROM-2 Array Control Register (EEACR2) CPU Registers Accumulator (A) Index Register (H:X) Stack Pointer (SP) Program Counter (PC) MC68HC908AS60 Rev. 1.0 Technical Data MOTOROLA List of Figures 23

24 List of Figures Figure Title Page 8-6 Condition Code Register (CCR) SIM Block Diagram SIM I/O Register Summary CGM Clock Signals External Reset Timing Internal Reset Timing Sources of Internal Reset POR Recovery Interrupt Entry Interrupt Recovery Interrupt Processing Interrupt Recognition Example Wait Mode Entry Timing Wait Recovery from Interrupt or Break Wait Recovery from Internal Reset Stop Mode Entry Timing Stop Mode Recovery from Interrupt or Break SIM Break Status Register (SBSR) SIM Reset Status Register (SRSR) SIM Break Flag Control Register (SBFCR) CGM Block Diagram I/O Register Summary CGM External Connections PLL Control Register (PCTL) PLL Bandwidth Control Register (PBWC) PLL Programming Register (PPG) Configuration Write-Once Register (CONFIG-1) Break Module Block Diagram I/O Register Summary Break Status and Control Register (BSCR) Break Address Registers (BRKH and BRKL) Technical Data MC68HC908AS60 Rev List of Figures MOTOROLA

25 List of Figures Figure Title Page 13-1 Monitor Mode Circuit Monitor Data Format Sample Monitor Waveforms Read Transaction Break Transaction Monitor Mode Entry Timing COP Block Diagram COP Control Register (COPCTL) LVI Module Block Diagram LVI I/O Register Summary LVI Status Register (LVISR) IRQ Block Diagram IRQ I/O Register Summary IRQ Interrupt Flowchart IRQ Status and Control Register (ISCR) SCI Module Block Diagram SCI I/O Register Summary SCI Data Formats SCI Transmitter SCI Receiver Block Diagram Receiver Data Sampling Slow Data Fast Data SCI Control Register 1 (SCC1) SCI Control Register 2 (SCC2) SCI Control Register 3 (SCC3) SCI Status Register 1 (SCS1) Flag Clearing Sequence SCI Status Register 2 (SCS2) SCI Data Register (SCDR) SCI Baud Rate Register (SCBR) MC68HC908AS60 Rev. 1.0 Technical Data MOTOROLA List of Figures 25

26 List of Figures Figure Title Page 18-1 SPI I/O Register Summary SPI Module Block Diagram Full-Duplex Master-Slave Connections Transmission Format (CPHA = 0) Transmission Format (CPHA = 1) Transmission Start Delay (Master) Missed Read of Overflow Condition Clearing SPRF When OVRF Interrupt Is Not Enabled SPI Interrupt Request Generation SPRF/SPTE CPU Interrupt Timing CPHA/SS Timing SPI Control Register (SPCR) SPI Status and Control Register (SPSCR) SPI Data Register (SPDR) TIM Block Diagram TIM I/O Register Summary TIM Status and Control Register (TSC) TIM Counter Registers (TCNTH TCNTL) TIM Counter Modulo Registers (TMODH TMODL) I/O Port Register Summary Port A Data Register (PTA) Data Direction Register A (DDRA) Port A I/O Circuit Port B Data Register (PTB) Data Direction Register B (DDRB) Port B I/O Circuit Port C Data Register (PTC) Data Direction Register C (DDRC) Port C I/O Circuit Port D Data Register (PTD) Data Direction Register D (DDRD) Port D I/O Circuit Port E Data Register (PTE) Data Direction Register E (DDRE) Technical Data MC68HC908AS60 Rev List of Figures MOTOROLA

27 List of Figures Figure Title Page Port E I/O Circuit Port F Data Register (PTF) Data Direction Register F (DDRF) Port F I/O Circuit Port G Data Register (PTG) Data Direction Register G (DDRG) Port G I/O Circuit Port H Data Register (PTH) Data Direction Register H (DDRH) Port H I/O Circuit BDLC Block Diagram BDLC I/O Register Summary BDLC Operating Modes State Diagram BDLC Block Diagram BDLC Rx Digital Filter Block Diagram J1850 Bus Message Format (VPW) J1850 VPW Symbols with Nominal Symbol Times J1850 VPW Received Passive Symbol Times J1850 VPW Received Passive EOF and IFS Symbol Times J1850 VPW Received Active Symbol Times J1850 VPW Received BREAK Symbol Times J1850 VPW Bitwise Arbitrations BDLC Block Diagram BDLC Protocol Handler Outline BDLC Block Diagram BDLC Analog and Roundtrip Delay Register (BARD) BDLC Control Register 1 (BCR1) BDLC Control Register 2 (BCR2) Types of In-Frame Response (IFR) BDLC State Vector Register (BSVR) BDLC Data Register (BDR) TIMA Block Diagram TIMA I/O Register Summary MC68HC908AS60 Rev. 1.0 Technical Data MOTOROLA List of Figures 27

28 List of Figures Figure Title Page 22-3 PWM Period and Pulse Width Timer A Status and Control Register (TASC) TIMA Counter Registers (TCNTH and TCNTL) TIMA Counter Modulo Registers (TAMODH and TAMODL) TIMA Channel Status and Control Registers (TACC0 TASC5) CHxMAX Latency TIMA Channel Registers (TACH0H/L TACH3H/L) ADC Block Diagram ADC Status and Control Register (ADSCR) ADC Data Register (ADR) ADC Input Clock Register (ADICLK) SPI Master Timing Diagram SPI Slave Timing Diagram BDLC Variable Pulse-Width Modulation (VPW) Symbol Timing Technical Data MC68HC908AS60 Rev List of Figures MOTOROLA

29 Technical Data MC68HC908AS60 List of Tables Table Title Page 1-1 External Pins Summary Clock Source Summary Vector Addresses Charge Pump Clock Frequency Erase Block Sizes Charge Pump Clock Frequency Erase Block Sizes EEPROM Program/Erase Cycling Reduction EEPROM Array Address Blocks EEPROM Program/Erase Mode Select EEPROM Program/Erase Cycling Reduction EEPROM Array Address Blocks EEPROM Program/Erase Mode Select Instruction Set Summary Opcode Map Signal Name Conventions PIN Bit Set Timing Variable Definitions VCO Frequency Multiplier (N) Selection COP Time Clarification MC68HC908AS60 Rev. 1.0 Technical Data MOTOROLA List of Tables 29

30 List of Tables Table Title Page 13-1 Mode Selection Mode Differences READ (Read Memory) Command WRITE (Write Memory) Command IREAD (Indexed Read) Command IWRITE (Indexed Write) Command READSP (Read Stack Pointer) Command RUN (Run User Program) Command Monitor Baud Rate Selection LVIOUT Bit Indication Pin Name Conventions Start Bit Verification Data Bit Recovery Stop Bit Recovery Character Format Selection SCI Baud Rate Prescaling SCI Baud Rate Selection SCI Baud Rate Selection Examples Pin Name Conventions I/O Register Addresses SPI Interrupts SPI Configuration SPI Master Baud Rate Selection Prescaler Selection Port A Pin Functions Port B Pin Functions Port C Pin Functions Port D Pin Functions Port E Pin Functions Port F Pin Functions Port G Pin Functions Technical Data MC68HC908AS60 Rev List of Tables MOTOROLA

31 List of Tables Table Title Page 20-8 Port H Pin Functions BDLC J1850 Bus Error Summary BDLC Transceiver Delay BDLC Rate Selection BDLC Transmit In-Frame Response Control Bit Priority Encoding BDLC Interrupt Sources Prescaler Selection Mode, Edge, and Level Selection Mux Channel Select ADC Clock Divide Ratio MC Order Numbers MC68HC908AS60 Rev. 1.0 Technical Data MOTOROLA List of Tables 31

32 List of Tables Technical Data MC68HC908AS60 Rev List of Tables MOTOROLA

33 Technical Data MC68HC908AS60 Section 1. General Description 1.1 Contents 1.2 Introduction Features MCU Block Diagram Pin Assignments Power Supply Pins (V DD and V SS ) Oscillator Pins (OSC1 and OSC2) External Reset Pin (RST) External Interrupt Pin (IRQ) Analog Power Supply Pin (V DDA ) Analog Ground Pin (V SSA ) External Filter Capacitor Pin (CGMXFC) Port A Input/Output (I/O) Pins (PTA7 PTA0) Port B I/O Pins (PTB7/ATD7 PTB0/ATD0) Port C I/O Pins (PTC5 PTC0) Port D I/O Pins (PTD7 PTD0/ATD8) Port E I/O Pins (PTE7/SPSCK PTE0/TxD) Port F I/O Pins (PTF7 PTF0/TACH2) Port G I/O Pins (PTG2 PTG0) Port H I/O Pins (PTH1 PTH0) BDLC Transmit Pin (BDTxD) BDLC Receive Pin (BDRxD) MC68HC908AS60 Rev. 1.0 Technical Data MOTOROLA General Description 33